SWITCHING/DYNAMIC POWER

CONSUMPTION

Prof. Kaushik Roy

@ Purdue Univ.
 Switching Power

• Signal properties
– Signal probability, Pi, - probability of a signal being logic ONE
– Signal activity, ai, - probability of signal switching(0->1, or 1->0)

• Energy dissipated per transition

 
dvout
EVDD   iVDD (t )VDD dt  VDD  C L dt
0 0
dt
VDD

 C LVDD  dvout  C LVDD

2

0
  DD V
dvout
EC   iVDD (t )vout dt   C L vout dt  C L  vout dvout  C LVDD
2
/2
0 0
dt 0

2
Source: Intel
Energy dissipated for 1->0 or 0->1 transition: C LVDD /2

Prof. Kaushik Roy

@ Purdue Univ.
 Pdynamic = CL.VDD2.f

• Example
– 1.2m CMOS chip
– 100 MHz clock rate
– Average load capacitance of 30 fF/gate
– 5V power supply
• Power consumption/gate = 75 mW
• Design with 200,000 gates: 15W !
• Pessimistic evaluation: not all gates switch at the
full rate
• Have to consider the activity factor a: Effective
switching capacitance = aCL
Source: Intel

• Reducing VDD has a quadratic effect on Pdynamic

Prof. Kaushik Roy
@ Purdue Univ.
 Estimation of Average Number of Transitions

Switching at internal nodes depends on input signals.

Model input signals as stochastic process. Each signal having some properties:
- Signal probability
- Signal activity
Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.