SHORT-CIRCUIT POWER CONSUMPTION

Prof. Kaushik Roy

@ Purdue Univ.
 Direct Path Current

• Inputs have finite rise and fall times

• Direct current path from VDD to GND while PMOS and
NMOS are ON simultaneously for a short period

tr tf
VDD + Vtp

Vtn

Imax
Imean
t1 t2 t3
Psc = Imean.VDD
Prof. Kaushik Roy
@ Purdue Univ.
 Short-Circuit Power Consumption
Symmetrical Inverter without Load

 1 t2 1 t3 
I mean  2  I (t )dt   I (t )dt 
 T t1 T t2 
If Vtn = -Vtp=VT and n = p = 
and that the behavior around t2 is symmetrical
2 t2 
I mean  2  (Vin (t )  Vt ) 2 dt
T t1 2
VDD
with Vin (t )  t
tr
Vt
t1  .t r
VDD
Source: Intel tr
t2 
2
t r  t f  t rf Prof. Kaushik Roy
@ Purdue Univ.
 PSC cont’d

2 t rf / 2 VDD
 trf VT /VDD trf   2
I mean ( t Vt dt
)
T
t rf / 2
2  t rf VDD 
  (  t  Vt ) 
3

T  3VDD t rf  trf VT / VDD

2t rf  VDD
  (  Vt ) 3
3T VDD 2
t rf 
  (VDD  2Vt ) 3
12T VDD

Source: Intel  t
Psc  (VDD  2Vt ) 3 rf

12 T
Prof. Kaushik Roy
@ Purdue Univ.
 Short Circuit Current with Load

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.
POWER-CONSUMPTION DUE TO SPURIOUS
TRANSITIONS

Prof. Kaushik Roy

@ Purdue Univ.
 Spurious Transition at a Node

Hazardous transition occurs at the output of AND gate due

to different delays through two different paths converging
at the inputs to the AND gate.
- Assume each gate has unit delay
Source: Intel - Width of the glitch depends on the delays through
the logic gates and interconnects.
Prof. Kaushik Roy
@ Purdue Univ.