Pulsed Static Logic (PS-CMOS)

VDD INPUT3
VDD
CLK’ RESET LOW
1 CLK
1 5
0
2
DATA IN
INPUT 1 RESET HIGH RESET HIGH
3
CLK
4
INPUT2 INPUT 4
RESET HIGH RESET LOW

- High performance, skew transitions in a particular direction

- Good dynamic noise immunity
- Static circuit testability
- Cumbersome monotonic stage operation
- Complex clocking
 Clock Delayed Domino (CD Domino)
CLK

Q
A B

Delayed clock output

- Extreme process sensitivity

- Capability of inverting functions - Timing complexity
- Reduced chip clock overhead - Additional clk propagated
with logic
 Dual Rail Domino
Differential

Q Q’

PC
B B’

A A’

AND

- Complete logic family

 Cross-Coupled Domino

B B’

A A’

- Logically complete - Higher device count

- Enhanced noise immunity - Higher clock load
- High performance - Higher power