APPLICATION TO DSP:

LOW-POWER, UNEQUAL ERROR

PROTECTION, & ERROR RESILIENCY

Prof. Kaushik Roy

@ Purdue Univ.
When approximate is ‘good enough’

• Do few scratches make your car useless?

Prof. Kaushik Roy

@ Purdue Univ.
 When approximate is ‘good enough’

• Can you quantify the image quality visually?

Prof. Kaushik Roy

@ Purdue Univ.
 Error Resilient Applications: 20000ft view

• Error Resilient Applications: Produce acceptable outputs even

in the presence of imperfect implementation
• Can you spot the differences?
Input Image
Image
Segmentation
(Kmeans
Clustering)

Fully correct
computations

Application: Cancer
detection from
histological micrographs

10% erroneous computations 5% erroneous computations

Prof. Kaushik Roy
@ Purdue Univ.
 Low-Voltage DSP: Basic Idea

 All computations are “not equally important” for determining

outputs
 Identify important and unimportant computations based on
output “sensitivity”
 Compute important computations with “higher priority”
 Delay errors due to variations/ Vdd scaling “affect only”
non-important computations
 “Gradual degradation” in output with voltage scaling and
process variations

Prof. Kaushik Roy

@ Purdue Univ.
 Example: Low-Voltage Image Compression
8×8 blocks
JPEG Encoder Block Diagram
Source image X
T• Z • T '
Round
5 Paths
Q
Compressed
Z V Image Data
FDCT Quantizer Entropy
Encoder
512×512 image Z = T• X • T '

X W Transpose Y Z
1D DCT 1D DCT
Memory

 DCT is used in current international image/video coding standards

- JPEG, MPEG, H.261, H.263
Prof. Kaushik Roy
@ Purdue Univ.
 Energy Distribution of a 2D-DCT Output

1 2 6 7 15 16 28 29

3 5 8 14 17 27 30 43

4 9 13 18 26 31 42 44

10 12 19 25 32 41 45 54

11 20 24 33 40 46 53 55

21 23 34 39 47 52 56 61

22 35 38 48 51 57 60 62

36 37 49 50 58 59 63 64

High energy components (important outputs 75% energy)

Low energy components (less important outputs)
Can important components be computed with higher priority ?

Prof. Kaushik Roy

@ Purdue Univ.
 Design Methodology

x w w w1 w2 w3 w4 w4 w5
0
0
x w 8 6 4 2 0 8 6
1
x T.xt 1
w Faster
2 2
x w
3 1D-DCT 3
Computation
x w
4 w4
x Slower
5x 5w

6 6
Computation
x w
7 7
(a) Input Block (b) 1D- intermediate DCT outputs
z0
Computation

y
Computation

Computation

Computation
z1 0
y
Faster

z2 1y
Slower

Slower
Faster
2
z3 y3
z4 1D-DCT
y4
y5
y6
y7

(b)(d
Final DCT outputs (c)(c
Transpose Memory
) ) Prof. Kaushik Roy
@ Purdue Univ.
 Path Delays for 1D-DCT outputs
(x(0x+0 +x7x)7) dd
w0 ( x0 + x7 )  e + w2

(x3+ x4)  d
(2 adders
delay)
( x3+ x4)  e
( x1+ x6)  f
- (3 adders
delay)
( x0 + x7 )  f
(x2 + x5)  d ( x2 + x5)  f
+ w4 ( x3+ x4)  f
(x1+ x6)  d + -
<< -
(3 adders
delay)
( x3+ x4)  f
<< - w6

( x0- x7 )  a w1 (x + x ) f
1 6
<< + + (4 adders
delay)

( x1- x6)  a (3 adders

(x + x )e +
2 5
-
( x1- x6) e delay)
(x + x ) e
1 6 + - w3
( x2- x5) e (x - x ) a
0 7
(x - x ) a - (3 adders
( x1- x6)  f - (x - x )e +
2 5 delay)

( x3- x4)  f
<< 0 7

>> + w7 (x - x ) e
- -
( x2- x5) e +
3 4
(x - x ) f <<
<< -
0 7
(x - x ) f
2 5 >> + w5
( x2- x5)  a
(x - x ) e
+ 3 4
<<
( x3- x4)  a - - (x - x ) a
(4 adders
delay)
( x2- x5)  f <<
3 4
(x - x ) a +
1 6
- -
( x0- x7 )  f >> + (x - x ) f
3 4 <<
(x - x ) f
2 5 >> + Prof. Kaushik Roy
@ Purdue Univ.
 CRISTA-DCT under Vdd scaling
Proposed Design with high/low delay paths Scaled Vdd: Longer paths under Vdd scaling
w0 w0
w1 Important w1
Computations w2 D1
w2
w3 w3 @Vdd2
w4 Delay=D1 w4
w5 w5 D2 >D1
Paths Not
@ Vdd1
w6 Longer w6 @Vdd2 Computed
Delays
w7 w7

Extreme Scaled Vdd: Shorter paths affected

Only DC w0 D1 @Vdd3 Vdd3 < Vdd2 < Vdd1(nominal)

component w1
w2 D3 > D1
w3 @Vdd3
Paths Not
w4
Computed
w5 D4 >D1
w6 @Vdd3
w7
Prof. Kaushik Roy
@ Purdue Univ.
 1D-DCT Path Delay Comparisons

4
Conventional DCT Proposed DCT
3.5

3
Delay(ns)

2.5

1.5

0.5

0
Path1(w0)

Path4(w3)

Path5(w4)

Path7(w6)

Path8(w7)
Path2(w1)

Path3(w2)

Path6(w5)
Computation Paths

Prof. Kaushik Roy

@ Purdue Univ.