Fast Addition Techniques Using Hybrid Signed Digit
Number System
Reibhu Sant Abhilasha Gokhale
Maharaja Agrasen Maharaja Agrasen
Institute of Technology Institute of Technology
Rohini, New Delhi Rohini, New Delhi
reibhusant1@gmail.com abhilashagokhale6@gmail.com
ABSTRACT- Hybrid Signed Digit (HSD) is
the combination of conventional binary digit as
well as Redundant Binary Signed Digit (RBSD)
representation. Hybrid Signed Digits has
revolutionized the design of adders. It has made
adders faster than traditional adders and has
reduced propagation delay time. RBSD adders
are fast processors but have complex circuitry
with a high cost factor while conventional
binary adders like Ripple Carry Adder (RCA)
and Carry Look Ahead Adders (CLA) have
huge propagation delay times. HSD can be
implemented in different combinations of RBSD
and conventional binary and thus has
advantages of both. In HSD, some bits are
signed while the rest remain unsigned. With
such a design the carry propagation delay can
be limited to any desired value required. This
makes the circuitry less complex than RBSD
adder but the speed of operation is higher than
RCA or CLA adder. This paper aims to
compare the conventional adders (CLA and
RCA) as well as RBSD Adder. The adders are
compared in areas such as simplicity of design
and delay time. The design of the RBSD Adder
is implemented using verilog hardware
description language on Xilinx FPGA platform.
KEYWORDS—HSD, Signed Adders,
RBSD, fast adder, carry propagation, signed
digits, ripple carry adder, FPGA, verilogHDL.
I. INTRODUCTION
As an adder is the basic building block of a
multiplier, subtractor and divider, it is an integral
component of a digital system. Computer
arithmetic processes play a major role in many
applications such as signal processing,
cryptography, data analysis etc. Thus improving
performance of the adder would improve the
overall performance of the system.
Neelam Sharma
Maharaja Agrasen
Institute of Technology
Rohini, New Delhi
neelam_sr@yahoo.com
A parallel adder despite taking all the bits
concurrently doesn’t give out the output in a single
clock cycle. Carry propagation results in a varied
amount of propagation delay depending upon the
range of bits that are being computed. As most of
the operations that take place in an ALU happen
due to addition, be it multiplication by successive
addition or subtraction by addition using 2s
complement method, the time lost due to carry
propagation delay becomes crucial factor in
determining the speed of an ALU. Redundant
Binary Signed Digit number system reduces this
propagation delay by having the property of carry
free addition.[1] RBSD is unlike traditional binary
representation which uses more bits than needed to
represent a single binary digit, this results in more
than one way to represent a number and hence is
called redundant. The basic ripple carry adder
provides a fast operation for data having small size
but as the number of bits increase the time required
to yield the result also increases.
The time delay of Ripple carry Adder which is
directly proportional to the number of data bits i.e.
the time delay of the Ripple Carry Adder rises
exponentially as the number of data bits increase.
On the other hand, Redundant Binary Signed Digit
Adder maintains a constant time delay irrespective
of the number of data bits. It can be inferred that
for 4-bit operations ripple carry adder proves to be
faster than RBSD Adder. However, as the number
of bits increase which is the requirement of today’s
fast processors, RBSD Adder is the one which will
carry out fast computing.
In comparison RBSD adder cell takes a static
amount of time in order to yield the result thus
making it beneficial for computation of data of
large number of bits. Carry look ahead adder faces
irregular layout, and with increasing data bits its
circuit becomes more complex and expensive.[2]
Neelam Sharma put forward the adder cell design
using universal logic gates for fast addition.[6][3]
A novel hybrid number representation proposed by
Dhananjay S. Phatak[9] provides the algorithm to
formulate a variable carry propagation chain for TABLE 1: EXAMPLE 1: BINARY TO
addition purpose. This provides the designer with
the option of suiting the representation as per their
RBSD CONVERSION
design constraints. To find a middle way between
RBSD Adder and Ripple carry Adder, a hybrid Digit
signed digit adder can be formulated. Here, instead position 4 3 2 1 0
of all digits being signed, only some are signed
while the rest remain unsigned. With such a design
the carry propagation delay can be limited to any ai 0 1 0 0 1
desired value required. The maximum carry
propagation chain equals to (m+1) where m is the di 0 -1 0 0 -1
longest distance between neighbouring signed
digits. li 1 0 01 0
This paper discusses about RBSD number
system and conversion of binary numbers to RBSD Zi= di+ li 1 -1 0 1 -1
numbers and simulation results of RBSD adder in
section 2. Section 3 discusses HSD addition, B. RBSD to Binary Conversion
specifying the algorithm with examples. Section 4
shows the comparison between ripple carry adder, In order to convert RBSD number back to
carry look ahead adder, RBSD adder and HSD binary number, the following equation is used
adder over varying number of data bits. Finally in (5)
Zi = Z+ - Z-
section 5 the conclusion along with the
development of ALU using HSD number system
Here Z+ represents the RBSD number with all
employing the fast adder cell is briefly discussed.
the -1 replaced by 0 and Z- represents the RBSD
number with all 1 replaced by 0.
II. RBSD NUMBER SYSTEM
Avizienis(1961)[4] and Robertson(1959) are Subtraction of Z+ and Z- results in the
formation of the original binary number. An
credited with the formation of signed digit number example is shown in Table II.
system. The proposed method of addition put
forward by Avizienis led to a carry free addition TABLE 2: EXAMPLE 2: RBSD TO
process. In the traditional number system, each BINARY CONVERSION
digit can assume only r values where r being the Digit position 4 3 2 1 0
radix of the number system, r=10 for decimal Zi 1 0 - 1 -1
system, r=2 for binary. In RBSD number system, 1
Z+ 1 0 0 1 0
each digit can take more than r values. A signed
Z 0 0 - 0 -1
digit can take (2θ +1) values. 1
Binary 0 1 1 0 1
∑r= (-θ.. -1, 0, 1,..θ) (1)
III. HYBRID SIGNED DIGITS
A. Conversion To find a middle way between RBSD Adder and
Conversion from binary to RBSD takes place Ripple carry Adder, a hybrid signed digit adder can
with the help of following equations [5].
be formulated. Here, instead of all digits being
Step 1: For every conventional digit ai, we generate signed, only some are signed while the rest remain
an interim difference digit di. unsigned. With such a design the carry propagation
di = ai–r*li+1 (2) delay can be limited to any desired value required.
The maximum carry propagation chain equals to
Where r is the radix and li is (m+1) where m is the longest distance between
li+1 ={0 if ai< θ neighbouring signed digits.
{1 if ai>= θ
A. Addition of hybrid signed numbers
Step 2: Each digit of di and li are added together to
yield the binary number in RBSD form Addition of hybrid signed numbers is carried out in
two parts, the addition of the unsigned digits and
Zi = di + li (3)
the addition of signed digits. Let ai-1 and bi-1 be the
Here Zi is the RBSD representation for the binary unsigned digits to be added at the (i-1)th position
number. An example is shown in Table I with, and ci-1 be the carry out of the unsigned digits while
ci-2 be the carry into the unsigned digits. If it is
a = (9)10 = (1001)2 (4)
assumed that the carry into the (i-1)th can be (-1,0,1)
as a signed digit can be next to an unsigned. The
output oi-1 at the (i-1)th position is restricted to
(1,0). The following condition is followed to
achieve this.
If (ai-1 = bi-1 = 0 & ci-2 = -1) then
ci-1= -1 and oi-1 =1
else
(ai-1+ bi-1 + ci-2 = 2ci-1 + oi-1)
end
position. The fifth and sixth columns show the
values of Si and Ci for all possible combinations.
The carry generated out of the signed digit position
ripples through the unsigned all the way up to the
next higher order signed digit position. The
important thing to note is that the most significant
digit in any HSD representation must be a signed
digit in order to incorporate enough negative
numbers. It is upto the designer to incorporate as
many signed digits into the representation. The
addition time for any representation is determined
by the longest possible carry-propagation chain
between consecutive signed digit positions.

For signed digits a carry out and an intermediate B. Algorithm

sum is generated by the two input signed digits and
the two bits at the neighbouring lower order
unsigned digit position. Rules for selecting the
carry ci and intermediate sum si based on xi, yi, ai-1
and bi-1 are given in the following table. Here xi and
yi are signed digits and ai-1 and bi-1are unsigned
digits.
The following sets of steps are undertaken:
Step 1: Enter the hybrid signed digit operands
which need to be added.
Step 2: Separate the signed and unsigned digits.
Step 3: The parallel addition of signed digits is
performed with reference to the translation table
without carry propagation.

TABLE 3: TRANSLATION TABLE Step 4: The intermediate sum and carry for all
signed digit is saved.
FOR HSD
Step 5: The addition operation of unsigned digits is
Xi + Xi ai-1, bi-1 Ci-1 si Ci performed with reference to the addition constraint
of unsigned digits and the intermediate carry which
Yi Yi was saved earlier.
-2 -1 - X x 0 -1
Step 6: The values of intermediate sum of both
1 signed and unsigned are arranged in the right order.
-1 -1 0 ai-1 = bi-1 {-1,0} +1 -1
=0
-1 0 -1 At least {+1,0} -1 0
one of ai-
1, bi-1 is 1
0 -1 1 X x 0 0
0 1 -1 X x 0 0
0 00 X x 0 0
+1 0 1 ai-1 = bi-1 {-1,0} +1 0
=0
+1 1 0 At least {+1,0} -1 +1
one of ai-
1, bi-1 is 1
+2 11 X x 0 +1

In this table x denotes a ‘don’t care’. The first

column takes care of all possible sums of (Xi + Yi). Figure 1: Flow chart for HSD Addition
The second column mentions the individual value
that made the sum. The fourth column mentions the
possible values of carry into the signed digit
 C. Examples U13 U12 U9 U8 U5 U4 U1 U0
For the first example, it is assumed that positions of
0 1 0 1 0 1 0 1
signed and unsigned are alternate with the most
significant position being signed. Here Si represents 1 1 1 1 1 1 1 1
signed digit position, Ui represents unsigned digit
position and Z represents the sum. SUM 1 0 1 0 1 0 1 0

Addition of 8-bit HSD numbers CARRY 0 1 0 1 0 1 0 1

Example I: Alternate Signed and Unsigned digits Z = [0100010001000100] = (17476)10

S7 U6 S5 U4 S3 U2 S1 U0 Example II: Four unsigned digits are together

Xi [-1 1 0 1 1 0 -1 0]HSD (-42) S15 S14 S13 S12 U11 U10 U9 U8 S7 S6 S5 S4 U3 U2 U1 U0

Yi [1 1 -1 0 1 1 -1 0]HSD (170) Xi [-1 -1 -1 -1 1 1 0 0 -1 -1 -1 -1 1 1 0 0]HSD (-58596)

+ Yi [ 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1]HSD (62451)

+
S7 S5 S3 S1 U6 U4 U2 U0

-1 0 1 -1 1 1 0 0 S15 S14 S13 S12 S7 S6 S5 S4

1 1 1 -1 1 0 1 0 -1 -1 -1 -1 -1 -1 -1 -1

1 1 1 1 1 1 1 1
SUM 0 1 0 0 0 1 1 0

CARRY 0 0 1 -1 0 0 0 0 SUM 0 0 0 0 0 0 0 0

CARRY 0 0 0 0 0 0 0 0
Z = [1000000] = (128)10
U11 U10 U9 U8 U3 U2 U1 U0
Addition of 16-bit HSD numbers
1 1 0 0 1 1 0 0
For the second example, it is assumed that
positions of signed and unsigned are random with 0 0 1 1 0 0 1 1
the most significant position being signed.
SUM 1 1 1 1 1 1 1 1
Example I: Two unsigned digits are together
CARRY 0 0 0 0 0 0 0 0
S15 S14 U13 U12 S11 S10 U9 U8 S7 S6 U5 U4 S3 S2 U1 U0

Xi [-1 -1 0 1 -1 -1 0 1 -1 -1 0 -1 -1 -1 0 1]HSD (-48059) Z = [0000111100001111] = (3855)10

Yi [ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1]HSD (65535) Example III: Eight unsigned digits are together

+ S15 S14 S13 S12 S11 S10 S9 S8 U7 U6 U5 U4 U3 U2 U1 U0

Xi [-1 -1 -1 1 -1 -1 -1 -1 0 0 0 0 1 1 1 1]HSD (-65265)

S15 S14 S11 S10 S7 S6 S3 S2
Yi [ 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0]HSD (65535)
-1 -1 -1 -1 -1 -1 -1 -1
+
1 1 1 1 1 1 1 1
S15 S14 S11 S10 S7 S6 S3 S2
SUM 0 0 0 0 0 0 0 0
-1 -1 -1 -1 -1 -1 -1 -1
CARRY 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
SUM 0 0 0 0 0 0 0 0

CARRY 0 0 0 0 0 0 0 0

U13 U12 U9 U8 U5 U4 U1 U0

0 0 0 0 1 1 1 1

1 1 1 1 0 0 0 0

SUM 1 1 1 1 1 1 1 1 Figure 3: 4-bit Carry Look Ahead

Adder
CARRY 0 0 0 0 0 0 0 0
C. Comparison
Z = [0000000011111111] = (255)10 The RBSD adder displays a consistent time delay
over any number of input bits while Ripple Carry
IV. COMPARISON AMONG RIPPLE Adder displays a varying time delay with respect to
CARRY ADDER , RBSD ADDER, the input bit it processes. The delay in Ripple Carry
CARRY LOOK AHEAD ADDER AND Adder increases as the number of input bits
HSD ADDER . increase.

A. Ripple Carry Adder
A full adder circuit can be cascaded in parallel
to add an N-bit number. This results in a structure
where carry out of each full adder becomes the
carry in of the next full adder. Hence each carry bit
ripples across.
The time delay of Ripple carry Adder is directly
proportional to the number of data bits i.e. the time
delay of the Ripple Carry Adder rises exponentially
as the number of data bits increase. On the other
hand, Redundant Binary Signed Digit Adder
maintains a constant time delay irrespective of the
number of data bits as shown by the straight line. It
can be inferred that for 4-bit operations ripple carry
adder proves to be faster than RBSD Adder.
However, as the number of bits increase which is
the requirement of today’s fast processors, RBSD
Adder is the one which will carry out fast
computing.

Figure 2: 4-bit Ripple Carry Adder V. CONCLUSION

Ripple carry adder was simulated in Xilinx ISE to
yield the following results.
B. Carry Look Ahead Adder
A carry-look ahead adder (CLA) or fast adder is a
type of adder used in digital logic. A carry-look
ahead adder improves speed by reducing the
amount of time required to determine carry bits. It
can be contrasted with the simpler, but usually
slower, ripple carry adder for which the carry bit is
calculated alongside the sum bit, and each bit must
wait until the previous carry has been calculated to
begin calculating its own result and carry bits. The
carry-look ahead adder calculates one or more carry
bits before the sum, which reduces the wait time to
calculate the result of the larger value bits.
The signed digits in HSD adder go through
parallel addition in constant time as with the RBSD
adder and the unsigned digits have carry
propagation delay as in the Ripple Carry Adder. A
hybrid signed digit logarithmic number system
processor [10] made using appropriate radices by
taking into account both the speed of operations
and the memory storage requirements showcases
the benefit of having a mix of both signed and
unsigned digits.
An adder is an integral part of an arithmetic logic
unit (ALU). A multiplier can be made using the
RBSD and HSD adder as multiplication is nothing
but repeated addition. Subtraction is nothing but
addition using 2s complement method. An ALU
can be easily implemented using a RBSD and HSD
Adder. An ALU forms a basic building block of
many types of computing circuits, including the
central processing unit, floating point unit and Authors
graphics processing units (GPUs). A single CPU,
FPU or GPU may contain multiple ALUs.

If the speed of the adder is improved, it would

result in an ALU of higher computation speed and
Reibhu Sant is a fourth year student of Maharaja
hence would lead to faster processing.
Agrasen Institute of Technology, GGSIPU. He is
REFERENCES pursuing his Bachelors in Technology in the
Electronics and Communication Branch.
[1] Chow C. Y. and Robertson J. E. Logical
Design of a Redundant Binary Adder,
Proceedings of 4th Symposium on Computer
Arithmetic, pp. 109-115, 1978.

[2] R.UMA, Vidya Vijayan, M. Mohanapriya and

Sharon Paul, Area, Delay and Power
Comparison of Adder Topologies,
International Journal of VLSI design & Abhilasha Gokhale completed her B.E. (ECE) from
Communication Systems (VLSICS) Vol.3, Marathwada University, Aurangabad with
No.1, pp 153-168, February 2012.
distinction. She passed M.Tech. (EC) from Delhi
[3] Neelam Sharma, B.S. Rai and Arun Kumar College of Engineering, Delhi University. She has
Design of RBSD Adder and Multiplier Circuits presented 7 papers in National and International
for High Speed Arithmetic operations and their
Timing Analysis Advances in Computer Conferences. She has guided more than 45
Science and Engineering, Research in undergraduate students in their projects in the field
computing Science-23, pp 243-254, 2006.
of Microcontrollers and Embedded Systems. Her
[4] ALGIRDAS AVIZIENIS, ’Signed-Digit areas of interest include Computer Architecture,
Number Representations for Fast Parallel Switching Theory and Logic Design,
Arithmetic’ IRE TRANSACTIONS ON
ELECTRONIC COM-PUTERS,pp 389- Microprocessors and Microcontrollers and
401,1961. Embedded Systems.
[5] Neelam Sharma., Development of Fast RBSD
Arithmetic Logic Unit, Ph.D Thesis, U. P.
Technical University, Lucknow, India, 2006.

[6] Rakesh Kumar Saxena, Neelam Sharma and A.

K. Wadhwani., ’Fast Adder Design using
Redundant Binary Numbers with Reduced
Chip Complexity’, IACSIT International Neelam Sharma, passed her B.E. (EC) with
Journal of Engineering and Technology, Vol.3,
No.3, June 2011. honours from Thapar Institute of Engineering and
Technology, Patiala. She is a gold medalist of
[7] Somayeh Timarchi, Parham Ghayour, and GNDU, Amritsar. She did her M.Tech and Ph.D.
Asadollah Shahbahrami, ’A Novel High-Speed
Low-Power Binary Signed-Digit Adder ’, The from UPTU, Lucknow. She has guided 05
16th CSI International Symposium on Ph.Ds.and many M.Tech Dissertations and B.Tech
Computer Architecture and Digital Systems projects. The areas of her special interest are
(CADS 2012).
Computer Architecture, CAD, VHDL, VLSI
[8] A.A. El-Slehdar, A.H. Fouad, A.G. Radwan, Technology, VLSI Design and Nano Technology.
’Memristor based N-bits redundant binary She has published 74 papers in various Journals
adder’, IMicroelectronics Journal 46 (2015)
207213. and conference proceedings. She has five books to
[9] DS Phatak, I Koren, ‘Hybrid signed-digit her credit. She has been sanctioned many Research
number systems: A unified framework for
redundant number representations with Projects by World Bank, A.I.C.T.E. M.H.R.D and
bounded carry propagation chains’, IEEE GGSIPU.
Transactions on Computers, vol. 43, No. 8,
August 1994pp 880-891
[10] T Stouraitis, C Chen, ‘Hybrid signed digit
logarithmic number system processor’, IEEE
Proceedings E (Computers and Digital
Techniques) Volume 140, Issue 4, July 1993,
p. 205 – 210