 The above is the LSRX connector ,the first pin of C can be connected to shield.

 Inputs accepted are E1 and/or G703.10 2.048 MHz derived from an atomic clock.
 The guidelines in general, taking into account an inherent element of jitter involved because
of the pointer adjustment mechanism involved in SDH technology, are as follows:

 If available, use the T4 clock from the SDH transmission equipment, and connect it to the LSRX
input of RCHIS in the same manner as the OCB283 is synchronized with the atomic clock in the
BSNL network (for example, Hyderabad DTAX). The connection to the OCB283 is well known to
BSNL/MTNL.
 Else, use E1s derived from PDH, connected to LSR inputs on RCHIS.
 Else, with no other option available, connect only one SDH derived E1 input to the RCHIS(but
not recommended, for failure leads to loss of external synchronization).
Once synchronized even for a few moments, holdover mode ensures good functioning for at least
72 hours.

A quick check on RCHIS can be done by connecting only one E1,disconnecting all other E1s and
LSRX and looping this solitary E1 on the ICTRQ. Wait about half an hour, and check for no more than
an hour for synchronization, then put back through, to prevent calibration from getting spoilt.

Troubleshooting
 Replace RCHIS boards/ test RCHIS board on good site. If an RCHIS board syncs at one site but
fails at another, check the following:
 2048 khz +- 4.5 ppm---check with oscilloscope
 Only LSRs or LSRX should be used, use of both simultaneously should be avoided
 Jitter<.05 UI measured at 20 hz-100khz -----check with ANT-20 network analyzer.
 1-1.9 V peak at output port, with no more than 6db loss introduced by cable section----check with
oscilloscope.. comparing signal amplitude at output(clock) and input (RCHIS).
 Waveshape at output port must be in conformance with fig. 21/ G 703---check with oscilloscope.
 120 ohms impedence(not 75)—use a good balun; to check goodness of output without RCHIS
connected, terminate output with resistive 120 ohm load.
 Symmetrical pair connection--screen must be connected to earth on output side. At the input(7
pin connector, 80C and 110C ),on the left, pins 2 and 4 are shorted, and 1 connected to screen.
 On the right , pins 1 and 3 are connected to the symmetrical pair.
 If required, change the RCHIS power supplies and check(could affect the pulse shape if
degraded)
 High voltage cables crossing over/under the synchronizing cable can disturb the waveshape.
 Swap the RSIAS bouchons connected at 84 & 110 2B slots.
 Measure the Clock when it is directly connected to to the input slot of RCHIS.
 Both the LSRX input and the STM Clock source should have common earth.
 The Wander should also be within permissible limits.
 Check for the Loop impedance matching adapter at 101 slot
 The return Loss at 2.048 MHz should be > 15dB.
 The signal should be monotonic within the shaded area illustrated below (Fig 21 of G703)
 LSRX not getting synchronized usually relates to a node in free running mode even though
supposedly connected on the national ring(it should be in slave mode, with synchronizing port-
STM4 or STM16--- correctly specified ). Jitter tests on this clock can be carried out with ANT20
analyzer, while wander tests are to be carried out with,eg, Anaritsu Jitter demodulator(TEC
approved) with respect to a highly stable clock.
 The priority is always RCHIS0 first, and then RCHIS1 (within a board, it is always LSRS-LSR0-1-
2-3 in that order)so it is advisable, that once synchronized on LSRX, all E1 LSRs are to be
disconnected, else, if say, LSRX on RCHIS 0 is lost, sync will move to LSR0 even though LSRX
is available on RCHIS1.

T T T T T T
3 0 3 0 3 0 3 0 3 0 3 0

+ V

+ V 1

– V 1

T T T T – V
4 4 4 4

T
T 1 8 1 8 9 0 0 -9 2

S h a d e d a r e a in w h ic h T A v e r a g e p e r io d o f
s ig n a l s h o u l d b e s y n c h r o n iz in g s ig n a l
m o n o to n ic

F IG U R E 2 1 /G .7 0 3
W a v e sh a p e a t a n o u tp u t p o rt
Ambala site Wave Shape