ISSCC2018 30 Visuals

ISSCC
2018
SESSION 30
Emerging Memories
A N40 256KX44 Embedded RRAM Macro with SL-
Pre-charged SA and Low Voltage Write Current
Limiter to Improve Read and Write Performance
Chung-Cheng Chou, Zheng-Jun Lin, Pei-Ling Tseng, Chih-Feng Li,

Chih-Yang Chang, Wei-Chi Chen, Yu-Der Chih,
Tsung-Yung Jonathan Chang
TSMC
© 2018 IEEE 30.1: A N40 256KX44 Embedded RRAM macro with SL precharged SA and low voltage write current
International Solid-State Circuits Conference limiter to improve read and write performance 1 of 32
Outline
1.Basics of RRAM Operations
2.Low-Voltage Write Current Limiting Scheme

(LV-WCLS)
3.SL Pre-Charged SA
4.Silicon Data
5.Summary
Outline

(LV-WCLS)
3.SL Pre-charged SA
4.Silicon Data
5.Summary
Basic RRAM Operations
Set Reset
Fresh Sample V-forming Low Resistance State High Resistance State
BL 2.4V 1.4V 0V
TE TE TE TE
O2- Oxygen
Capping
vacancies
Hi-K
BE BE BE BE
WL 1V 1.3V 2.4V
SL 0V 1.4V
Cell Current Distribution
RESET SET
Variation: Process, Bias, etc
Tighter Distribution
Bit Count
Better endurance
Better retention
More read window
IR0 IR1
Cell Current
∆
Read Window
Self-Adaptive Write Scheme
FB
VDDH VDIO
VREF -
Verdict COMP Write Vref WR_VOL
+
DATA + OP2
Module Generator - IWRITE
RS SET
WEN
VWRITE
IWRITE
Fast Cell Slow Cell
1T1R
Prevent Fast cells from Over-Write,
[X.Xue, et al., JSSC ,2013] Save Write Power
Area, Power Penalty
Voltage Overhead = Vdsat+VDS
Current Limiter
VWRITE Specified Filament Size
Protect Fast Cells by Current Limiting
IWRITE Area Efficient
Icomp Voltage Overhead = Vdsat+VDS
1T1R
IWRITE
+
VDD Icomp
VD (300uA)
- VD
0.5V
Outline

(LV-WCLS)
3.SL Pre-Charged SA
4.Silicon Data
5.Summary
LV-WCLS: 2-Step Operation of Current Limiter
VWRITE SET_B
SET_B SW1
= <
Icomp SW2
1T1R
700
0.1V + 600
VD
N1 N3
- 500
+ 1 1-X X N4
ID (uA)
OP2 400
0.1V -
SW1 SW2 300
OP1 EN N2 N5 N6
200 SW1+SW2
100
0
Post-Delay, Td 0 0.1 0.2
VD (V)
LV-WCLS: Full Conduction Phase
VWRITE SET_B
SET_B SW1
= <
Icomp SW2
1T1R
700
0.1V + 600
VD
N1 N3
- 500
+ 1 1-X X N4
ID (uA)
OP2 400
0.1V -
SW1 SW2 300
OP1 EN N2 N5 N6
200 SW1+SW2
100
0
VD (V)
LV-WCLS: Partial Conduction Phase
VWRITE SET_B
SET_B SW1
= <
Icomp SW2
1T1R
700
0.1V + 600
VD
N1 N3
- 500
+ 1 1-X X N4
ID (uA)
OP2 400
0.1V -
SW1 SW2 300 SW1+SW2
OP1 EN N2 N5 N6
200
SW1
100
0
VD (V)
LV-WCLS: Write Termination
Td
VWRITE SET_B
SET_B SW1
= <
Icomp SW2
1T1R
700
0.1V + 600
VD
N1 N3
- 500
+ 1 1-X X N4
ID (uA)
OP2 400
0.1V -
SW1 SW2 300
OP1 EN N2 N5 N6
200 SW1
100
0
VD (V)
OP2: Latch-Type Voltage Comparator
Reuse Read SA
Area Saving VDD
Realize 0.1V Sensing CLK_B

Preset Response Time
CLK
40nS
0.1V
SW2
CLK
0.1V CLK
VD
SW2
VD
Performance of LV-WCLS
1000000 Tighten high bound to prevent over-

set due to current limiting
100000
Improve low bound due to the allowed
long stimulus pulse and post-delay
Bit Counts (a.u)
10000
Only 0.1V of voltage overhead
1000
LV_WCLS OFF
LV_WCLS ON
100
10
1
40 45 50 55 60 65 70 75
Cell Current (a.u.)
Voltage Overhead Comparison
VDDH VWRITE
+ VWRITE
IWRITE
IWRITE
SET_B
>800mV Icomp
+
- 1T1R 1T1R
-
VWRITE
IWRITE + +
VBIAS
100mV >500mV
1T1R
- -
Self-Adaptive Write Scheme This Work Conv. Current Limiter
Outline

(LV-WCLS)
3.SL Pre-charged SA
4.Silicon Data
5.Summary
Common-SL Architecture
 SL-Read: Better immunity from read disturb than BL-read
 Common SL
 Pros: Reduce SL resistance, feasibility to further shrink bit-cell
 Cons: Incur more capacitive load at SL node
SA
SA
SL Iref
SL Iref WL
WL BL
BL EQ1
EQ0
Icell Icell
Dedicated-SL (DSL) Common-SL (CSL)

Presented SL Pre-charged SA
Bias_gen VDD
VDD VDD VDD Pre-charger
Iref SW1
RDREF
+
SW2
- DOUT
VRSL + VCL RDI Latch SA
VCL -
VRD SE
SE
Read SA
BL0 CSL BL1
cmux_t
W_pre
VRSL_pre
VRSL
WL[0:1023]
Cell array
EQ1
EQ0 equalizer
cmux_b
Read SA Operation (1/3)
VDD
Standby VDD VDD Pre-charger
P3
 Read Path is Off (SE=“0”) P0 P1
 SW1 On, SW2 Off SW2 SW1
 SL & BL are Pre-Charged at VRSL RDI
 RDI/RDREF = VDD RDREF DO
N0
VCL N1
SE=0
0.3V (VRSL)
WL C_SL
VRD
0.3V (VRSL)
C_BL
VDD
Pre-charge VDD VDD Pre-charger
P3
 Reference branch is on (SE=“1”) P0 P1
 SW1 on, SW2 off SW2 SW1
 Cell branch connects to RDI Pre-Charger RDI
 RDI = VDD-VTH(P3) ~ RDREF RDREF DO
N0
VCL N1
~0.3V ~0.3V
SE=1
0.3V (VRSL)
WL C_SL
VRD
0.3V (VRSL)
Iref C_BL
Icell
VDD
Signal Development VDD VDD Pre-charger
P3
 Reference branch is on (SE=“1”) P0 P1
 SW1 off, SW2 on SW2 SW1
 Signal = RDI – RDREF RDI
 Latch-SA amplifies signal RDREF DO
N0
VCL N1
~0.3V ~0.3V
SE=1
0.3V (VRSL)
WL C_SL
VRD
0.3V (VRSL)
Iref C_BL
Icell
Waveform of the SA Operation
READ “1” This work READ “0”
Grounded SL
Tacc Tacc
Grounded-SL SE
Favor read “1”
Charge SL by cell current WL
Un-balanced read 58% improved
SW1
Precharged-SL
SL has been pre-charged
SW2
Discharge BL by VSS RDI
Balanced read RDREF
SL/BL SL SL
(This work) BL BL
SL/BL BL SL BL SL
(Grounded SL)
DOUT
Shmoo Plot: Tacc v.s. VRSL
 VRSL: Pre-Charged SL/BL Voltage Level
 Optimum VRSL Can Achieve Balanced Read 0 and Read 1
VRSL(V) V.S Tacc(ns) 5 6 7 8 9 10 11 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
0.28 . . . . P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P
Read 0 0.26 . . P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P
HB=24uA 0.24 . . . . . . . . . . . P P P P P P P P P P P P P P P P P P P P P P P P P P
Iref=25uA 0.22 . . . . . . . . . . . . . . P P P P P P P P P P P P P P P P P P P P P P P
∆ =1uA 0.2 . . . . . . . . . . . . . . . . P P P P P P P P P P P P P P P P P P P P P
0.18 . . . . . . . . . . . . . . . . . P P P P P P P P P P P P P P P P P P P P
VRSL(V) V.S Tacc(ns) 5 6 7 8 9 10 11 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Iref=27.6uA
Ir1 LB=30uA 0.22 . . P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P
∆ =2.4uA 0.2 . . . P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P
0.18 . . . . . . . . . P P P P P P P P P P P P P P P P P P P P P P P P P P P P
Shmoo Plot: Tacc v.s. VRSL
 9nS of Access Time can be achieved for both Read”0” and “1”, at
VRSL=0.26~0.28V, at VDD= 1.1V / 25C.
VRSL(V) V.S Tacc(ns) 5 6 7 8 9 10 11 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
HB=24uA 0.24 . . . . . . . . . . . P P P P P P P P P P P P P P P P P P P P P P P P P P
Iref=25uA 0.22 . . . . . . . . . . . . . . P P P P P P P P P P P P P P P P P P P P P P P
∆ =1uA 0.2 . . . . . . . . . . . . . . . . P P P P P P P P P P P P P P P P P P P P P
0.18 . . . . . . . . . . . . . . . . . P P P P P P P P P P P P P P P P P P P P
VRSL(V) V.S Tacc(ns) 5 6 7 8 9 10 11 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Iref=27.6uA
Ir1 LB=30uA 0.22 . . P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P
∆ =2.4uA 0.2 . . . P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P
0.18 . . . . . . . . . P P P P P P P P P P P P P P P P P P P P P P P P P P P P
Outline

(LV-WCLS)
3.SL Pre-charged SA
4.Silicon Data
5.Summary
Ir0/Ir1 Distribution after 1KC RAC at 25C
Endurance Test: Do SET/RESET cycling and check failure bit count for every Cycle
RAC (Retention After Cycles) : After Endurance Test, then bake the samples at 175C
for 11 hours, equivalent to 85C for 10 years.
1K cycles RAC @ 25ﾟC
Ir0>30uA FBC: 22
Ir1<42uA FBC: 0
BER: 0.008 PPM
14uA
Ir0/Ir1 Distribution After 1KC RAC at -40C
1K cycles RAC @ -40ﾟC
Ir0>30uA FBC: 0
Ir1<42uA FBC: 0
BER: 0 PPM
12uA
Ir0/Ir1 distribution after 1KC RAC at 125C
1K cycles RAC @ 125ﾟC
Ir0>30uA FBC: 117

Ir1<42uA FBC: 0
BER: 0.041 PPM
14uA
Die Photo and Key Parameters
Technology node 40nm CMOS logic

3600um
Supply 1.1V / 2.5V
Cell size 53F2
Die size (drawing) 3600um x 3600um
CFG registers &

2b-ECC logic
3600um
11Mb RRAM 256K x 44

Density
(32+12parity)
Macro
Architecture Common SL
Read speed (Tacc) 9ns
Read window after 1K RAC 12uA
Outline

(LV-WCLS)
3.SL Pre-charged SA
4.Silicon Data
5.Summary
Summary
LV-WCLS
 Tighter distribution of "1" current
 Reduce write operation voltage overhead by 400mV
 Area efficient
SL Pre-charged SA scheme

 58% improvement of Read speed
 Balanced Read for “0” and “1” at VRSL=0.28V
11Mb RRAM macro

 12uA current window after 85C/10years
 9nS access time at 3.4uA of read window
Thank You !
A 1Mb 28nm STT-MRAM with 2.8ns Read
Access Time at 1.2V VDD Using Single-
Cap Offset-Cancelled Sense Amplifier
and In-situ Self-Write-Termination
Qing Dong1,2, Zhehong Wang1, Jongyup Lim1, Yiqun Zhang1, Yi-Chun
Shih3, Yu-Der Chih3, Jonathan Chang3, David Blaauw1, Dennis Sylvester1
1University
of Michigan, Ann Arbor, MI
2TSMC, San Jose, CA
3TSMC, Hsinchu, Taiwan
© 2018 IEEE 30.02 : A 1Mb 28nm STT-MRAM with 2.8ns Read Access Time at 1.2V VDD Using
International Solid-State Circuits Conference Single-Cap Offset-Cancelled Sense Amplifier and In-situ Self-Write-Termination 1 of 57
Outline
 Motivation
 Read margin improvement
 Self-generated Vref
 Offset-cancelled sense amplifier
 Write power reduction

 In-situ self-write-termination
 Measurement Results
 Conclusion
Outline
 Motivation

 Conclusion
Memory Applications and Requirements
Many-Core Systems Mobile Systems IoT Systems
 Servers  Phones & Tablets  Sensor Nodes

 Scientific computing  Consumer devices  Auto-electronics
 Cloud data centers  Microcontrollers  Wearables
Challenges of Conv. Embedded Memories
SRAM DRAM Flash
 Large cell area  High refresh power  Scaling Issue

 High standby power  High write energy
 Limited Endurance
Introduction of STT-MRAM
BL Free Layer
MTJ Tunneling Barrier
WL Fixed Layer
SL RP RAP
 Compact area RAP
 Good scalability
 High performance
RP
 Good endurance
 Low write energy IW- IW+
STT-MRAM Read Challenge
Array0 at 20˚C
Frequency
RP RAP
 Limited read margin (RAP/RP≈2)
Array0 at 20˚C
Array0 at 120˚C
Margin degraded with
Frequency
temperature variation
RP RAP
 Degraded read margin at high temperature
Array0 at 20˚C Array1 at 20˚C
Margin degraded with
Frequency
array-to-array variation
RP RAP
 Degraded read margin at high temperature
 Array to array process variations
STT-MRAM Write Challenge
Write
Pulse
20˚C
RAP
RP
 Hundreds of μA are required to flip the cell
Write
Pulse
Write completion could change
20˚C with state and variation
RAP
RP
 Hundreds of μA are required to flip the cell

 Write completion could change with state and variation
Write
Pulse
Write completion could change
20˚C with state and variation
RAP
120˚C
RP
Write completion is earlier at
high temperature
 Hundreds of μAs are required to flip the cell
 Write completion could change with state and variation
 Write completion varies with temperature
Outline
 Motivation

 Conclusion
Variation Sources in Conventional SA VDD
VDD
OUT
Vclamp Vclamp
BL
Icell Iref
VDD
OUT
Vclamp Vclamp
BL
Icell Iref Reference
Reference PVT
PVT
Generation Variation
VDD
OUT
Vclamp Vclamp Voltage

Voltage
VtVtmismatch
Mismatch
Clamper
Clamper
BL
Reference PVT
PVT
VDD
PMOS
PMOS
Header Vtmismatch
Vt Mismatch
Header
OUT

Voltage
VtVtmismatch
Mismatch
Clamper
Clamper
BL
Reference PVT
PVT
VDD
PMOS
PMOS
Header Vtmismatch
Vt Mismatch
Header
Latch-based
Latch-based
InputOffset
Input Offset
SenseAmp
Sense Amp
OUT

Voltage
VtVtmismatch
Mismatch
Clamper
Clamper
BL
Reference PVT
PVT
Conventional Reference Generation
WL
Array0 at 20˚C Array1 at 20˚C
Array0 at 120˚C
Array
Frequency
BL
MUX 1/32
Sense Amplifiers
Ref RP Ref RAP

Ref Gen. w/ Golden Array
 Constant ref generated by golden array cannot finely track

process and temperature variation
Previous SA Works
ISSCC’08 JSSC’13 JSSC’16
Previous SA Works
ISSCC’08 JSSC’13 JSSC’16
 All previous offset-cancellation methods employed two or more caps,

inducing area overhead
Self-Reference
1Mb MRAM Macro
Generation
Vref ≈ 2Iread*(RP//RAP)
Level Converter WL
Pre-Decoder
Ref BLs BL[32] SL[32] BL[0] SL[0]

WL Driver
Decoder
Array
256 * (512+2)
WL
Ref BLs BL
Local MUX 1/32 RP RAP

Gen.
Ref
Timing Write Drivers

Control Sense Amplifiers Vref
Tracking Row-wise
Global Timing Control PVT Variation
Analog Voltage Generation
 Extra 2 reference columns in each array to generate read Vref tracking
row-wise PVT variation
 Less than 1% macro area overhead 30.02 : A 1Mb 28nm STT-MRAM with 2.8ns Read Access Time at 1.2V VDD Using
© 2018 IEEE
Proposed Sensing Scheme
Iref
Gen. X2 X1  Constant large current
Vbias_R
based fast voltage sensing
2Iread
Iread
S4
 Using PMOS headers as
S3R S3R current clamper instead of
S1 C0 S1 voltage clamper
S2R
S2R
S1B
Ref BLs
 Shared large-sized write driver

BL
S4
WL
as PMOS headers to alleviate
SL variation
RP RAP
Iref WL
Gen.
Vbias_R S1
S1B
2Iread
Iread
S2R
S4
S3R
S3R S3R S4
Offset
S1 VL C0 VR S1
S2R
S2R
Cancelling
S1B
Ref BLs
BL
S4
WL
SL
RP RAP
Iref WL
Gen.
Vbias_R S1
S1B
2Iread
Iread
S2R
S4
S3R
S3R VR-VL S3R S4
0 C0
Offset
S1 S1 Equalizing
S2R
S2R
Cancelling
S1B
Ref BLs
BL
S4
WL
SL
RP RAP
Iref WL
Gen.
Vbias_R S1
S1B
2Iread
Iread
S2R
S4
S3R
S3R Vref Vref +VR-VL VBL S3R S4
C0 Offset BL
S1 S1 Equalizing
S2R
S2R
Cancelling Sampling
S1B
Ref BLs
BL
S4
WL
SL
RP RAP
Iref WL
Gen.
Vbias_R S1
S1B
2Iread
Iread
S2R
S4
S3R
S3R S3R S4
C0 Offset BL
S1 S1 Equalizing Evaluating
S2R
S2R
Cancelling Sampling
S1B
Ref BLs
BL
S4
WL
SL
RP RAP
Iref WL
Gen.
Vbias_R S1
S1B
2Iread
Iread
S2R
S4
S3R
S3R S3R S4
C0 Offset BL
S1 S1 Equalizing Evaluating
S2R
S2R
Cancelling Sampling
S1B
Overlaps with decoding
Ref BLs
BL
S4
WL  Both offset cancelling and equalizing are

SL performed simultaneously with address
RP RAP
decoding, avoiding any timing penalty
Simulation Results
45
Conv. SA
Standard Deviation of
40
Offset Voltage (a.u.)

35
Proposed SA
30
25
20
15 >60% Offset Reduction
10
5
0 1 2 3 4 5 6 7 8 9 10 11
Transistors Size in SA (a.u.)
 Input offset is reduced by > 60%
 With only a single capacitor added, area of SA is reduced by 15%
compared to using dual capacitors 30.02 : A 1Mb 28nm STT-MRAM with 2.8ns Read Access Time at 1.2V VDD Using
© 2018 IEEE
Outline
 Motivation

 Conclusion
Read-Compare-Write & Write-Verify-Write
Read
 Hundreds of μAs current continuously applied
A Complete Write Cycle
on the cell, wasting power consumption

Compare
Write  Pros:
 Only write necessary bits, avoid redundant
Read write
 Verifying end of write avoids overwrite
End  Cons:
[ISSCC’16]  Multiple cycles are used for write
Proposed in-situ self-write-termination
Continuous read during write to perform

verify instead of interrupted write-read-write
A Complete Write Cycle
Write
Read
 Saving power without timing penalty

End
Detection of Write Completion
Write 1 Write 0
VDD VSS
 Current flows from BL to SL to write
1; from SL to BL to write 0
Iwrite1 Iwrite0
VH1 VH0
VL1 VL0
BL BL
RAP RP RP RAP
 BL voltage drops abruptly once write
WL WL
is completed in both write 0/1 cases
SL SL
VSS VDD
Proposed Write Scheme
Iref Vbias_W0  Shared sense amplifier
Gen.
Vbias_W1
Self-termination STOP Data
with read
S4
Iwrite
S3W S3W
Vref_W
S0
S0
S1 C0 S1
S2W
S2W
S1B
BL
S4
WL
SL
Data
Iref Vbias_W0
Gen.
Vbias_W1
S4
Iwrite
Vref_W
S3W S3W WL
S0
S0
S0
S1 C0 S1
S2W
S2W
S1
S1B
S2W
BL
S4
S3W
WL
SL
STOP
Data BL
Offset
Cancelling
Iref Vbias_W0
Gen.
Vbias_W1
S4
Iwrite
Vref_W
S3W S3W WL
S0
S0
VDD S0 VSS
S1 C0 S1
S2W
S2W
S1
S1B
S2W
BL
S4
S3W
WL
SL
STOP
Data BL
Offset Precharge
Cancelling
Iref Vbias_W0
Gen.
Vbias_W1
S4
Iwrite
Vref_W
S3W S3W WL
S0
S0
VDD S0 VSS
S1 C0 S1
S2W
S2W
S1
S1B
S2W
BL
S4
S3W
WL
SL
STOP
Data BL
Offset Precharge BL
Cancelling Developing
Iref Vbias_W0  Ends redundant write
Gen.
Vbias_W1
S4
Iwrite
Vref_W
S3W S3W WL
S0
S0
VSS S0 VDD
S1 C0 S1
S2W
S2W
S1
S1B
S2W
BL
S4
S3W
WL
SL
STOP
Data BL
Offset
Precharge BL In-situ Already
Cancelling Written
Developing Evaluating
Iref Vbias_W0  Ends redundant write
Gen.
Vbias_W1
Self-termination STOP Data  Avoid overwrite
S4
Iwrite
Vref_W
S3W S3W WL
S0
S0
VSS S0 VDD
S1 C0 S1
S2W
S2W
S1
S1B
S2W
BL
S4
S3W
WL
SL
STOP
Write is
Data BL Done
Offset Precharge BL In-situ Already
Cancelling Written
Developing Evaluating
Outline
 Motivation

 Conclusion
Chip Photos
600μm
28μm
Bank Bank Bank Bank
Iref Ctrl.
350μm
0 2 4 6
145μm
BIST
Gen.
Bank Bank Bank Bank
1 3 5 7
1Mb MRAM Macro

(0.214mm2)
 Taped out in TSMC 28nm embedded MRAM technology

 Macro area for 1Mb is 0.214 mm2
 Each array has 128kb 30.02 : A 1Mb 28nm STT-MRAM with 2.8ns Read Access Time at 1.2V VDD Using
© 2018 IEEE
Measured Read Results using Self-generated Vref
1E-0
1E-1
@120˚C
Read Fail Rate

1E-2
2.8ns 3.6ns
@25˚C @120˚C
1E-3
@25˚C
1E-4
1E-5 Zero Error Floor for

128kb Array
1.6 2.0 2.4 2.8 3.2 3.6

Read Access Time (ns)
 2.8ns and 3.6ns read access time at 25oC and 120oC to achieve
1E-5 error rate for a 128kb array, respectively
Measured Read Results across 8 arrays
Array[1:8] @25˚C w/ External Vref
1E-3
Read Fail Rate

1E-4
1E-5
Zero Error Floor
0.20 0.21 0.22 0.23 0.24 0.25 0.26

Vref (V)
1E-3
Optimal Fixed Vref
Read Fail Rate

across 8 Arrays
1E-4
1E-5
Zero Error Floor
0.20 0.21 0.22 0.23 0.24 0.25 0.26

Vref (V)
1E-3
Optimal Fixed Vref
Read Fail Rate

across 8 Arrays
1E-4
1E-5
2.2X
Self-Generated V ref Zero Error Floor
0.20 0.21 0.22 0.23 0.24 0.25 0.26

Vref (V)
 Self-reference generation tracks array-to-array variation,
improving read failure rate by 2.2×
Read Shmoo Plot
1.20 2.8ns
1.10
1.00
VDD (V) 0.90
0.80
0.70
0.60
3 4 5 6 7 8 9 10 20 100 200
Read Access Time (ns)
 2.8ns read access time at 1.2V and 25oC
 <0.6V VDD_min can be achieved
Measured VDD_min of SA
3 μ=0.57V
σ=0.019V
Die Count (#)

2
0
0.55 0.56 0.57 0.58 0.59 0.60
Measured SA VDD_min (V)
 With offset cancellation, the average VDD_min of SA is 0.57V with
19mV standard deviation across 10 dies
Measured Write Results for 1Mb Chip
80
(%)
Write (%)
68%
w/
1E-1 70
Ratiow/
Self-TerminationWrite
SavingRatio
61% 60
1E-2
Write Fail Rate

50
Self-Termination
47%
PowerSaving
1E-3
40
1E-4 30
Power
1E-5 20
Zero Error Floor 10

1E-6
for 1Mb Chip
0
0 5 10 15 20 25 30 35 40
Write Access Time (ns)
 Write access time must be > 20ns to achieve 1E-5 error rate
 Self-write-termination saves 47% write power for 20ns write cycle
Measured Write Power
10
w/o Self-Termination Write
9 w/ Self-Termination Write
8
Write Power (mW)

7 60%
6 Saving
47%
5
Saving
4
3
2
1 w/ 20ns Write Access Time
0
-20 0 20 40 60 80 100 120
Temperature (˚C)
 At high temperature, self-termination write saves more dynamic power
Comparison Table
This Work ISSCC’13 ISSCC’10 ISSCC’09 ISSCC’15 VLSI’13
Technology (nm) 28 40 65 90 65 65
Cell Type 1T1MTJ 1T1MTJ 1T1MTJ 2T1MTJ 2T2MTJ 2T2MTJ
Target Application NVM NVM NVM LLC1) LLC1) LLC1)
Cell Area (F2) 75 85 169 107
Capacity 1Mb 1Mb 64Mb 32Mb 1Mb 1Mb
Macro Area (mm2) 0.214 0.57 47.124 91.02 0.8196 0.628
Power Supply (V) 1.2/1.8 1.1/2.5 1.2 1.5 1.2/0.9/0.4 1.2/0.9/0.4
Word Length (bit) 16 32 16 32 256 256
Read Speed (ns) 2.8 10 30 12 3.3 4
Write Speed (ns) 20 30 12 3 4
Read Power (mW) 3.9 7.8 60 21.6 17.8
Write Power (mW) 3.6 9.3 91 55.4 46.5
1) MTJ cell in LLC applications do not require high retention, allowing low switching current MTJs
Comparison Table
Technology (nm) 28 40 65 90 65 65
Cell Area (F2) 75 85 169 107
Macro Area (mm2) 0.214 0.57 47.124 91.02 0.8196 0.628
Power Supply (V) 1.2/1.8 1.1/2.5 1.2 1.5 1.2/0.9/0.4 1.2/0.9/0.4
Word Length (bit) 16 32 16 32 256 256
Read Speed (ns) 2.8 10 30 12 3.3 4
Read Power (mW) 3.9 7.8 60 21.6 17.8
Write Power (mW) 3.6 9.3 91 55.4 46.5
Comparison Table
Technology (nm) 28 40 65 90 65 65
Cell Area (F2) 75 85 169 107
Macro Area (mm2) 0.214 0.57 47.124 91.02 0.8196 0.628
Power Supply (V) 1.2/1.8 1.1/2.5 1.2 1.5 1.2/0.9/0.4 1.2/0.9/0.4
Word Length (bit) 16 32 16 32 256 256
Read Speed (ns) 2.8 10 30 12 3.3 4
Read Power (mW) 3.9 7.8 60 21.6 17.8
Write Power (mW) 3.6 9.3 91 55.4 46.5
Comparison Table
Technology (nm) 28 40 65 90 65 65
Cell Area (F2) 75 85 169 107
Macro Area (mm2) 0.214 0.57 47.124 91.02 0.8196 0.628
Power Supply (V) 1.2/1.8 1.1/2.5 1.2 1.5 1.2/0.9/0.4 1.2/0.9/0.4
Word Length (bit) 16 32 16 32 256 256
Read Speed (ns) 2.8 10 30 12 3.3 4
Read Power (mW) 3.9 7.8 60 21.6 17.8
Write Power (mW) 3.6 9.3 91 55.4 46.5
Outline
 Motivation

 Conclusion
Conclusions
A 1Mb 28nm 1T1MTJ embedded STT-MRAM is presented
2.8ns read access time is achieved with self-reference generation

and offset-cancelled sense amplifier
With in-situ self-write-termination, write power is reduced by 47%

with 20ns write access time
Conclusions
A 1Mb 28nm 1T1MTJ embedded STT-MRAM is presented
2.8ns read access time is achieved with self-reference generation

and offset-cancelled sense amplifier
With in-situ self-write-termination, write power is reduced by 47%

with 20ns write access time
We thank TSMC for chip fabrication and support.

Thank You!
A 28nm 32Kb Embedded 2T2MTJ
STT-MRAM Macro with 1.3ns
Read-Access Time for Fast and
Reliable Read Applications
Tzu-Hsien Yang1,2, Kai-Xiang Li1,Yen-Ning Chiang1,

Wei-Yu Lin1, Huan-Ting Lin1, Meng-Fan Chang1
1National Tsing Hua University, Hsinchu, Taiwan,
2TSMC, Hsinchu, Taiwan
© 2018 IEEE 30.3 : A 28nm 32Kb Embedded 2T2MTJ STT-MRAM Macro with 1.3ns Read-Access Time for Fast and Reliable Read Applications
International Solid-State Circuits Conference 1 of 21
Outline
Introduction to STT-MRAM
Challenges of Conventional(CNV) Read Scheme
Proposed Continuous-Recording-and-Enhancement
VSA (CRE-VSA) Scheme
• Circuit structure
• Read operations
• Analysis
Measurement Results
Conclusion
Introduction to STT-MRAM
Many IoT and wearable devices require an eNVM for code memory
STT-MRAM is a good candidate for these applications:
• Fast speed  STT-MRAM
2T2M
• Low-voltage write 
• High endurance 
WL[n]
• Low TMR ratio 
• Read disturb  WL[n+1]
 Low read reliability
BL SL BLB SLB
 2T2MTJ can improve read performance, but it still face some
challenges in conventional-VSA scheme
Challenges of CNV Read Scheme-1
Pre-charge Developing Sensing
Turn on SAEN
The resistance of STT-MRAM is quite low *VOS: SA offset
VBL_RD *TSMW: Sensing window
• BL and BLB rapidly drop to ground RAP (VRSM>VOS)
BL/ BLB
• VRSM (VBL-VBLB) is decreasing after RP VSS
reaching its peak

Peak:VRSM_MAX
 Limited sensing window (TSMW) VRSM
(VBL-VBLB) VRSM decrease
If SAEN is out of the sensing window VOS
VSS
 Sensing fail TSMW

Developing time (TBL)
Challenges of CNV Read Scheme-2
Process variation makes this issue more
serious  Small sensing window
Low read voltage  Small VRSM
 Low sensing yield
Outline
Proposed Continuous-Recording-and-Enhancement VSA
(CRE-VSA) Scheme
• Read operations
• Analysis
Conclusion
Proposed CRE-VSA Scheme
Pre-charge/ Developing/ VBL_RD
Sensing
VTH Sampling CRE CNV-VSA ΔVIN Cell variation
- IN1/ IN2
Concept: VSS
VDD
Continuously enhance ∆VIN over TBL, despite
VRSM is decreasing after reaching its peak Proposed ΔVIN ΔVIN Continuous
CRE-VSA Enhancement
- IN1/ IN2
Feature: VSS
All Pass (Proposed)
• Continuous-Margin enhancement
1. Out of TSMW_CNV: Fail
• Variation tolerance in the input stage ΔVIN 2. Tail bit: Fail (CNV)
Peak:VRSM_MAX
(IN1-IN2)
VSS
• No timing overhead
TBL
 Improve sensing yield and read speed  TSMW_CNV
Improve Access time
CRE-VSA Operations- Standby Phase
Standby phase
• Reset all nodes to zero
Phase 1(P1)- VTH Sampling/ BL Pre-charge
P1 phase: VTH sampling
• VX1=VDD-VTH3  VTH is sampled on Cap.
• VX2=VDD-VTH4
VDD VDD
VBL_RD VBL_RD
Phase 2(P2)- CRE/ BL Developing-(T1)
P2 phase: Continuous-Recording and P1 P2 P3
VDD
CLK
Enhancement (CRE) (Time=T1) VSS
VDD
WL
• M3: VOD3=VS_BL VOD: Over-drive voltage (VGS-VTH) VSS
VBL_RD
BL/BLB
• M4: VOD4=VS_BLB VSS
VDD
 Variation tolerance INI VSS
VDD
PRE VSS
VDD VDD VDD
SAEN VSS
X1/X2
VDD VSS
VDD-VTH3-VS_BL VDD-VTH4-VS_BLB
IN1/IN2
ΔVIN > VS VSS
VDD
Q/QB
VS_BL VS_BLB VSS
T1 T2
30.3 : A 28nm 32Kb Embedded 2T2MTJ STT-MRAM Macro with 1.3ns Read-Access Time for Fast and Reliable Read Applications
Time
© 2018 IEEE
Phase 2(P2)- CRE/ BL Developing-(T2)
P2 phase: CRE (Time=T2)
• M3: VOD3=VS_BL (Saturation region)
• M4: VOD4=Negative (Sub-VTH region)
VIN2 keep in ~VDD
VDD-k*VS_BL ~VDD
∆VIN: IN voltage drop (VDD-VIN)
VS_BL VS_BLB
Phase 3(P3)- Sensing Phase
P3 phase: Sensing
• VIN1=VDD-k*VS_BL
Margin enhancement
• VIN2=~VDD
VDD-k*VS_BL ~VDD
Analysis: Tolerate Low TMR Ratio
CRE-VSA achieves 5.85x margin enhancement
TMRMIN of CRE-VSA is 5.6x~8x lower than that of CNV-VSA
Analysis: Tolerate Low Read Voltage
VBL_RD of CRE-VSA is 2x lower than that of CNV-VSA
Reduce read disturb rate by 106x and 34% lower I/O read energy
Analysis: Improve Read Speed
This work achieves 1.5x~1.86x read speed improvement in different
BL length  This work achieved the fastest read speed among
the reported STT-MRAM works
This work
Outline
Proposed Continuous-Recording-and-Enhancement VSA
(CRE-VSA) Scheme
• Read operations
• Analysis
Conclusion
Test-chip Summary
Technology 28nm CMOS Process
A 28nm 32kb STT-MRAM chip Device STT-MRAM
was fabricated Cell type 2T-2MTJ
0.18mm2 (including test-
Macro area
We implement CRE-VSA and modes and conventional
Capacity 32kb
CNV-VSA for comparison purpose Sub-array 256 columns x 64 rows
I/O widths 64 bits
Supply Voltage VDD=0.9V
Read Voltage V BL_RD=0.14V~0.3V
CRE-VSA (Proposed) and
Sense Amp options
CNV-VSA (Conventional)
Read speed CRE-VSA: 1.3 ns
@V BL_RD=0.3V Conventional: 1.86 ns
Read speed CRE-VSA: 2 ns
@V BL_RD=0.15V Conventional: Fail
Measured Read 209.6 fJ (@ V BL_RD=0.3V)
Energy (fJ/bit) 172.8 fJ (@ V BL_RD=0.15V)
Measurement Results-1
Use DFF methodology to measure the read latency (TAC)
This work achieved 1.3ns macro-level read access time
TAC
Measurement Results-2
Achieved 1.3ns read access time (1.43x faster than CNV-VSA)
Minimum VBL_RD: Improve 140mV @ 25oC, Improve 190mV @ 75oC
VBL_RD [mV]
Access time [ns]

Conclusion
We proposed CRE-VSA scheme to improve the read performance
 Feature:
1. Continuous-Margin enhancement
2. Variation tolerance in the input stage
3. No timing overhead
 Low TMR ratio tolerance (5.6x~8x lower than CNV-VSA)
 Low read voltage tolerance (2x lower than CNV-VSA)
 Reduce read disturb rate by 106x and reduce 34% I/O read energy
 Achieve 1.5x~1.86x read speed improvement
A 28nm 32kb STT-MRAM chip is verified
 Macro-level TAC: 1.3ns (1.43x faster than CNV-VSA)
 Minimum VBL_RD: 140mV (2x lower than CNV-VSA)
Thank you for your kind attention
Acknowledgements
NTHU-MDL
TSMC
MOST-Taiwan
A 20ns-Write 45ns-Read and
1014-Cycle Endurance Memory Module
Composed of 60nm Crystalline Oxide
Semiconductor Transistors
S. Maeda, S. Ohshita, K. Furutani, Y. Yakubo,
T. Ishizu, T. Atsumi, Y. Ando, D. Matsubayashi,
K. Kato, T. Okuda, M. Fujita*, S. Yamazaki
Semiconductor Energy Laboratory, Kanagawa, Japan
*The University of Tokyo, Tokyo, Japan
© 2018 IEEE
International Solid-State Circuits Conference 30.4: A 20ns-Write 45ns-Read and 1014-Cycle Endurance Memory Module Composed of 60nm Crystalline Oxide Semiconductor Transistors 1 of 22
Motivation
Performance required in LSI and memory for AI
–Low power consumption
• Low-power memory capable of long-term data retention
• Low energy for driving IOs
–High-performance processing
• Memory and architecture reducing data delay time
–High endurance
• Memory with high durability for more learning time
© 2018 IEEE
Motivation
Local memory architecture
Global memory architecture CMOS +
CMOS
Oxide Semiconductor
Chen, et al., Bong, et al., Logic
ISSCC2016 ISSCC2017 Memory
Memory
Processing
Engine (PE)
High data delay Low data delay Data retention w/o power
High energy for driving IOs Low energy for driving IOs Low area overhead
© 2018 IEEE
Outline
• Oxide Semiconductor (OS) Memory
• Design of OS Memory Module
• Measurement Results
• Summary
© 2018 IEEE
What Is OS Memory?
• Oxide semiconductor (OS): Novel channel material for FET
 C-Axis-Aligned Crystalline In-Ga-Zn Oxide
• Memory using OSFET’s ultralow off-state current
Arrhenius plot of off-state current
1T1C cell 2T1C cell
OSFET OSFET
© 2018 IEEE
What Is OS Memory?
• OS process is compatible with CMOS process.
• OS memory can be embedded in BEOL including access Tr.
1T1C Cell 2T1C Cell MIM
OS FET
OS FET
Si FET Si FET
Onuki, et al., VLSI2016 Ishizu, et al., VLSI2017

© 2018 IEEE
Memory Cell and Logic in BEOL
OSFETs can build memory cells and logic circuits.
MRAM / FeRAM / ReRAM OS Memory
Memory Cell Logic
Memory Cell Logic

© 2018 IEEE
Design Challenges and Solutions
• OSFET = NMOS only → Dynamic logic circuit
• Long readout time → Vt control with back gate,
Bootstrapping
OS dynamic logic circuit Vt control
10-3
1.E-03 VBG = -5V to 5V
10-5
1.E-05 W/L = 60nm/60nm
RT
ID (A)
10-7
1.E-07
10-9
1.E-09
10-11
1.E-11
10-13
1.E-13
-1 -0.5 0 0.5 1 1.5 2 2.5
VG (V)
© 2018 IEEE
OS Dynamic Logic Circuit
Normal operation is possible even applying power gating.
© 2018 IEEE
Test Chip Configuration
• 1 kb memory cell (3T1C) array with 32b access
• OS dynamic logic for drivers
© 2018 IEEE
© 2018 IEEE
© 2018 IEEE
© 2018 IEEE
Write Sequence of Memory Cell
• T1: Reset
– Fix WWL and WBL to 0V
• T2: Write
– Control access Tr. (M1) (0 V)
– Write data via WBL
logic-1
logic-0
VDD = 3.3 V
VH (control signal) = 5.0 V Write time
© 2018 IEEE
Write Sequence of Memory Cell
• T1: Reset
– Fix WWL and WBL to 0V
• T2: Write
– Control access Tr. (M1) (0 V)
– Write data via WBL
logic-1
logic-0
VDD = 3.3 V
VH (control signal) = 5.0 V Write time
© 2018 IEEE
Read Sequence of Memory Cell
• T1: Reset
– Fix RBL to 0V
– Fix OUT to 3.3V
• T2: Read
– Control selection Tr. (M3) (3.3 V)
– Control read Tr. (M2) with
SN voltage
logic-1
– Determine data of read logic-0
circuit with RBL voltage
VDD = 3.3V
VH(Control signal) = 5.0V Read time
© 2018 IEEE
(0 V)
Read Sequence of Memory Cell
• T1: Reset
– Fix RBL to 0V
– Fix OUT to 3.3V
• T2: Read
– Control selection Tr. (M3) (3.3 V)
– Control read Tr. (M2) with
SN voltage
logic-1
– Determine data of read logic-0
circuit with RBL voltage
VDD = 3.3V
VH(Control signal) = 5.0V Read time
© 2018 IEEE
(0 V)
Reduction of Read Time
• Lowered Vt of read transistors by back gate
• 33% reduction in read time by bootstrapping RBL
Typical, RT
w/o bootstrap w/ bootstrap 80
70
－33%
60
Read time (ns)

50
40
30
20
10
0
w/o bootstrap w/ bootstrap
© 2018 IEEE
Shmoo Plots
Write time: 20 ns, Read time: 45 ns (VDD = 3.3 V, RT)
© 2018 IEEE
Endurance
>1014-cycle endurance is achieved.
10-4
1.E-04 2.50
10-5
1.E-05
Logic-1
10-6
1.E-06 1.50
10-7
1.E-07 Logic-0
0.50
ISL (A)
Vt (V)
10-8
1.E-08
Logic-0
10-9
1.E-09
-0.50
10 -10
1.E-10
10 -11
1.E-11
-1.50
Logic-1
10 -12
1.E-12
10 -13
1.E-13 -2.50
1.E+00
0 1.E+02
2 1.E+04
4 1.E+06
6 1.E+08
8 1.E+10
10 1.E+12
12 1.E+14
-3 -2 -1 01 2 3 4 10 10 10 10 10 10 1410 10
VRWL (V) Write cycles
© 2018 IEEE
Die Photo and Comparison Table
• Standby power (RT) : 9.9 nW
• Write power (RT) : 97.9 μW/MHz
• Read power (RT) : 123.6 μW/MHz (CL=10fF)
[1] [2] This work

Memory Ferroelectric MTJ
Device OSFET
Logic CMOS CMOS
Technology (nm) 130 40 60
Supply voltage (V) 1.5 1.2 3.3/5.0
Density (bit) 512k 1M 1k
Frequency (MHz) 8 50 18
Endurance (cycle) - 1013 1014
Power (μW/MHz) >143 207 123.6
[1] Bartling, et al., ISSCC2013, [2] Lu, et al., IEDM2015
© 2018 IEEE
Summary
OS memory module characteristics
• Comparable performance with other emerging memories
• Fabricated only through BEOL process
Possibility of additional function to LSI
© 2018 IEEE

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Chung-Cheng Chou, Zheng-Jun Lin, Pei-Ling Tseng, Chih-Feng Li,

2.Low-Voltage Write Current Limiting Scheme

2.Low-Voltage Write Current Limiting Scheme

2.Low-Voltage Write Current Limiting Scheme

Realize 0.1V Sensing CLK_B

1000000 Tighten high bound to prevent over-

2.Low-Voltage Write Current Limiting Scheme

Dedicated-SL (DSL) Common-SL (CSL)

VRSL(V) V.S Tacc(ns) 5 6 7 8 9 10 11 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

VRSL(V) V.S Tacc(ns) 5 6 7 8 9 10 11 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

2.Low-Voltage Write Current Limiting Scheme

1K cycles RAC @ -40ﾟC

1K cycles RAC @ 125ﾟC

Ir0>30uA FBC: 117

Technology node 40nm CMOS logic

CFG registers &

11Mb RRAM 256K x 44

Read speed (Tacc) 9ns

Read window after 1K RAC 12uA

2.Low-Voltage Write Current Limiting Scheme

SL Pre-charged SA scheme

11Mb RRAM macro

3TSMC, Hsinchu, Taiwan

 Write power reduction

 Write power reduction

 Servers  Phones & Tablets  Sensor Nodes

 Large cell area  High refresh power  Scaling Issue

 Hundreds of μA are required to flip the cell

 Hundreds of μA are required to flip the cell

 Write power reduction

Vclamp Vclamp Voltage

Vclamp Vclamp Voltage

Vclamp Vclamp Voltage

Ref RP Ref RAP

 Constant ref generated by golden array cannot finely track

ISSCC’08 JSSC’13 JSSC’16

ISSCC’08 JSSC’13 JSSC’16

 All previous offset-cancellation methods employed two or more caps,

Ref BLs BL[32] SL[32] BL[0] SL[0]

Local MUX 1/32 RP RAP

Timing Write Drivers

 Shared large-sized write driver

WL  Both offset cancelling and equalizing are

Offset Voltage (a.u.)

 Write power reduction

on the cell, wasting power consumption

Continuous read during write to perform

 Saving power without timing penalty

Overlaps with decoding

Overlaps with decoding

Overlaps with decoding

 Write power reduction

1Mb MRAM Macro

 Taped out in TSMC 28nm embedded MRAM technology

Read Fail Rate

1E-5 Zero Error Floor for

1.6 2.0 2.4 2.8 3.2 3.6

Read Fail Rate

Zero Error Floor

0.20 0.21 0.22 0.23 0.24 0.25 0.26

Read Fail Rate

Zero Error Floor

0.20 0.21 0.22 0.23 0.24 0.25 0.26