Int. J. Electron. Commun.

(AEÜ) 65 (2011) 673–677

Contents lists available at ScienceDirect

International Journal of Electronics and

Communications (AEÜ)
journal homepage: www.elsevier.de/aeue

LETTER

0.65 V class-AB current-mode four-quadrant multiplier with reduced

power dissipation
C. Kasimis, C. Psychalinos ∗
University of Patras, Physics Department, Electronics Laboratory, GR-26504 Rio Patras, Greece

a r t i c l e i n f o a b s t r a c t

Article history: A class-AB CMOS current-mode four-quadrant multiplier with an improved biasing scheme is introduced
Received 31 May 2010 in this letter. Compared to the corresponding already published topology, the proposed multiplier offers
Accepted 4 October 2010 a significant reduction of power dissipation without increasing the circuit complexity. The behavior of
the proposed topology has been verified through simulation results using typical parameters of a 0.13 ␮m
Keywords: CMOS technology.
Analogue circuits
© 2010 Elsevier GmbH. All rights reserved.
CMOS integrated circuits
Multipliers
Low-voltage circuits

1. Introduction 2. Proposed configuration

Current-mode class-AB four-quadrant multipliers are very use- Let us consider the topology of the four-quadrant multiplier
ful blocks for performing analog signal processing, including introduced in [4], constructed form appropriately configured sinh-
telecommunication, gain control, instrumentation, and biomedical transconductors, denoted as S+ cells. This is recalled in Fig. 1 with
applications. The multipliers in [1–3] are formed by appropri- the following modification: the left side lowermost S+ cell that
ately interconnected current-mode squarer/divider blocks, which performs a split of the input current i2 is now biased at dc cur-
are realized by employing second generation current conveyors rent Ia , instead of current Io . As it will be proved in the next, the
(CCIIs) as active elements. The CCIIs are constructed from translin- expression for the output current is independent of the current Ia ,
ear loops realized by both nMOS and pMOS transistors operated in and this degree of freedom offers a significant reduction of power
strong inversion. An attractive four-quadrant multiplier topology is dissipation.
introduced in [4], where appropriately configured hyperbolic sine In order to facilitate our discussion, the sinh-transconductor
(sinh) transconductors have been employed. Thus, the exponen- employed in [4] is given in Fig. 2a. Its output current is given by
tial current–voltage relationship of MOS transistors in subthreshold (1) as
inversion has been utilized for realizing the corresponding multi-  

ˆ IN+ − ˆ IN−
plication function. Important features of the topology in [4] are the iout = 2Ibias sinh , (1)
nVT
construction of translinear loops from one type (pMOS) of transistor
and its modular structure.
An improved version of the multiplier in [4] is introduced in where  ˆ IN+ , 
ˆ IN− are the positive and negative input voltages, Ibias is
this letter. The main offered benefit is a significant reduction in the bias current, n is the subthreshold slope factor, and VT (∼ =26 mV)
power dissipation, without increasing circuit complexity. The let- is the thermal voltage [4,5].
ter is organized as follows: the improved scheme is presented in Thus, the left side uppermost S+ cell in Fig. 1, biased at dc current
Section 2, where the achieved reduction of power dissipation is ana- Io , performs a conversion of the input current i1 into a compressed
lytically discussed. The correct function of the multiplier has been voltage according to (2)
verified through simulation results in Section 3, where a compar-

ˆ − Vref
i 
= sinh−1
ison between the performance of the improved topology and that 1
. (2)
in [4] has been also performed. nVT 2Io

The left side lowermost S+ cell in Fig. 1 is configured in order to

perform a split of the current i2 . The corresponding transistor level
∗ Corresponding author. realization employed in [4] is depicted in Fig. 2b, where the pro-
E-mail address: cpsychal@physics.upatras.gr (C. Psychalinos). duced components i2p and i2n are given by the expressions in (3)

1434-8411/$ – see front matter © 2010 Elsevier GmbH. All rights reserved.
doi:10.1016/j.aeue.2010.10.001
674 C. Kasimis, C. Psychalinos / Int. J. Electron. Commun. (AEÜ) 65 (2011) 673–677

connected to the voltages  ˆ and Vref , using (1)–(4) the expression

of the output current is given by (5) as

i1 · i2
iout = K · (5)
Io

According to (5), the output current is independent of the bias

current Ia of the splitter. This is an important conclusion, not men-
tioned in [4] where all transconductors are biased at the same
current Io , and it will be used for reducing the power dissipation
of the multiplier by choosing Ia < Io instead of Ia = Io as in [4].
The power dissipation could be further reduced by modifying
the splitter given in Fig. 2b, as it is depicted in Fig. 3. Extra dc current
sources with a value KIbias have been added in order the right side
S+ cells to be biased at currents iA = Ki2p and iB = Ki2n , instead of
iA = K(Io + i2p ) and iB = K(Io + i2n ) as in [4].
Fig. 1. Class-AB four quadrant multiplier based on sinh-transconductors. According to (3) and (4) it is easily derived that at the quies-
cent point both the i2p and i2n components are equal to Ibias . Thus,
and (4), respectively: the power dissipation of each one of the right side S+ cells is now
 8KVDD Ia , instead of 16KVDD Io as in [4]. In other words, the power
i2 + i22 + 4Ibias
2
dissipation is halved, compared to that required for the correspond-
i2p = (3)
2 ing cells in [4]. With regards to the whole system, by employing the
 proposed concept concerning the value of the bias current Ia and
−i2 + i22 + 4Ibias
2
i2n = (4) the modification of the splitter topology, the total power dissipa-
2 tion is 8VDD (Io + 3Ia + KIa ). The corresponding value for the topology
In [4] the S+ cells in the right side of Fig. 1 are biased at currents in [4], where Ia = Io , is 8VDD Io (4 + K). Taking into account that Ia could
iA = K(Io + i2p ) and iB = K(Io + i2n ), where K is a scaling factor demon- be much smaller than Io it is obvious that the power dissipation is
strated in Fig. 2b. Due to the fact that their input terminals are significantly reduced compared to that in [4].

Fig. 2. Basic building blocks in [4]: (a) sinh-transconductor and (b) current splitter.
 C. Kasimis, C. Psychalinos / Int. J. Electron. Commun. (AEÜ) 65 (2011) 673–677 675

Fig. 3. Modified topology of the current splitter in Fig. 2a.

A useful comment concerning the topology in Fig. 1 is that it
could also be considered as a class-AB divider. This is achieved by
interchanging currents Io and i2 . Taking into account that the dc
bias current of each S+ cell must be strictly positive, a two-quadrant
divider is obtained, with an output current given by the expression
iout = Io (i1 /i2 ).
3. Simulation and comparison results
The performance of the modified multiplier topology has been
evaluated through simulation results, using MOS transistor models
provided by the 130 nm CMOS TSMC process and the Analog Design
Environment of the Cadence software. In order to achieve fair com-

Fig. 4. dc transfer characteristics of the multiplier.

Fig. 5. Time-domain behavior of the multiplier.

676 C. Kasimis, C. Psychalinos / Int. J. Electron. Commun. (AEÜ) 65 (2011) 673–677

Fig. 6. Linear performance of the multiplier with regards to the input i1 .

constant at a value 5 nA have been applied at the inputs of multi-

plier. Utilizing the periodic state space (PSS) analysis offered by the
Analog Design Environment of Cadence software, the derived total
harmonic distortion (THD) plot as a function of the amplitude of the
current i1 is given in Fig. 6. A THD level of about −30 dB has been
measured at an amplitude of i1 equal to 4.1 nA, which corresponds
to modulation index factor (MI ≡ i1 /Io ) equal to 8.2.
Also, the linear performance with respect to the second input of
the multiplier has been evaluated. Thus, a constant current i1 with
value 5 nA and a sinusoidal signal i2 with variable amplitude have
been applied. The same THD level as in the previous test has been
Fig. 7. Linear performance of the multiplier with regards to the input i2 . observed for an amplitude equal to 55.6 pA. Taking into account
that the bias of the splitter is equal to 5 pA, the achieved modulation
index factor is equal to 11.12 (Fig. 7).
In order to facilitate the discussion the most important perfor-
Table 1 mance factor of the proposed multiplier and that introduced in
Performance comparison results of the multiplier.
[4] have been summarized in Table 1. According to this table, the
Performance factor [4] Proposed proposed multiplier offers a significant reduction of the power dis-
Technology 0.13 ␮m CMOS 0.13 ␮m CMOS
sipation compared with that in [4], while both circuits have almost
Power supply 0.65 V 0.65 V the same number of active elements.
Bias currents Io = 0.5 nA Io = 0.5 nA, Ia = 5 pA
Power dissipation 12.4 nW 6.43 nW
4. Conclusion
Transistor count 60 62
M.I. of i1 @ THD −30 dB 10 8.2
M.I. of i2 @ THD −30 dB – 11.12 The proposed multiplier topology offers reduced minimum
power dissipation without using additional circuitry, compared to
the corresponding one already introduced in the literature. In addi-
parison results, the same bias scheme with that employed in [4] has tion, it is capable of operating in lower power supply voltages. All
been applied. Thus, the power supply voltages have been chosen as the above have been achieved at the expense of the reduction of its
VDD = 0.65 V and Vref = 450 mV. The aspect ratios were 4 ␮m/4 ␮m linear performance.
for transistors Mp1–4 , 1 ␮m/1 ␮m for Mp5–8 , 1 ␮m/10 ␮m for tran-
sistors Mp9–10 , 2 ␮m/4 ␮m for transistors Mp11–12 , 2 ␮m/2 ␮m for Acknowledgment
transistors Mn1–8 . The dc current sources have been realized by
nMOS transistors with aspect ratio 1 ␮m/10 ␮m. The authors would like to thank anonymous reviewers for their
Considering bias currents with values Io = 0.5 nA and Ia = 5 pA, valuable comments.
the dc power dissipation of the multiplier was 6.43 nW.
The dc transfer characteristics of the multiplier, at different val- References
ues of i2 , are given in Fig. 4 where the current i1 is varied within the
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The linear performance of the multiplier was evaluated by four-quadrant CMOS analog multiplier in current mode. Int J Electron Commun
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establishing conditions similar to those in [4]. For this purpose a [4] Sawigun C, Serdijn WA. Ultra-low power, class-AB, CMOS four quadrant current
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 C. Kasimis, C. Psychalinos / Int. J. Electron. Commun. (AEÜ) 65 (2011) 673–677 677

[5] Katsiamis AG, Glaros KN, Drakakis EM. Insights and advances on the Costas Psychalinos received the BSc degree in physics
design of CMOS sinh companding filters. IEEE Trans Circ Syst I 2008;55(9): and the PhD degree in electronics from the University
2539–50. of Patras, Patras, Greece, in 1986 and 1991, respectively.
From 1993 to 1995, he worked as post-doctoral researcher
Chrisostomos Kasimis received the MSc degree in elec- with the VLSI Design Laboratory at the University of Patras.
tronics in 2006 from the physics department, University From 1996 to 2000, he was an adjunct lecturer with
of Patras, Greece. He is currently a PhD student in the Elec- the department of computer engineering and informat-
tronics Laboratory working with the Analog Integrated ics at the University of Patras. From 2000 to 2004 he was
Circuits Design research group. His main research inter- an assistant professor with the Electronics Laboratory,
ests include the design of analog integrated companding Department of Physics, Aristotle University of Thessa-
filters and OTA-C filters. loniki, Thessaloniki, Greece. From 2004 to 2009 he was
an assistant professor and currently he is an associate
professor with the Electronics Laboratory, Department of
Physics, University of Patras, Patras, Greece. His research area is in the continu-
ous and discrete-time analog filtering, including companding filters, sampled-data
filters, current amplifier filters, CCII and CFOA filters, and in the development of
low-voltage active blocks for analog signal processing.