ANNA UNIVERSITY, CHENNAI APRIL/MAY 2014

Sub. Title : DIGITAL LABORATORY Sub. Code : CS6211

Degree: B.E Branch: CSE
Sem : 02 Duration: 3 hours
Max marks: 100 Regulations:R-2013

1. (a) Design & construct Half adder by using suitable logic gates & verify its truth table.
(b) Write a program for 4 bit up counter using verilog. Obtain RTL schematic and
necessary simulation waveforms.

2. (a) Design & construct Full Adder by using suitable logic gates & verify its truth table.
(b) Write a program for T flip flop using verilog. Obtain RTL schematic and necessary
simulation waveforms

3. (a) Design & construct Half Subtractor by using suitable logic gates & verify its truth table.
(b) Write a program for any one type of shift register using verilog. Obtain RTL schematic
and necessary simulation waveforms.

4. (a) Design & construct Full Subtractor by using suitable logic gates & verify its truth
table.
(b) Write a program for D flip flop using verilog. Obtain RTL schematic and necessary
simulation waveforms

5. (a) Implement F = ( AB + AB)(C + D ) using basic gates and verify its truth table.
(b) Write a program for JK flip flop using verilog. Obtain RTL schematic and necessary
simulation waveforms

6. (a) Design & construct BCD to excess-3 converter using suitable logic gates and verify
their truth table.
(b) Write a program for Half adder using verilog. Obtain RTL schematic and necessary
simulation waveforms.

7. (a) Design & construct excess-3 to BCD converter using suitable logic gates and verify
their truth table.
(b) Write a program for Full adder using verilog. Obtain RTL schematic and necessary
simulation waveforms.
8. (a) Design & construct four bit binary to gray code converter using suitable logic gates
and verify their truth table.
(b) Write a program for Multiplexer using verilog. Obtain RTL schematic and necessary
simulation waveforms

9. (a) Design & construct four bit gray to binary code converter using suitable logic gates and
verify their truth table.
(b) Write a program for De-Multiplexer using verilog. Obtain RTL schematic and necessary
simulation waveforms

10.(a) Design & construct 4 bit Binary adder/ subtractor using IC 7483
(b) Write a program for encoder using verilog. Obtain RTL schematic and necessary
simulation waveforms

11. (a) Design & construct 4 bit BCD adder/ subtractor using IC 7483
(b)Write a program for half adder using verilog. Obtain RTL schematic and necessary
simulation waveforms

12.(a) Design & construct 8 bit magnitude comparator using IC7485 and verify its operation.
(b) Write a program for full adder using verilog. Obtain RTL schematic and necessary
simulation waveforms

13.(a) Design & construct a 16 bit parity generator using logic gates using IC 74180.
(b)Write a program for T flip flop using verilog. Obtain RTL schematic and necessary
simulation waveforms

14. (a) Design & construct a 16 bit parity checker using logic gates using IC 74180
(b) Write a program for JK flip flop using verilog. Obtain RTL schematic and necessary
simulation waveforms

15. (a) Design & construct 4x1 Multiplexer & verify its truth table
(b) Write a program for decoder using verilog. Obtain RTL schematic and necessary
simulation waveforms.

16.(a) Design & construct 1x4 demultiplexer & verify its truth table
(b) Write a program for D flip flop using verilog. Obtain RTL schematic and necessary
simulation waveforms.
17. (a) Design & implement 4x2 Encoder & verify its truth table.
(b) Write a program for any one type of shift register using verilog. Obtain RTL schematic
and necessary simulation waveforms.

18. (a) Design & implement 2x4 decoder & verify its truth table.
(b) Write a program for 4 bit up counter using verilog. Obtain RTL schematic and
necessary simulation waveforms.

19. (a) Design an asynchronous/ripple 4-bit binary up counter using JK flip flops.
(b) Write a program for full subtractor using verilog. Obtain RTL schematic and
necessary simulation waveforms.

20. (a) Design an synchronous/parallel 4-bit binary up counter using JK flip flops.
(b) Write a program for Half subtractor using verilog. Obtain RTL schematic and
necessary simulation waveforms.

21. (a) Design & construct a 4 bit serial in serial out shift register.
(b) Write a program for decoder using verilog. Obtain RTL schematic and necessary
simulation waveforms

22. (a) Design & construct a 4 bit Serial in parallel out shift register.
(b)Write a program for Multiplexer using verilog. Obtain RTL schematic and necessary
simulation waveforms.

23. (a) Design & construct a 4 bit Parallel in serial out shift register.
(b) Write a program for De-Multiplexer using verilog. Obtain RTL schematic and
necessary simulation waveforms.

24. (a) Design & construct a 4 bit Parallel in parallel out shift register.
(b) Write a program for decoder using verilog. Obtain RTL schematic and necessary
simulation waveforms.

Marks allocation:
Design &Truth table& Procedure : 20
Circuit Diagram/Program : 20
Connection & Conduction : 40
Result : 10
Viva voce : 10
Total : 100