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Allen E.

Paulson College of Engineering

ENGR 2323 – Digital Design

Section-A

Lab 6

Muhammad Safwan
4545

Date Performed: March 10th, 2016

Submission Date: March 31, 2016


Lab 5 ENGR 2323 – Digital
Muhammad Safwan Design Lab

Abstract:
In this Lab we continue to experiment with the DE2 board, software Quartus 2, and the
VHDL design in Quartus 2. In this lab we continued to use VHDL combined with state
machines to control two separate trains on a track. For us, this was a harder challenge as we had
to use our previous knowledge of state machines and VHDL to solve the problem of allowing
both trains to run their routes without colliding with one another.

Introduction:
The lab was divided into two section, a pre-lab and the actual lab section. The pre-lab
portion of the lab was conducted before starting the actual lab. Once completing the steps for
pre-lab and lab portion of lab 6 we had a better understanding and knowledge of how a state
machine functioned as these state machines were used to control the train’s movement. We also
used previous knowledge from past labs to obtain the proper result for their train’s movement.

The pre-lab required us to read and study Chapter 8 of the textbook, viewing sections 8.1
through 8.5 to learn more about VHDL. After that we had to download the train path worksheets
off of the course website. After filling out their train path worksheet we build a UML state chart
which represents the proper movement of the trains. The UML and state table for each of the six
states for the train’s movement is provided at the end of this lab report.

VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language)
is a hardware description language. It is used in electronic design to describe digital and mixed-
signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also
be used as a general purpose parallel programming language. VHDL is great for creating
circuits, since we don’t have to actually design them anymore, we can just VHDL to create them.
This is especially great when you are dealing with a big circuit with a lot of gates.

Once the pre-lab was completed we had the materials and information to begin the in
class activities of the lab portion of the experiment. During this part of the lab, we took our
UML diagram and state machine table to create VHDL code implemented it into the DE2 board.
We got to discover a new feature involved with the Quartus 2 which was seeing that Quartus 2
can create graphics which in this labs case, displayed the two trains (Train A and Train B) and
the tracks the trains were on.

Methods:
In the lab we started off by completing the pre-lab steps. After completing the pre-lab
steps we then moved onto the lab steps. The lab steps required the completed pre-lab material in
order for the lab portion of the lab to be conducted. In lab 6, the pre-lab was a crucial part in
order for us to be able to complete the in class lab portion of the lab 6 experiment.

The pre-lab consisted of steps listed inside the lab manual. In these steps we had to read
and study Chapter 8, sections 8.1 through 8.5, of their text book in order to obtain a better
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Allen E. Paulson College of
Engineering
Lab 5 ENGR 2323 – Digital
Muhammad Safwan Design Lab

understanding of how the trains functioned. We were required to download the train paths
worksheet from the course website, which in our case we had to view the document. For our
train problem, we had to make train A move to sensor 5 and make train B move to sensor 2 at the
same time. Once each train reaches the sensor, the train then stopped, when both trains reached
their initial destination the trains were able to begin their next movements. This initial
movement is displayed in Figure 1 under the results section of the report. The next step in the
train’s movement was for Train A for train A to move forward (counter clock wise) around the
green arrows displayed in Figure 2. After train A completed its route displayed in Figure 2, train
B would then begin its route in Figure 3 which is highlighted with red arrows. After train B
completes its route train A than begins its route again. These two trains loop one another and
continue on these paths forever. After we created a UML and state table for the train’s paths we
than has completed the pre-lab portion of lab 6.

After completing the prelab we had the materials required to move on with the final steps
from the lab manual. In these steps we created the state machine VHDL code for the train’s
movement paths. After making sure their code is correct and functions the same way as
described in the train assignment document found on the course website. The way the trains are
supposed to move is displayed in Figures 1, 2, and 3. We then checked to see if our VHDL code
was correct by implementing the VHDL code into the DE2 board and then connected the DE2
board to a monitor which displayed a similar image found in Figure 5. The DE2 board was
connected to the monitor using a VGA monitor cable. We used the DE2 board to control the
train’s speed with the DE2 board’s switches, while the VHDL code functioned as the train’s
controller, making the trains follow their designated routes. We used DE2 board’s KEY1 to start
the train’s simulation and used the DE2 board’s KEY2 to reset the simulation to where the trains
were back at their original positions. We completed the lab portion of the lab 6 after we got our
trains to move in the described paths in Figures 1, 2, and 3.

Results:
.

Figure 1: Starting paths of train A


and B

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Allen E. Paulson College of
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Lab 5 ENGR 2323 – Digital
Muhammad Safwan Design Lab

Figure 2: Path of train B

Figure 3: Path of train B

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY Tcontrol IS
PORT(reset, clock, sensor1, sensor2 : IN std_logic;
sensor3, sensor4, sensor5, sensor6 : IN std_logic;
switch1, switch2, switch3, switch4 : OUT std_logic;
dirA, dirB : OUT std_logic_vector(1 DOWNTO 0));
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Allen E. Paulson College of
Engineering
Lab 5 ENGR 2323 – Digital
Muhammad Safwan Design Lab

END Tcontrol;

ARCHITECTURE a OF Tcontrol IS
TYPE STATE_TYPE IS (ABmoving,Amoving,Bmoving,Astop,Bstop,Bmoving_1);
SIGNAL state : STATE_TYPE;
SIGNAL sensor25, sensor12 : std_logic_vector(1 DOWNTO 0);

BEGIN
PROCESS (clock, reset)
BEGIN
-- Reset to this state
IF reset = '1' THEN
state <= ABmoving;
ELSIF clock'EVENT AND clock = '1' THEN
-- Case statement to determine next state
CASE state IS
WHEN ABmoving =>
CASE Sensor25 IS
WHEN "00" => state <= ABmoving;
WHEN "01" => state <= Astop;
WHEN "10" => state <= Bstop;
WHEN "11" => state <= Amoving;
WHEN OTHERS => state <= Amoving;
END CASE;

WHEN Amoving =>


CASE Sensor25 IS
WHEN "00" => state <= ABmoving;
WHEN "01" => state <= Bmoving;
WHEN "10" => state <= Amoving;
WHEN "11" => state <= Bmoving;
WHEN OTHERS => state <= Bmoving;
END CASE;

WHEN Bmoving =>


CASE Sensor12 IS
WHEN "00" => state <= Bmoving;
WHEN "01" => state <= Amoving;
WHEN "10" => state <= Bmoving_1;
WHEN "11" => state <= Bmoving;
WHEN OTHERS => state <= Bmoving;
END CASE;
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Allen E. Paulson College of
Engineering
Lab 5 ENGR 2323 – Digital
Muhammad Safwan Design Lab

WHEN Astop=>
CASE Sensor25 IS
WHEN "00" => state <= ABmoving;
WHEN "01" => state <= Bmoving;
WHEN "10" => state <= Amoving;
WHEN "11" => state <= Amoving;
WHEN OTHERS => state <= Amoving;
END CASE;

WHEN Bstop=>
CASE Sensor25 IS
WHEN "00" => state <= ABmoving;
WHEN "01" => state <= Astop;
WHEN "10" => state <= Bstop;
WHEN "11" => state <= Amoving;
WHEN OTHERS => state <= Amoving;
END CASE;

WHEN Bmoving_1=>
CASE Sensor12 IS
WHEN "00" => state <= Bmoving_1;
WHEN "01" => state <= Amoving;
WHEN "10" => state <= Bmoving_1;
WHEN "11" => state <= Bmoving;
WHEN OTHERS => state <= Bmoving;
END CASE;

END CASE;
END IF;
END PROCESS;

-- combine bits for case statements above


-- "&" operator combines bits
Sensor25 <= sensor2 & sensor5;
Sensor12 <= sensor1 & sensor2;

-- These outputs do not depend on the state

-- Outputs that depend on state


WITH state SELECT
Switch1 <= '0' WHEN ABmoving,
'1' WHEN Bmoving,
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Allen E. Paulson College of
Engineering
Lab 5 ENGR 2323 – Digital
Muhammad Safwan Design Lab

'0' WHEN Amoving,


'0' WHEN Astop,
'0' WHEN Bstop,
'0' WHEN Bmoving_1;
WITH state SELECT
Switch2 <= '0' WHEN ABmoving,
'0' WHEN Bmoving,
'0' WHEN Amoving,
'1' WHEN Astop,
'0' WHEN Bstop,
'1' WHEN Bmoving_1;
WITH state SELECT
Switch3 <= '1' WHEN ABmoving,
'0' WHEN Bmoving,
'1' WHEN Amoving,
'0' WHEN Astop,
'1' WHEN Bstop,
'0' WHEN Bmoving_1;
WITH state SELECT
Switch4 <= '1' WHEN ABmoving,
'0' WHEN Bmoving,
'1' WHEN Amoving,
'1' WHEN Astop,
'1' WHEN Bstop,
'0' WHEN Bmoving_1;
WITH state SELECT
DirA <= "10" WHEN ABmoving,
"00" WHEN Bmoving,
"01" WHEN Amoving,
"00" WHEN Astop,
"10" WHEN Bstop,
"00" WHEN Bmoving_1;
WITH state SELECT
DirB <= "01" WHEN ABmoving,
"01" WHEN Bmoving,
"00" WHEN Amoving,
"01" WHEN Astop,
"00" WHEN Bstop,
"01" WHEN Bmoving_1;
END a;
Figure 4: VHDL code

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Allen E. Paulson College of
Engineering
Lab 5 ENGR 2323 – Digital
Muhammad Safwan Design Lab

Figure 5: Trains display

Discussion:
After completing the lab’s UML diagram, the state table for the state machine, and
creating the VHDL state machine code on Quartus 2 the lab was finished. The train’s initial
movement is found in Figure 1. The movements for train A are found in Figure 2. The
movements for train B are found in Figure 3. The VHDL code for both the train’s movements are
show in Figure 4. The image produced by the DE2 board with assistance from the Quartus 2
software of the train diagram graphics is displayed in figure

In the pre-lab and lab, we used our previous knowledge from past labs to create a state
machine for both the train’s movements. We than created the UML chart attached at the end of
the lab report which describes the VHDL code that controls both the train’s movement. This
VHDL code is displayed in Figure 4. The results from Lab 6 allowed us to implement real world
situations where our skills and knowledge can be used to solve real world problems. The result
from lab 6 is that both train’s A and B move on their correct paths without colliding, with each
train looping another, forever.

Conclusion:
After completing the lab, we discovered how to create the VHDL state machine code
(Figure 4) for the train’s paths. We obtained a better understanding of how state machines
function in terms of real world situations and how useful these can be to our society. We
obtained information that gave us insight on real world problems that can be solved by
implementing state machines.

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Allen E. Paulson College of
Engineering
Lab 5 ENGR 2323 – Digital
Muhammad Safwan Design Lab

References:
Rapid Prototyping of Digital Systems, SOPC Edition, Hamblem, Hall and Furman, Springer
2008.

Digital Design Laboratory Manuel, Furman, Hall, Collins, and Twigg, 2nd Ediiton, Kendell
Hunt. 2009.

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