Multi Vt 7T Sram Cell for high speed application At
45 Nm Technology
Shyam Akashe
Assistant Professor
Institute of Technology & Management
Gwalior,India
vlsi.shyam@gmail.com
Sanjay Sharma
Associate Professor
Thapar University,
Patiala,India
sanjay.sharma@thapar.edu
Abstract- The trend of decreasing device size and increasing
chip densities involving several hundred millions of transistors
per chip has resulted in tremendous increase in design
complexity. Low power SRAMs are essential in today's demand
as they are preferred as on chip memories with read write
stability. This paper presents a method based on multi-Vt to
increase read, write stability and reduce the total leakage power
dissipation of SRAMs while maintaining their performance. The
proposed method is based on the observation that read and write
delays of a memory cell in an SRAM block depend on the
physical distance of the cell from the sense amplifier and it is also
depend on Vt.
Keywords- read and write stability, Leakage Power, multiple Vt.
I. INTRODUCTION
In recent years the demand for low power devices has been
increases tremendously. This demand may be due to fast
growth of battery operated portable applications such as PDAs,
cell phones, laptops & other handheld devices. But also at the
same time problems arising from continuous technology
scaling have recently made power reduction an important
design issue for the digital circuits and applications. CMOS
scaling beyond the 90nm technology node requires not only
very low threshold voltages (Vt) to retain the device switching
speeds to maintain the current drive and keep threshold voltage
variations under control when dealing with short-channel
effects [1]. The increased importance of power is even more
noticeable for a new class of energy constrained systems. As
sub-threshold circuits can allow ultra-low power designs to be
fabricated on modem process technology. Sub threshold
operation is applicable to wide range of applications ranging
from wireless devices, biomedical applications, spacecraft
applications etc. The leakage power dissipation is roughly
proportional to the area of a circuit. Since in many processors
caches occupy about 50% of the chip area [2]. Lowering
supply voltage to reduce power consumption is one of the
choice of the designers for designing low leakage SRAM
circuits. However ultra-low power design of high density
978-1-4673-0074-21111$26.00 @2011 IEEE
Mayank Shastri
M-TECH VLSI
Institute of Technology & Management
Gwalior,India
mayank vlsi@yahoo.com
_
SRAMs in which the operating voltage is below the transistor
sub threshold is extremely challenging. Also by the system
integration point of view, SRAM must be compatible with sub­
threshold combinational logic, operating at ultra-low voltages.
Ultra-Dynamic Voltage Scaling (U-DVS) is another approach
to reduce energy consumption by adjusting the system supply
voltage over a large range, depending on the performance
requirement. U-DVS is suitable for systems with time-varying
throughput constraint.
On the other hand, many of these techniques result in
hardware overhead and hence increase chip's area and reduce
the manufacturing yield. Furthermore, many of them try to
reduce the subthreshold leakage current only, whereas for sub-
100nm technology node, the tunneling gate leakage is
comparable to the subthreshold leakage. In this paper we
present a method for reducing both subthreshold and tunneling
gate leakage current of an SRAM by using different threshold
voltages and oxide thicknesses for transistors in an SRAM cell.
The idea is to deploy different configurations of six-transistor
SRAM cells corresponding to different threshold voltage and
oxide thickness assignments for the transistors [3,4].
II. 6 TRANSISTOR (6T) CELL
A different cell design that eliminates the above limitations
is the use of a CMOS flip-flop. In this case,the load is replaced
by a PMOS transistor. This SRAM cell is composed of six
transistors, one NMOS transistor and one PMOS transistor for
each inverter, plus two NMOS transistors connected to the row
line. This configuration is called a 6T Cell. Figure I shows this
structure. This cell offers better electrical performances (speed,
noise immunity,standby current) than a 4T structure.
The main disadvantage of this cell is its large size. Until
recently, the 6T cell architecture was reserved for niche
markets such as military or space that needed high immunity
components. However, with commercial applications needing
faster SRAMs, the 6T cell may be implemented into more
widespread applications in the future.
351
 B. Sub threshold Leakage

Sub threshold leakage is the drain-source current of a

transistor when the gate-source voltage is less than the
threshold voltage. More precisely, sub threshold leakage
happens when the transistor is operating in the weak inversion
region. The sub threshold current depends exponentially on
threshold voltage,which results in large subthreshold current in
short channel devices.

C. Gate Tunneling Leakage

Electrons (holes) tunneling from the bulk silicon through

the gate oxide into the gate results in gate tunneling current in
an NMOS (PMOS) transistor. Gate tunneling current is
composed of three major components: (1) gate to source and
gate to drain overlap current, (2) gate to channel current,part of
which goes to source and the rest goes to drain, and (3) gate to
substrate current. In bulk CMOS technology, the gate to
substrate leakage current is several orders of magnitude lower
than the overlap tunneling current and gate to channel current.
On the other hand, while the overlap tunneling current
Figure 1. 6T SRAM Cell
dominates the gate leakage in the OFF state, gate to channel
tunneling dictates the gate current in the ON condition. Since
the gate to source and gate to drain overlap regions are much
III. LEAKAGE CURRENT COMPONENT smaller than the channel region, the gate tunneling current in
the OFF state is much smaller than gate tunneling in the ON
The leakage current of a deep submicron CMOS transistor state.
consists of three major components: junction tunnelling
current, sub threshold current, and gate tunnelling current, as
shown in fig.2. IV. 7T DUAL VT SRAM CELL
The circuit schematic of the 7T dual-Vt SRAM cell with
transistors sized for a 45nm CMOS technology is shown in
Fig.3. The cross-coupled inverters formed by the transistors
NI, PI, N2, and P2 store a single bit of information. The write
bitline WBL and the pass transistor N3 are used for transferring
new data into the cell [5]. Alternatively, the read bitline RBL
and the transistor stack formed by N4 and N5 are used for
reading data from the cell. Two separate control signals R and
Ware used for controlling the read and the write operations,
respectively,with the 7T SRAM circuit as shown in Fig.3

Figure 2. Leakage currents

A. Junction Tunnelling Leakage

The reversed biased p-n junction leakage has two main

components: one is minority carriers' diffusion near the edge of
the depletion region and the other is due to electron-hole pair
generation in the depletion region of the reverse biased
junction. The junction tunnelling current is an exponential
function of junction doping and reverse bias voltage across the Figure 3. Proposed 7T dual Vt SRAM
junction.

All results presented in this section are obtained by

Cadence virtuoso simulations using a predictive 45nm

352
technology with 1.1V for the supply voltage, O.l8V for the
threshold voltage. Moreover, unless otherwise stated, it is
asswned that the value of the high threshold voltage is 0.28V
and the value of the thicker gate oxide is 14A. The Si02 layer
in the gate stack is assumed to be 2 A thicker than the thin
oxide so as to achieve one order of magnitude reduction in
tunnelling gate leakage. All simulations are performed at a die
temperature of 100°C.
V. POWER REDUCTION MECHANISMS USING MULTIPLE
VOLTAGE (MULTI-VDD)
B. Writability
The write-trip voltage is a measure of the writability of an
SRAM cell [9]. The write-trip voltage is the highest voltage on
the bit-line, which can still flip the SRAM cell content. A
higher value for the write-trip voltage represents ease of
writability, but the write-trip voltage should be sufficiently
lower than the supply voltage so noise cannot cause a write
failure or a write during a read operation [9]. The write-trip
voltage is mainly determined by the pull-ups' ratio of the cell
[10].

Multiple voltage (multi-VDD) techniques have been VII. SIMULAnON RESULTS

explored as attractive methods for behavioral- and RTL-Ievel To study the efftciency of the proposed technique, we
dynamic power minimization. Moreover, multiple threshold performed extensive simulations. To reduce the simulation
(multi-VTh) options have been proposed for the reduction of time, all simulations were done on a simplified version of the
subthreshold current There are two dominant subthreshold memory circuit comprising only of elements in the read/write
leakage paths in a 6T SRAM cell: path of a cell; this included the critical path of the decoder, all
1) Vdd to ground paths inside the SRAM cell and cells in corresponding row and column of the SRAM array, the
corresponding pre-charge devices, column multiplexers, sense
2) The bit-line (or bit-bar line) to ground path through the amplifiers, write drivers, and the output buffer. The read write
pass transistor. stability shown in figure 4 and leakage current shown in figure
To reduce the first type of leakage, the threshold voltages 5.
of the pull-down NMOS transistors and/or pull-up PMOS
transistors can be increased, whereas to lower the second type Tranlienl ResPQnse ofn
of leakage, the threshold voltages of the pulldown NMOS 12
�
transistors and/or pass transistors can be increased. If the ,7
L! Ldr"r
\ H,I
../
threshold voltage of the pull up PMOS transistors is increased, >2
�
·.2
the write delay increases while the effect on the read delay
would be negligible.

VI. STABILITY

The Static Noise Margin (SNM) of a CMOS SRAM cell is

defined as the minimum DC noise voltage necessary to flip the
state of a cell [6]. SRAM cells are especially sensitive to noise
during a read operation because the "0" storage node rises to a
voltage higher than ground due to a resistive voltage divider
comprised of the pull-down NMOS transistor and the pass
transistor. If this voltage is high enough, it can change the 100 200
cell's value. To design an HCS as robust as the conventional time(ps)

SRAM, only configurations that do not degrade the SNM Figure 4. read, write waveform of proposed 7T SRAM cel
should be used during design.

A. Read Stability
Trb.nsient Relponse oflT

The read stability is a transient stability metric which

specifies the likelihood of inverting an SRAM cell's stored
value during a read operation [7]. It is typically computed as
the ratio of Itrip/Iread, where Itrip is the current through the
pulldown NMOS transistor on the "0" side of the cell when the
state of the cell is inverted by an external current ltest injected
i
I
at the node storing the "0" value. Notice that Iread is the
maximum current through the pass-transistor during the read
operation [8]. The larger the Itrip/Iread ratio, the higher the
read stability of a cell is. The read stability simulation results
on NICS configurations are reported in Table V. From this
table, it is seen that for different configurations in NICS, the
time "M)
maximwn reduction in Itrip/Iread is 7.1%.
Figure 5. Leakage curren! waveform of 7!

353
 32.6% also reduce area of cell by using 45 nm technology
and it is 3.79 /lm2 this shows in fig. 6.
Figure 6. Layout of 7T SRAM
VIII. CONCLUSION
As low leakage SRAM will continue be in demand due to
rise in battery operated portable applications and also due to
continuous scaling of CMOS. Also area and cell stability
should be taken care while optimizing the power reduction. So,
new approach involved to reduce the leakage power and
maintain the read-write stability. This technique can be
implemented in various SRAM transistor cells which overall
increase the performance. The Dual Vt mechanism techniques
discussed in this paper will work for lower technology till
32nm. By applying the proposed technique to a SRAM in
45nm technology, the read write stability increase by 21% with
total leakage power dissipation of the SRAM has been reduced
by up to 32.6%.
354
ACKNOWLEDGMENT
This work was supported by ITM University Gwalior, with
collaboration Cadence Design System Bangalore.
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