5 4 3 2 1

VCC

D D
R6 R5
330 330

VCC
D1 D2
VCC TX RX DB9 MALE
VCC
U1 R3
1 28 U2 2K2 5
GND VCC
2 P0[7]/AI AI/P0[6] 27 9
3 P0[5]/AIO AI/P0[4] 26 1 R VCC 8 4
4 P0[3]/AIO AI/P0[2] 25 2 RE B 7 8
5 P0[1]/AI AI/P0[0] 24 3 DE A 6 3
6 P2[5] P2[4] 23 4 D GND 5 7
C 7 P2[3]/AI AI/P2[2] 22 2 C
8 21 R4 6
P2[1]/AI AI/P2[0] 75176 2K2
9 P1[7]/SCL P1[6] 20 1
10 P1[5]/SDA P1[4] 19
11 P1[3] P1[2] 18
SCL 12 17 SDA P1
P1[1]/SCL SDA/P1[0]
13 VSS VDD 16 VCC
14 D+ D- 15
HEADER 2

A 1
B 2
R1
27R
VCC J3
J1
B R2 B
1
2 D-
3 D+
4 27R VCC
J2
USB PORT
1
2
3
SCL 4
SDA 5

PROGRAMMER

A A

Title
<Title>

Size Document Number Rev

A <Doc> <RevCod

Date: Tuesday, April 22, 2008 Sheet 1 of 1

5 4 3 2 1