Beruflich Dokumente
Kultur Dokumente
Features
· Operating voltage: 2.4V~5.2V · Built-in 32´4 bit display RAM
· Built-in 256kHz RC oscillator · 3-wire serial interface
· External 32.768kHz crystal or 256kHz frequency · Internal LCD driving frequency source
source input · Software configuration feature
· Selection of 1/2 or 1/3 bias, and selection of 1/2 or · Data mode and command mode instructions
1/3 or 1/4 duty LCD applications · R/W address auto increment
· Internal time base frequency sources
· Three data accessing modes
· Two selectable buzzer frequencies (2kHz/4kHz)
· VLCD pin for adjusting LCD operating voltage
· Power down command reduces power consumption
· HT1621: 48-pin SSOP package
· Built-in time base generator and WDT
HT1621B: 48-pin DIP/SSOP/LQFP package
· Time base or WDT overflow output HT1621D: 28-pin SKDIP package
· 8 kinds of time base/WDT clock sources HT1621G: Gold bumped chip
· 32´4 LCD driver
General Description
The HT1621 is a 128 pattern (32´4), memory mapping, systems. Only three or four lines are required for the in-
and multi-function LCD driver. The S/W configuration terface between the host controller and the HT1621.
feature of the HT1621 makes it suitable for multiple LCD The HT1621 contains a power down command to re-
applications including LCD modules and display sub- duce power consumption.
Selection Table
HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626
COM 4 4 8 8 8 8 16
SEG 32 32 32 32 48 64 48
Built-in Osc. ¾ Ö Ö ¾ Ö Ö Ö
Crystal Osc. Ö Ö ¾ Ö Ö Ö Ö
Block Diagram
D is p la y R A M
O S C O
O S C I
C o n tro l
C S C O M 0
a n d
R D T im in g
C O M 3
C ir c u it L C D D r iv e r /
W R B ia s C ir c u it S E G 0
D A T A
V D D S E G 3 1
V S S V L C D
B Z T o n e F re q u e n c y W a tc h d o g T im e r
G e n e ra to r a n d IR Q
B Z T im e B a s e G e n e r a to r
Pin Assignment
S E G 7 1 4 8 S E G 8 S E G 7 1 4 8 S E G 8
S E G 6 2 4 7 S E G 9 S E G 6 2 4 7 S E G 9
S E G 5 3 4 6 S E G 1 0 S E G 5 3 4 6 S E G 1 0
S E G 4 4 4 5 S E G 1 1 S E G 4 4 4 5 S E G 1 1
S E G 3 5 4 4 S E G 1 2 S E G 3 5 4 4 S E G 1 2
S E G 2 6 4 3 S E G 1 3 S E G 2 6 4 3 S E G 1 3
S E G 1 7 4 2 S E G 1 4 S E G 1 7 4 2 S E G 1 4
S E G 0 8 4 1 S E G 1 5 S E G 0 8 4 1 S E G 1 5
C S 9 4 0 S E G 1 6 C S 9 4 0 S E G 1 6
R D 1 0 3 9 S E G 1 7 R D 1 0 3 9 S E G 1 7
W R 1 1 3 8 S E G 1 8 W R 1 1 3 8 S E G 1 8 S E G 5 1 2 8 S E G 7
D A T A 1 2 3 7 S E G 1 9 D A T A 1 2 3 7 S E G 1 9 S E G 3 2 2 7 S E G 9
V S S 1 3 3 6 S E G 2 0 V S S 1 3 3 6 S E G 2 0 S E G 1 3 2 6 S E G 1 1
O S C O 1 4 3 5 S E G 2 1 O S C O 1 4 3 5 S E G 2 1 C S 4 2 5 S E G 1 3
N C 1 5 3 4 S E G 2 2 O S C I 1 5 3 4 S E G 2 2 R D 5 2 4 S E G 1 5
O S C I 1 6 3 3 S E G 2 3 V L C D 1 6 3 3 S E G 2 3 W R 6 2 3 S E G 1 7
V D D /V L C D 1 7 3 2 S E G 2 4 V D D 1 7 3 2 S E G 2 4 D A T A 7 2 2 S E G 1 9
IR Q 1 8 3 1 S E G 2 5 IR Q 1 8 3 1 S E G 2 5 V S S 8 2 1 S E G 2 1
B Z 1 9 3 0 S E G 2 6 B Z 1 9 3 0 S E G 2 6 V L C D 9 2 0 S E G 2 3
B Z 2 0 2 9 S E G 2 7 B Z 2 0 2 9 S E G 2 7 V D D 1 0 1 9 S E G 2 5
C O M 0 2 1 2 8 S E G 2 8 C O M 0 2 1 2 8 S E G 2 8 IR Q 1 1 1 8 S E G 2 7
C O M 1 2 2 2 7 S E G 2 9 C O M 1 2 2 2 7 S E G 2 9 B Z 1 2 1 7 S E G 2 9
C O M 2 2 3 2 6 S E G 3 0 C O M 2 2 3 2 6 S E G 3 0 C O M 0 1 3 1 6 S E G 3 1
C O M 3 2 4 2 5 S E G 3 1 C O M 3 2 4 2 5 S E G 3 1 C O M 1 1 4 1 5 C O M 2
H T 1 6 2 1 H T 1 6 2 1 B H T 1 6 2 1 D
4 8 S S O P -A 4 8 S S O P -A /D IP -A 2 8 S K D IP -A
S E G 1
S E G 1
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
0
1
2
3
4
5
6
7
8
9
0
1
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
C S 1 3 6 S E G 1 2
R D 2 3 5 S E G 1 3
W R 3 3 4 S E G 1 4
D A T A 4 3 3 S E G 1 5
V S S 5 3 2 S E G 1 6
O S C O 6 H T 1 6 2 1 B 3 1 S E G 1 7
O S C I 7 4 8 L Q F P -A 3 0 S E G 1 8
V L C D 8 2 9 S G E 1 9
V D D 9 2 8 S E G 2 0
IR Q 1 0 2 7 S E G 2 1
B Z 1 1 2 6 S E G 2 2
B Z 1 2 2 5 S E G 2 3
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
C O
C O
C O
C O
S E
S E
S E
S E
S E
S E
S E
S E
G 3
G 3
G 2
G 2
G 2
G 2
G 2
G 2
M 0
M 1
M 2
M 3
1
0
9
7
8
6
5
4
Pad Assignment
S E G 1 0
S E G 1 1
S E G 1 2
S E G 1 3
S E G 1 4
S E G 1 5
S E G 8
S E G 9
S E G 0
S E G 1
S E G 2
S E G 3
S E G 4
S E G 5
S E G 6
S E G 7
C S
1 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3
R D 2 3 2 S E G 1 6
W R 3 3 1 S E G 1 7
3 0 S E G 1 8
D A T A 4
(0 ,0 )
2 9 S E G 1 9
V S S 5 2 8 S E G 2 0
O S C O 6 2 7 S E G 2 1
2 6 S E G 2 2
2 5 S E G 2 3
2 4 S E G 2 4
O S C I 7
2 3 S E G 2 5
V L C D 8
2 2 S E G 2 6
V D D 9
2 1 S E G 2 7
1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 S E G 2 8
C O M 0
C O M 1
C O M 2
C O M 3
S E G 3 1
S E G 3 0
S E G 2 9
B Z
B Z
IR Q
Pad Description
Pad No. Pad Name I/O Function
Chip selection input with pull-high resistor
When the CS is logic high, the data and command read from or written to
1 CS I the HT1621 are disabled. The serial interface circuit is also reset. But if CS
is at logic low level and is input to the CS pad, the data and command trans-
mission between the host controller and the HT1621 are all enabled.
READ clock input with pull-high resistor
Data in the RAM of the HT1621 are clocked out on the falling edge of the RD
2 RD I
signal. The clocked out data will appear on the DATA line. The host control-
ler can use the next rising edge to latch the clocked out data.
WRITE clock input with pull-high resistor
3 WR I Data on the DATA line are latched into the HT1621 on the rising edge of the
WR signal.
4 DATA I/O Serial data input/output with pull-high resistor
5 VSS ¾ Negative power supply, ground
7 OSCI I The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to
generate a system clock. If the system clock comes from an external clock
source, the external clock source should be connected to the OSCI pad. But
6 OSCO O if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads
can be left open.
8 VLCD I LCD power input
9 VDD ¾ Positive power supply
10 IRQ O Time base or WDT overflow flag, NMOS open drain output
11, 12 BZ, BZ O 2kHz or 4kHz tone frequency output pair
13~16 COM0~COM3 O LCD common outputs
48~17 SEG0~SEG31 O LCD segment outputs
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage ¾ ¾ 2.4 ¾ 5.2 V
3V 2.4 ¾ 3.0 V
VIH Input High Voltage DATA, WR, CS, RD
5V 4.0 ¾ 5.0 V
3V VOL=0.3V 80 150 ¾ mA
IOL2 LCD Common Sink Current
5V VOL=0.5V 150 250 ¾ mA
3V VOH=2.7V -80 -120 ¾ mA
IOH2 LCD Common Source Current
5V VOH=4.5V -120 -200 ¾ mA
3V VOL=0.3V 60 120 ¾ mA
IOL3 LCD Segment Sink Current
5V VOL=0.5V 120 200 ¾ mA
3V VOH=2.7V -40 -70 ¾ mA
IOH3 LCD Segment Source Current
5V VOH=4.5V -70 -100 ¾ mA
3V 40 80 150 kW
RPH Pull-high Resistor DATA, WR, CS, RD
5V 30 60 100 kW
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
fSYS1 System Clock ¾ On-chip RC oscillator ¾ 256 ¾ kHz
fSYS2 System Clock ¾ Crystal oscillator ¾ 32.768 ¾ kHz
fSYS3 System Clock ¾ External clock source ¾ 256 ¾ kHz
3V ¾ ¾ 150 kHz
fCLK1 Serial Data Clock (WR pin) Duty cycle 50%
5V ¾ ¾ 300 kHz
3V ¾ ¾ 75 kHz
fCLK2 Serial Data Clock (RD pin) Duty cycle 50%
5V ¾ ¾ 150 kHz
fTONE Tone Frequency ¾ On-chip RC oscillator ¾ 2.0 or 4.0 ¾ kHz
Serial Interface Reset Pulse
tCS ¾ CS ¾ 250 ¾ ns
Width (Figure 3)
Write mode 3.34 ¾ ¾
3V ms
WR, RD Input Pulse Width Read mode 6.67 ¾ ¾
tCLK
(Figure 1) Write mode 1.67 ¾ ¾
5V ms
Read mode 3.34 ¾ ¾
Rise/Fall Time Serial Data
t r, t f ¾ ¾ ¾ 120 ¾ ns
Clock Width (Figure 1)
Setup Time for DATA to WR,
tsu ¾ ¾ ¾ 120 ¾ ns
RD Clock Width (Figure 2)
Hold Time for DATA to WR, RD
th ¾ ¾ ¾ 120 ¾ ns
Clock Width (Figure 2)
Setup Time for CS to WR, RD
tsu1 ¾ ¾ ¾ 100 ¾ ns
Clock Width (Figure 3)
Hold Time for CS to WR, RD
th1 ¾ ¾ ¾ 100 ¾ ns
Clock Width (Figure 3)
tf tr V a lid D a ta
V D D
V D D
W R , R D 9 0 % D B 5 0 %
C lo c k 5 0 % G N D
1 0 % G N D
tC L K tC L K tS U th
V D D
W R , R D 5 0 %
Figure 1 C lo c k G N D
tC S
Figure 2
V D D
C S 5 0 %
G N D
tS U 1
th 1
V D D
W R , R D 5 0 %
C lo c k G N D
F ir s t C lo c k L a s t C lo c k
Figure 3
Functional Description
Display Memory - RAM command reduces power consumption, serving as a
system power down command. But if the external clock
The static display memory (RAM) is organized into 32´4
source is chosen as the system clock, using the SYS
bits and stores the displayed data. The contents of the
DIS command can neither turn the oscillator off nor
RAM are directly mapped to the contents of the LCD
carry out the power down mode. The crystal oscillator
driver. Data in the RAM can be accessed by the READ,
option can be applied to connect an external frequency
WRITE, and READ-MODIFY-WRITE commands. The
source of 32kHz to the OSCI pin. In this case, the sys-
following is a mapping from the RAM to the LCD pattern:
tem fails to enter the power down mode, similar to the
C O M 3 C O M 2 C O M 1 C O M 0 case in the external 256kHz clock source operation. At
S E G 0 0 the initial system power on, the HT1621 is at the SYS
DIS state.
S E G 1 1
Time Base and Watchdog Timer (WDT)
S E G 2 2
The time base generator is comprised by an 8-stage
A d d r e s s 6 b its count-up ripple counter and is designed to generate an
S E G 3 3
(A 5 , A 4 , ..., A 0 )
accurate time base. The watch dog timer (WDT), on the
other hand, is composed of an 8-stage time base gener-
ator along with a 2-stage count-up counter, and is de-
S E G 3 1 3 1 signed to break the host controller or other subsystems
A d d r from abnormal states such as unknown or unwanted
D 3 D 2 D 1 D 0
D a ta jump, execution errors, etc. The WDT time-out will result
D a ta 4 b its in the setting of an internal WDT time-out flag. The out-
(D 3 , D 2 , D 1 , D 0 )
puts of the time base generator and of the WDT time-out
RAM Mapping flag can be connected to the IRQ output by a command
option. There are totally eight frequency sources avail-
able for the time base generator and the WDT clock.
System Oscillator The frequency is calculated by the following equation.
The HT1621 system clock is used to generate the time 32kHz
base/Watchdog Timer (WDT) clock frequency, LCD fWDT =
2n
driving clock, and tone frequency. The source of the where the value of n ranges from 0 to 7 by command op-
clock may be from an on-chip RC oscillator (256kHz), a tions. The 32kHz in the above equation indicates that
crystal oscillator (32.768kHz), or an external 256kHz the source of the system frequency is derived from a
clock by the S/W setting. The configuration of the sys- crystal oscillator of 32.768kHz, an on-chip oscillator
tem oscillator is as shown. After the SYS DIS command (256kHz), or an external frequency of 256kHz.
is executed, the system clock will stop and the LCD bias
If an on-chip oscillator (256kHz) or an external 256kHz
generator will turn off. That command is, however, avail-
frequency is chosen as the source of the system fre-
able only for the on-chip RC oscillator or for the crystal
quency, the frequency source is by default prescaled to
oscillator. Once the system clock stops, the LCD display
32kHz by a 3-stage prescaler. Employing both the time
will become blank, and the time base/WDT lose its func-
base generator and the WDT related commands, one
tion as well.
should be careful since the time base generator and
The LCD OFF command is used to turn the LCD bias WDT share the same 8-stage counter. For example, in-
generator off. After the LCD bias generator switches off voking the WDT DIS command disables the time base
by issuing the LCD OFF command, using the SYS DIS generator whereas executing the WDT EN command
O S C I C r y s ta l O s c illa to r
O S C O 3 2 7 6 8 H z
E x te r n a l C lo c k S o u r c e
2 5 6 k H z S y s te m
C lo c k
1 /8
O n - c h ip R C O s c illa to r
2 5 6 k H z
T im e r /W D T
C lo c k S o u r c e s T IM E R E N /D IS
S y s te m C lo c k /2 n /2 5 6 IR Q
f= 3 2 k H z W D T E N /D IS
n = 0 ~ 7 V D D
D Q
W D T
/4 C K IR Q E N /D IS
R
C L R W D T
Timer and WDT Configurations
not only enables the time base generator but activates power fails or the external clock source is removed. Af-
the WDT time-out flag output (connect the WDT ter the system power on, the IRQ will be disabled.
time-out flag to the IRQ pin). After the TIMER EN com-
mand is transferred, the WDT is disconnected from the Tone Output
IRQ pin, and the output of the time base generator is con- A simple tone generator is implemented in the HT1621.
nected to the IRQ pin. The WDT can be cleared by execut- The tone generator can output a pair of differential driv-
ing the CLR WDT command, and the contents of the time ing signals on the BZ and BZ, which are used to gener-
base generator is cleared by executing the CLR WDT or ate a single tone. By executing the TONE4K and
the CLR TIMER command. The CLR WDT or the CLR TONE2K commands there are two tone frequency out-
TIMER command should be executed prior to the WDT puts selectable. The TONE4K and TONE2K commands
EN or the TIMER EN command respectively. Before ex- set the tone frequency to 4kHz and 2kHz, respectively.
ecuting the IRQ EN command the CLR WDT or CLR The tone output can be turned on or off by invoking the
TIMER command should be executed first. The CLR TONE ON or the TONE OFF command. The tone out-
TIMER command has to be executed before switching puts, namely BZ and BZ, are a pair of differential driving
from the WDT mode to the time base mode. Once the outputs used to drive a piezo buzzer. Once the system is
WDT time-out occurs, the IRQ pin will stay at a logic low disabled or the tone output is inhibited, the BZ and the
level until the CLR WDT or the IRQ DIS command is is- BZ outputs will remain at low level.
sued. After the IRQ output is disabled the IRQ pin will re-
main at the floating state. The IRQ output can be LCD Driver
enabled or disabled by executing the IRQ EN or the IRQ The HT1621 is a 128 (32´4) pattern LCD driver. It can be
DIS command, respectively. The IRQ EN makes the configured as 1/2 or 1/3 bias and 2 or 3 or 4 commons of
output of the time base generator or of the WDT time-out LCD driver by the S/W configuration. This feature
flag appear on the IRQ pin. The configuration of the time makes the HT1621 suitable for multiply LCD applica-
base generator along with the WDT are as shown. In the tions. The LCD driving clock is derived from the system
case of on-chip RC oscillator or crystal oscillator, the clock. The value of the driving clock is always 256Hz even
power down mode can reduce power consumption when it is at a 32.768kHz crystal oscillator frequency, an
since the oscillator can be turned on or off by the corre- on-chip RC oscillator frequency, or an external fre-
sponding system commands. At the power down mode quency. The LCD corresponding commands are sum-
the time base/WDT loses all its functions. marized in the table.
On the other hand, if an external clock is selected as the The bold form of 1 0 0, namely 1 0 0, indicates the com-
source of system frequency the SYS DIS command mand mode ID. If successive commands have been is-
turns out invalid and the power down mode fails to be sued, the command mode ID except for the first
carried out. That is, after the external clock source is se- command, will be omitted. The LCD OFF command
lected, the HT1621 will continue working until system turns the LCD display off by disabling the LCD bias gen-
erator. The LCD ON command, on the other hand, turns dress data mode, the CS pin should be set to ²1² and the
the LCD display on by enabling the LCD bias generator. previous operation mode will be reset also. Once the CS
The BIAS and COM are the LCD panel related com- pin returns to ²0² a new operation mode ID should be is-
mands. Using the LCD related commands, the HT1621 sued first.
can be compatible with most types of LCD panels.
Interfacing
Command Format
Only four lines are required to interface with the
The HT1621 can be configured by the S/W setting. There HT1621. The CS line is used to initialize the serial inter-
are two mode commands to configure the HT1621 re- face circuit and to terminate the communication between
sources and to transfer the LCD display data. The configu- the host controller and the HT1621. If the CS pin is set to 1,
ration mode of the HT1621 is called command mode, and the data and command issued between the host controller
its command mode ID is 1 0 0. The command mode con- and the HT1621 are first disabled and then initialized. Be-
sists of a system configuration command, a system fore issuing a mode command or mode switching, a high
frequency selection command, a LCD configuration com- level pulse is required to initialize the serial interface of the
mand, a tone frequency selection command, a timer/WDT HT1621. The DATA line is the serial data input/output line.
setting command, and an operating command. The data Data to be read or written or commands to be written have
mode, on the other hand, includes READ, WRITE, and to be passed through the DATA line. The RD line is the
READ-MODIFY-WRITE operations. The following are the READ clock input. Data in the RAM are clocked out on the
data mode IDs and the command mode ID: falling edge of the RD signal, and the clocked out data will
Operation Mode ID then appear on the DATA line. It is recommended that the
host controller read in correct data during the interval be-
Read Data 110 tween the rising edge and the next falling edge of the RD
Write Data 101 signal. The WR line is the WRITE clock input. The data,
address, and command on the DATA line are all clocked
Read-Modify-Write Data 101
into the HT1621 on the rising edge of the WR signal. There
Command Command 100 is an optional IRQ line to be used as an interface between
The mode command should be issued before the data the host controller and the HT1621. The IRQ pin can be
or command is transferred. If successive commands selected as a timer output or a WDT overflow flag output
have been issued, the command mode ID, namely 1 0 0, by the S/W setting. The host controller can perform the
can be omitted. While the system is operating in the time base or the WDT function by being connected with
non-successive command or the non-successive ad- the IRQ pin of the HT1621.
Timing Diagrams
READ Mode (Command Code : 1 1 0)
C S
W R
R D
1 1 0 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 1 1 0 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
D A T A
M e m o ry A d d re s s 1 (M A 1 ) D a ta (M A 1 ) M e m o ry A d d re s s 2 (M A 2 ) D a ta (M A 2 )
C S
W R
R D
1 1 0 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0
D A T A
M e m o ry A d d re s s (M A ) D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 )
C S
W R
1 0 1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 1 0 1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
D A T A
M e m o ry A d d re s s 1 (M A 1 ) D a ta (M A 1 ) M e m o ry A d d re s s 2 (M A 2 ) D a ta (M A 2 )
C S
W R
1 0 1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0
D A T A
M e m o ry A d d re s s (M A ) D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 )
C S
W R
R D
1 0 1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 1 0 1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
D A T A
M e m o ry A d d re s s 1 (M A 1 ) D a ta (M A 1 ) D a ta (M A 1 ) M e m o ry A d d re s s 2 (M A 2 ) D a ta (M A 2 )
C S
W R
R D
1 0 1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0
D A T A
M e m o ry A d d re s s (M A ) D a ta (M A ) D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 1 ) D a ta (M A + 2 )
C S
W R
1 0 0 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0
D A T A
C o m m a n d 1 C o m m a n d ... C o m m a n d i C o m m a n d
o r
D a ta M o d e
C S
W R
D A T A
C o m m a n d C o m m a n d C o m m a n d
o r A d d re s s & D a ta o r A d d re s s a n d D a ta o r A d d re s s a n d D a ta
D a ta M o d e D a ta M o d e D a ta M o d e
R D
Note: It is recommended that the host controller should read in the data from the DATA line between the rising edge
of the RD line and the falling edge of the next RD line.
Application Circuits
Host Controller with an HT1621 Display System
C S
* R D
V D D
*
V R
W R
V L C D
D A T A
M C U H T 1 6 2 1 B
* B Z
R
IR Q P ie z o
B Z
O S C I
C lo c k O u t
O S C O C O M 0 ~ C O M 3 S E G 0 ~ S E G 3 1
E x te r n a l C o lc k 1
E x te r n a l C o lc k 2 1 /2 o r 1 /3 B ia s ; 1 /2 , 1 /3 o r 1 /4 D u ty
O n - c h ip O S C
L C D P a n e l
C ry s ta l
3 2 7 6 8 H z
Note: The connection of IRQ and RD pin can be selected depending on the requirement of the MCU.
The voltage applied to VLCD pin must be lower than VDD.
Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW±20%.
Adjust R (external pull-high resistance) to fit user’s time base clock.
Command Summary
Name ID Command Code D/C Function Def.
READ 110 A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM
WRITE 101 A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM
READ-MODIFY-
101 A5A4A3A2A1A0D0D1D2D3 D READ and WRITE to the RAM
WRITE
Turn off both system oscillator and LCD
SYS DIS 100 0000-0000-X C Yes
bias generator
SYS EN 100 0000-0001-X C Turn on system oscillator
LCD OFF 100 0000-0010-X C Turn off LCD bias generator Yes
LCD ON 100 0000-0011-X C Turn on LCD bias generator
TIMER DIS 100 0000-0100-X C Disable time base output
WDT DIS 100 0000-0101-X C Disable WDT time-out flag output
TIMER EN 100 0000-0110-X C Enable time base output
WDT EN 100 0000-0111-X C Enable WDT time-out flag output
TONE OFF 100 0000-1000-X C Turn off tone outputs Yes
TONE ON 100 0000-1001-X C Turn on tone outputs
CLR TIMER 100 0000-11XX-X C Clear the contents of time base generator
CLR WDT 100 0000-111X-X C Clear the contents of WDT stage
XTAL 32K 100 0001-01XX-X C System clock source, crystal oscillator
Package Information
48-pin SSOP (300mil) Outline Dimensions
4 8 2 5
A B
1 2 4
C '
G
D H
a
E F
Dimensions in mil
Symbol
Min. Nom. Max.
A 395 ¾ 420
B 291 ¾ 299
C 8 ¾ 12
C¢ 613 ¾ 637
D 85 ¾ 99
E ¾ 25 ¾
F 4 ¾ 10
G 25 ¾ 35
H 4 ¾ 12
a 0° ¾ 8°
4 8 2 5
1 2 4
C
D
a I
E F G
Dimensions in mil
Symbol
Min. Nom. Max.
A 2435 ¾ 2445
B 535 ¾ 555
C 145 ¾ 155
D 125 ¾ 145
E 16 ¾ 20
F 50 ¾ 70
G ¾ 100 ¾
H 595 ¾ 615
I 635 ¾ 670
a 0° ¾ 15°
D H
G
3 6 2 5
I
3 7 2 4
F
A B
4 8 1 3
K a
J
1 1 2
Dimensions in mm
Symbol
Min. Nom. Max.
A 8.90 ¾ 9.10
B 6.90 ¾ 7.10
C 8.90 ¾ 9.10
D 6.90 ¾ 7.10
E ¾ 0.50 ¾
F ¾ 0.20 ¾
G 1.35 ¾ 1.45
H ¾ ¾ 1.60
I ¾ 0.10 ¾
J 0.45 ¾ 0.75
K 0.10 ¾ 0.20
a 0° ¾ 7°
2 8 1 5
B
1 1 4
D
a I
E F G
Dimensions in mil
Symbol
Min. Nom. Max.
A 1375 ¾ 1395
B 278 ¾ 298
C 125 ¾ 135
D 125 ¾ 145
E 16 ¾ 20
F 50 ¾ 70
G ¾ 100 ¾
H 295 ¾ 315
I 330 ¾ 375
a 0° ¾ 15°
D
T 2
A B C
T 1
SSOP 48W
Symbol Description Dimensions in mm
A Reel Outer Diameter 330±1.0
B Reel Inner Diameter 100±0.1
13.0+0.5
C Spindle Hole Diameter
-0.2
D Key Slit Width 2.0±0.5
32.2+0.3
T1 Space Between Flange
-0.2
T2 Reel Thickness 38.2±0.2
P 0 P 1 t
D
F
W C B 0
K 1
D 1 P
K 2
A 0
SSOP 48W
Symbol Description Dimensions in mm
W Carrier Tape Width 32.0±0.3
P Cavity Pitch 16.0±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 14.2±0.1
D Perforation Diameter 2.0 Min.
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length 12.0±0.1
B0 Cavity Width 16.20±0.1
K1 Cavity Depth 2.4±0.1
K2 Cavity Depth 3.2±0.1
t Carrier Tape Thickness 0.35±0.05
C Cover Tape Width 25.5