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# EE-231 Electronics I

## Engr. Dr. Hadeed Ahmed Sher

Ghulam Ishaq Khan Institute of Engineering Sciences and Technology, TOPI 23460

## March 29, 2018

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 1 / 24
1 Designing of Biasing Techniques
Design of Emitter follower Bias configuration
Design of voltage divider bias configuration

## 2 Multistage BJT networks

Example 4.26
Cascode configuration

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 2 / 24
Designing of Biasing Techniques

## The design process is reverse process of analysis.

Voltage and current is usually specified and resistance value is required.
Often assumptions are required to start a design process.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 3 / 24
Designing of Biasing Techniques Design of Emitter follower Bias configuration

## The design process follows two ways.

One is tracing backwards from the analysis process as presented in
example 4.23. The biasing voltages are selected using datasheets
Other is in addition to this i.e using engineering judgements in addition to
the values provided in the datasheet.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 4 / 24
Designing of Biasing Techniques Design of Emitter follower Bias configuration

Example 4.23

## Given that ICQ = 12 Isat and

CRC VCC − VC
ICsat =8mA,Vc =18V and β=110. RC = = = 2.5kΩ
Determine RC , RE and RB for the ICQ ICQ
(2)
circuit shown. VCC
ICsat = (3)
RC + RE
VCC
RC + RE = = 3.5kΩ (4)
ICsat
Using the value of RC , RE =1kΩ.
ICQ
IBQ = = 36.36µA (5)
β
1 VCC − VBE
ICQ = ICsat = 4mA (1) IBQ = (6)
2 RB + (β + 1)RE

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 5 / 24
Designing of Biasing Techniques Design of Emitter follower Bias configuration

Example 4.23

VCC − VBE
RB = − (β + 1)RE = 639.8kΩ (7)
IBQ
Because in market there are only standard values of resistances available
therefore, using the standard values
RC =2.4kΩ
RE =1kΩ
RB =620kΩ

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 6 / 24
Designing of Biasing Techniques Design of Emitter follower Bias configuration

## Design procedure of emitter bias circuit

Rule 1
RE cannot be very large otherwise it will limit the swing of the voltage
from collector to emitter.

Rule 2
1 1
4 VCC ≤ VE ≤ 10 VCC

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 7 / 24
Designing of Biasing Techniques Design of Emitter follower Bias configuration

Example 4.24
Determine RC , RE and RB for
the circuit shown.
VE VE
RE = ≈ = 1kΩ (9)
IE IC
VRC VCC − VCE − VE
RC = = = 4kΩ
IC IC
(10)
IC
IB = = 13.33µA (11)
β
VRB VCC − VBE − VE
Choosing the conservative value RB = = ≈ 1.3MΩ
IB IB
of VE given in rule 2. (12)
1
VE = VCC = 2V (8)
10

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 8 / 24
Designing of Biasing Techniques Design of voltage divider bias configuration

## There are four unknown resistances in this circuit.

The rules outlined on slide 7 leads to direct solution for the values of these
resistances.
Moreover it is assumed that current through R1 and R2 should be
approximately equal and greater to base current by a ratio of 10:1.
Rule 3
1
R2 ≤ 10 βRE

Rule 4
R2 VCC
VB = R1 +R2

## Example 4.25 is used to demonstrate the calculation procedure.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 9 / 24
Designing of Biasing Techniques Design of voltage divider bias configuration

Example 4.25
Choosing the lower value for VE
1
Determine the unknown VE = VCC = 2V (13)
10
resistances of the network shown.
VE VE
RE = ≈ = 200Ω (14)
IE IC
VRC VCC − VCE − VE
RC = = = 1kΩ
IC IC
(15)
VB = VBE + VE = 0.7 + 2 = 2.7V (16)
To find R1 and R2 rule 3 and rule 4 are
considered.
1
R2 ≤ (80)(200) = 1.6kΩ (17)
10
Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 10 / 24
Designing of Biasing Techniques Design of voltage divider bias configuration

Example 4.25

(1.6kΩ)(20V )
VB = 2.7V = (18)
R1 + 1.6kΩ
Solving for R1 =10.25kΩ

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 11 / 24
Multistage BJT networks

## BJT can be connected to other BJT to form a multistage network. Two

such arrangements are
Cascode arrangement
In cascade arrangement the output of one BJT is fed to the input of the
second BJT.
In cascode arrangement the BJT are connected such that the emitter of
one BJT is connected to the collector of other.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 12 / 24

## Technique 1 : R-C coupling

This is the most commonly used method of coupling. Capacitor is used to
block the DC signal. The circuit shown is for voltage divider biasing but
the same can be done using any other biasing method.

## Considering capacitors as open circuit the two circuits can be analyzed.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 13 / 24

## Technique 2 : Direct coupling — Darlington configuration

In this method the output of one BJT is connected directly to the other
BJT. It is mostly used to enhace the beta rating.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 14 / 24

## Technique 2 : Direct coupling — Darlington configuration

Consider fig below, The base and collector current for second
BJT are given below.

## IE 2 = (β2 +1)IB2 = (β2 +1)(β1 +1)IB1 (20)

Because β>>1 therefore,

βD = β1 β2 (21)

## Assume β1 for first transistor VCC − VBE 1 − VBE 2

IB1 = (22)
and β2 for second transistor. RB + (βD + 1)RE

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 15 / 24

## Considering this pair as a single

device The emitter voltage is

## Therefore, Because there is no resistor in

collector therefore,
VCC − VBED
IB1 = (24)
RB + (βD + 1)RE VC 2 = VCC (27)

## The collector currents are given as VCE 2 = VC 2 − VE 2 = VCC − VE 2

(28)
IC 2 ≈ IE 2 = βD IB1 (25)

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 16 / 24

## Technique 3 : Feedback Pair

In this coupling method both NPN and PNP transistors are used. This
circuit provides high gain with increased stability.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 17 / 24

## Technique 3 : Feedback Pair

Consider fig below,

Therefore,

## IC2 ≈ IE2 = β1 β2 IB1 (31)

Collector current is

## IB2 = IC1 = β1 IB1 (29)

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 18 / 24

Applying KVL

## VCC −IC RC −VEB1 −IB1 RB = 0 (34)

The collector voltage VC2 =VE1 is
Using the value of IC given in (33)
and rearranging VC2 = VCC − IC RC (38)

## VCC − VEB1 and VC1 =VBE2 . In this circuit

IB1 = (35)
RB + β1 β2 RC VCE2 =VC2 and VEC1 = VE1 − VC1 .
Therefore,
The base voltage VB1 and VB2 is
VEC1 = VC2 − VBE2 (39)
VB1 = IB1 RB (36)

## VB2 = VBE2 (37)

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 19 / 24

Example 4.26
Determine the dc levels for the currents and voltages of the direct- coupled
amplifier shown. Note that it is a voltage-divider bias configuration
followed by a CE configuration; one that is excellent in cases wherein the
input impedance of the next stage is quite low. The CCA is acting like a
buffer between stages.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 20 / 24

Example 4.26
Consider fig below,
In this example RTh =7.67kΩ and
ETh =3.26V.

In this circuit

## VE2 = VB2 − VBE2 = 5.68V (43)

VE2
IE2 = = 4.73mA (44)
RE2
ETh − VBE VC2 = VCC =14V and
IB1 =
RTh + (β + 1)RE VCE2 = VC2 − VE2 =8.32V
(40)
Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 21 / 24
Multistage BJT networks Cascode configuration

Cascode configuration
Collector of one transistor is connected to the emitter of other transistor.
It is actually a voltage divider network with common base configuration.It
offers reduced miller capacitance and high gain.

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 22 / 24
Multistage BJT networks Cascode configuration

Cascode configuration

## Consider fig. below It is assumed that current through R1 ,R2

and R3 is much larger than base current of
each transistor.

## IR1 ≈ IR2 ≈ IR3 >>IB1 IB2 (45)

Using VDR
R3 VCC
VB1 = (46)
R1 + R2 + R3
Similarly,

(R2 + R3 )VCC
VB2 = (47)
R1 + R2 + R3

Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 23 / 24
Multistage BJT networks Cascode configuration

Cascode configuration
Collector voltage VC2 is
Emitter voltage is determined by
VC2 = VCC − IC2 RC (52)
VE 1 = VB1 − VBE 1 (48)
The current through the biasing
VE 2 = VB2 − VBE 2 (49) resistors is
The collector currents are determined VCC
by IR1 ≈ IR2 ≈ IR3 =
R1 + R2 + R3
(53)
VB1 − VBE1
IC2 ≈ IE2 ≈ IC1 ≈ IE1 = Base currents for each BJT are
RE1 + RE2
(50) IC1
IB1 = (54)
Collector voltage VC1 is β1

## VC1 = VB2 − VBE2 (51) IC2

IB2 = (55)
β2
Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 10 Resources March 29, 2018 24 / 24