Lesson 1

Introduction to LabVIEW FPGA

TOPICS
A. Introduction to FPGA Technology
B. LabVIEW FPGA System Components
C. LabVIEW FPGA Applications

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A. Introduction to FPGA Technology

What it is
• A silicon chip with unconnected gates
• Enables user to define and re-define functionality
How it works
• Defines behavior in software
• Compiles and download to the hardware
When it is used
• Custom hardware or ICs, replacement for ASICs
• Reconfiguration required after deployment

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A. Introduction to FPGA Technology
Let’s begin by discussing the technology behind LabVIEW FPGA.
Field programmable gate arrays (FPGAs) are silicon chips with unconnected logic
gates. You can define the functionality of the FPGA by using software to configure the
FPGA gates. FPGAs are often used as processing components in low to medium
volume electronics, where the time and cost of developing and fabricating an
applications specific integrated circuit (ASIC) is prohibitive. FPGAs are also found in
applications that require reconfiguration in the field.
Typically, FPGAs are programmed using software development tools such as VHDL
and
Verilog. These tools require a steep learning curve, however, and can become a barrier
for
using this technology. The LabVIEW FPGA Module allows LabVIEW to target FPGAs
on
NI Reconfigurable I/O hardware so scientists and engineers can take advantage of the
performance and flexibility of FPGAs without needing to learn the low-level design
tools.

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B. LabVIEW FPGA System Components
LabVIEW FPGA Module
• Software for developing VIs for
FPGA target
• VIs for host PC interaction with
FPGA target

LabVIEW FPGA Enabled Hardware

• Plug-In Reconfigurable I/O (RIO) boards
• CompactRIO Modular Reconfigurable I/O
System
• Compact Vision System
• IF-RIO

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B. LabVIEW FPGA System Components
There are two main parts in a LabVIEW FPGA System: the LabVIEW FPGA Module
and the RIO hardware.
As mentioned earlier, you use the LabVIEW FPGA Module to develop VIs you can
implement as hardware in the FPGA on RIO hardware. Using the LabVIEW FPGA
Module, you can develop custom control and measurement hardware without any prior
knowledge of hardware description languages or board-level hardware design. Using
LabVIEW is also an intuitive way to represent the timing, concurrency, and parallelism
of FPGA hardware. Additionally, you can easily integrate your custom FPGA hardware
with other measurement and control system components using the LabVIEW FPGA
Interface VIs.
LabVIEW FPGA targets contain the FPGA designed by LabVIEW. Since this hardware
contains an FPGA, it is field programmable, offering a new level of flexibility for
virtual instrumentation. National Instruments offers a number of targets that include the
R Series line of data acquisition products, the IF-RIO product line, the rugged and
modular CompactRIO platform, and the Compact Vision System.

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Components of a Measurement System

A traditional system consists of three components

• Application software on the computer (LabVIEW)
• Driver software to interface to the hardware (NI-DAQmx)
• The I/O hardware (M Series MIO)

LabVIEW NI-DAQmx M Series Device

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To understand the paradigm of a LabVIEW FPGA system, it is important to
understand the specific components found in a traditional measurement
system. A traditional measurement and control system consists of three basic
components:
− The application software running in Windows or a Real-Time operating system
(RTOS). For example, the LabVIEW development environment
− The driver software and functions to interface to your hardware. For example, the
NI-DAQmx driver.
− And finally, the I/O hardware. For this specific example, we are calling out an M-
series DAQ device.
When National Instruments developed the M Series, developers had to put as
much general-purpose functionality as possible into the ASIC on the DAQ
device. This required an extensive driver that made all of this functionality
accessible through software. The drawback to this approach is that all of the
device functionality is fixed. The customization of such systems comes
through the programming at the application software layer.

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LabVIEW FPGA-Based Measurement System

• Application software on the computer (LabVIEW)

• User-defined hardware functionality (LabVIEW FPGA)
• Driver software to interface to LabVIEW on the device (NI-RIO)
• Reconfigurable I/O hardware (R Series)

R Series Device

FPGA FPGA
LabVIEW NI-RIO
Interface LabVIEW FPGA VI

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When using a LabVIEW FPGA-based measurement system, this
paradigm changes. Although the application software runs on
Windows or an RTOS, the very thin NI-RIO driver provides the
interface functions to the hardware. You can use vendor-defined
off-the-shelf hardware, in this case the R Series DAQ device, and
still modify the functionality of this device using LabVIEW
FPGA. On the RIO hardware platforms, the FPGA (instead of an
ASIC) defines the device functionality, which allows scientists
and engineers to use software to define the device functionality.
With this paradigm, end users have an I/O platform with the
performance and flexibility of an FPGA without the added
complexity of having to understand FPGA and board-level
hardware design.

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LabVIEW FPGA Targets

CompactRIO PXI R Series PCI R Series Compact Vision IF-RIO

Intelligent DAQ Intelligent DAQ System

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The following NI hardware platforms have a programmable FPGA.
− The R Series is a family of general-purpose data acquisition devices.
There are multiple versions of both PXI and PCI and include analog I/O
and digital I/O.
− CompactRIO is an embedded system that is used for machine control, in-
vehicle data acquisition, and portable NVH applications. Refer to
for more information on this platform.
ni.com/compactrio

− The Compact Vision System (CVS) and 825x can acquire data from up to
three IEEE 1394 FireWire® cameras and the CVS is a complete system for
machine vision applications. This system also includes 29 digital lines
whose functionality can be configured using LabVIEW FPGA.
− The IF-RIO line is a cost-effective IF transceiver with power and
flexibility that make it ideally suited for software-defined radio and other
communications applications.

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Traditional Approach to Custom Hardware

• Hardware Design
• Prototype A Build/Test
• Prototype B Build/Test
• Software Design/Coding
• Software Testing
• System
Testing/Certification

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To better understand the benefits of this RIO platform, let’s
consider that you have an application that requires some form of
custom hardware. In this case, we will consider a pulse width
modulator (PWM) motor driver. Designing this device will
require iterating through a variety of steps such as the hardware
design, software design, building prototypes and testing the
device throughout. If no major setbacks are encountered, this
could take up to 12 weeks and cost $50,000.00 to $150,000.00.
Now consider if your requirements change and you need to make
modifications to the device. You are now forced to either build a
daughter card so that you can reuse the previously designed
device, or you must redesign the original device to accommodate
the changes. Regardless, if your device requirements change, you
will need to go through the development process again.

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NI Approach to Custom Hardware

• Hardware Design
• Prototype A Build/Test
• Prototype B Build/Test
• Software Design/Coding
• Software Testing
• System
Testing/Certification

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Using LabVIEW FPGA, you can define the motor control functionality
in LabVIEW then deploy the VI to an appropriate hardware target.
Using these tools allows you to implement custom tasks without using
low-level hardware development tools or going through the entire
hardware development process. Additionally, as functional
requirements change, simply develop or change your LabVIEW VI and
re-download the VI to the NI hardware.
Using LabVIEW FPGA, you can define the motor control functionality
in LabVIEW then deploy the VI to an appropriate hardware target.
Using these tools allows you to implement custom tasks without using
low-level hardware development tools or going through the entire
hardware development process. Additionally, as functional
requirements change, simply develop or change your LabVIEW VI and
re-download the VI to the NI hardware.

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C. LabVIEW FPGA Applications

Applications Driving Need for Custom Hardware

• Intelligent DAQ
• Ultra-high speed control
• Specialized communication protocols
• Sensor level signal processing
• Off-load CPU – Coprocessing

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C. LabVIEW FPGA Applications

Now, let’s look at some common applications that are well

suited for the LabVIEW FPGA Module.
LabVIEW FPGA is best suited for applications that require
the development of custom hardware. These tasks include:
− Implementing custom I/O hardware for getting a custom mix
of analog or digital I/O, implementing custom counters or
pulse-wave modulation outputs, or implementing custom
timing and triggering routines
− Implementing control loops that run at rates over 150 kHz
− Interfacing to specialty communication protocols
− Implementing signal processing algorithms such as filters or
sensor simulations at the I/O level.

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Benefits of FPGA Logic in LabVIEW

• Multi-loop analog PID loop rates exceed 100 kHz on

embedded RIO FPGA hardware
• Single-cycle Timed Loops execute at the rate of the selected
FPGA clock
• Due to parallel processing ability, adding computation does
not necessarily reduce the speed of the FPGA application

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With the embedded RIO FPGA hardware, you can
implement multiloop analog proportional, integral,
derivative (PID) control systems at loop rates exceeding
100 kHz. In contrast, multiloop analog PID control
systems run at 30 kHz in real-time without FPGA
hardware. It is possible to evaluate multiple rungs of
Boolean logic using single-cycle Timed Loops at rates
of 40 MHz
(25 ns) or greater. Because of the parallel nature of the
FPGA, adding additional computation does not
necessarily reduce the speed of the FPGA application.

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Benefits of FPGA Logic with LabVIEW
(continued)
F =(A+B)C
True simultaneous parallel
implementation of
F = (A + B)C and Z = X + Y + M
in separate gates on an FPGA

Z=X+Y+M

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Another benefit of running your LabVIEW code on the
FPGA is that you can achieve true, simultaneous,
parallel processing. There is no operating system on the
module that must divide CPU time between several
tasks. Figure shows simultaneous parallel
implementation of
two calculations, F = (A + B) × C and Z = X + Y + M in
separate gates on an FPGA.

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Intelligent DAQ

Possible Intelligent applications

• Built-in IP Processing Blocks
• Custom Timing and Synchronization
• Custom Clocks
• Pulse-Width Modulation
• Custom Counters
• Custom Analog Triggering
• Multiple Scan Rates
• Custom Analog I/O

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LabVIEW FPGA is the heart and soul of intelligent DAQ devices. With LabVIEW
FPGA, you can create DAQ devices that have a custom mix of analog I/O. The analog
R Series devices have up to eight 16-bit analog inputs and outputs. Because
CompactRIO is a modular system, you can mix and match a variety of analog and
digital inputs and outputs.
With LabVIEW FPGA you can synchronize acquisitions on a device or have multiple
acquisition rates within a single device.
You can also perform custom triggering operations. For this specific code, we are
setting a trigger based off a variety of analog conditions.
LabVIEW FPGA is ideal for creating custom digital I/O. For instance, you can turn any
digital line into a counter just by drawing a counter in LabVIEW.
You can also customize counters by simply changing the LabVIEW block diagram.
You can turn a bidirectional digital line into a PWM, create clocks, or perform custom
timing and synchronization routines.
You can also embed other intelligence onto your RIO devices using the built-in
intellectual property (IP) functions for control or signal processing. You can implement
digital filters from the Digital Filter Design toolkit or optimized motion algorithms
from the NI SoftMotion Development Module. You can also bring certain existing
VHDL into a LabVIEW block diagram with the HDL interface node.

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Digital Communication Protocols
ChipSelect*
• FPGA can create/read almost
any communication protocol Clock
• Many protocols already created
by other developers Data
• Refer to ni.com/ipnet to find 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1

code

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Another common application for FPGA hardware is implementing
digital protocols that are commonly used for communicating between
embedded devices, digital audio, peripheral device interfaces such as
the mouse on your computer, or to connect different subsystems within
automobiles or airplanes.
While some of these interfaces have off-the-shelf hardware that may be
purchased, many times these communication interfaces are so
customized they require custom hardware. With LabVIEW FPGA, you
can simply configure the FPGA to control a set of digital lines to
implement many communication protocols requiring precise timing and
synchronization. The block diagram in the figure above is the output
for a 16-bit SPI device.
Refer to ni.com/ipnet for example code to implement a variety of
digital protocols including SPI, I2C, SPDIFF, and RS-232 protocols.
Plus IPs for control, signal generation, math, sensor simulation and data
acquisition.

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 Demonstration: IPNet

Navigate to ni.com/ipnet.
Find a VI related to a communication protocol of choice,
GOAL

download the VI, and examine how the VI works.

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Decision Making in Software

Traditional System Crash Possible

Application Software
Operating System

Calculation
Driver API
~25 ms
UUT
I/O
Response

Outputs

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Many test and control systems perform calculations in
software. When executing in software the calculation
must be performed after multiple software calls through
the application software, driver API, and operating
system before actually interfacing with the unit under
test (UUT). Even when using an RTOS and optimized
algorithms, the fastest response rate you can typically
achieve in software is around 25 µs. Additionally, there
is added vulnerability within a software-based system
because a crash can occur at multiple levels that
interfere with the response of the system.

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Decision Making in Hardware
Highest Reliability
LabVIEW FPGA System

Application Software
Operating System
Calculation

Driver API
25 ns*
UUT
I/O
Response

Outputs

* Faster response for 80 and 120 MHz clocks

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When executing calculations in hardware, such as when
using LabVIEW FPGA, you can remove software from the
required response to the UUT. Under this configuration,
LabVIEW FPGA
can respond to digital signals within a single clock cycle.
With a default clock rate of 40 MHz, LabVIEW FPGA can
respond to a digital signal within 25 ns. You can compile
LabVIEW FPGA code at higher rates in some cases.
Performing calculations in hardware provides the highest
reliability possible because any crash at any software layer
will not affect the execution of your code.

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Analog Control Over 40 kHz

LabVIEW Real-Time LabVIEW FPGA

Single PID 40 kHz PID at over 100 kHz

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A good example of the benefits of executing algorithms in
hardware is performing PID control. When implementing
simple PID control in LabVIEW FPGA, you can achieve a
performance increase of 300–500%. Control loops executing
in FPGA hardware can execute at rates between 100 and 200
kHz. Also, because FPGAs can implement tasks in parallel,
adding multiple control loops will not affect the
performance of your loops. This means that as long as you
have space on the FPGA, an application running one control
loop will run just as fast as the same application with eight
control loops. With systems running on Windows or an
RTOS, performance decreases as you add functionality.

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Off-Loading Processing from CPU
LVDT Simulation
Hardware-in-the-loop
Sensor simulation
• Cam and crank
• LVDTs
Encoding/decoding sensors Quadrature Encoder
• Tachometers
• PWM
• Quadrature Encoders

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Finally, you can off-load processing tasks from the
main-system processor to the FPGA. This is common in
systems that require real-world sensor simulation, such
as cam/crank sensors or LVDT sensors, and when
needing to encode or decode sensors such as
tachometers, PWM, or encoders.

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Quiz

1. FPGAs completely 2. It is usually fastest to

replace the need for develop protocols by
ASICS. yourself and then to look
a. True online to see if you were
b. False right.
a. True
b. False

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Quiz

3. FPGA applications use 4. LabVIEW FPGA allows

which of the following for you to program an FPGA
an operating system (OS). without knowing VHDL or
a. Windows FPGA HDL.
b. MicroLinux a. True
c. Unix b. False
d. PharLap
e. None of the above

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1.False
2.False
3. None of the above
4. True

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