Lesson 3

FPGA Programming Basics

TOPICS
A. Introduction E. Front Panel Communication
B. Defining FPGA Logic with F. Testing with the Emulator
LabVIEW G. Compiling the FPGA VI
C. FPGA VI Development Process
D. Developing the FPGA VI

ni.com/training
In this lesson you learn how to use the LabVIEW FPGA
Module to configure an FPGA chip. The I/O channels and
modules communicate with the FPGA chip, which you can
program to run at high rates. Furthermore, you can configure
the FPGA to pass information from the I/O modules, such as
data from sensors and calibration values, to the real-time
controller. In addition, the real-time controller can
communicate feedback control signals to the FPGA and I/O
modules. After you develop the FPGA VI, you can test and
debug it using the LabVIEW emulator and Interactive Front
Panel Communication.

ni.com/training
A. Introduction

FPGA Layout and Components

ni.com/training
A. Introduction
An FPGA is a chip that can be reconfigured through software for different applications.
The LabVIEW FPGA Module targets the following NI reconfigurable I/O (RIO)
devices:
− R Series data acquisition (DAQ)
− CompactRIO
− Compact Vision
− IF-RIO
Refer to ni.com for a current list of devices. R Series DAQ devices support complex
data acquisition or real-time I/O applications. FPGA logic on an NI Compact Vision
system adds custom triggering, pulse width modulation (PWM) signals, motion control,
or custom communications protocols. CompactRIO uses FPGA for modularity, FPGA-
timed I/O with
built-in signal conditioning, and direct signal connectivity for maximum flexibility in
embedded measurement and control applications.

ni.com/training
How FPGA Works

• Programmable interconnect switches and wires route

signals in an FPGA.
• Switches are known as Register Flip-Flops.
• Flip-Flops pass data on a rising edge of the clock.
• Compiled LabVIEW code produces a Look-up Table (LUT).
• LUT defines the interconnections between configurable logic
blocks (CLBs).

ni.com/training
A single FPGA can replace thousands of discrete components by
incorporating millions of
logic gates in a single integrated circuit (IC) chip. The previous figure
shows the FPGA as a reconfigurable digital architecture with a matrix
of configurable logic blocks (CLBs) with horizontal and vertical
routing channels surrounded by a periphery of I/O blocks. FPGA logic
is created by routing signals within the FPGA matrix using
programmable interconnect switches and wire routes. The switches,
known as register flip-flops, enforce dataflow between functions by
passing data on a rising edge of the clock. VIs you create in LabVIEW
define the logical interconnections between CLBs. The VI produces a
look-up table (LUT), also known as a truth table, that defines outputs
from all possible input values to a logic function. Typical logic
functions include Boolean operations, comparisons, and basic
mathematical operations.

ni.com/training
How FPGA Works (continued)
Implements a VI that calculates a
value for F from inputs A, B, C,
and D where F = CD(A + B)

ni.com/training
An FPGA is analogous to a printed circuit board that
has a large number of unconnected devices on it.
Traditionally, the devices are connected with physical
wires soldered to the pins with a wire wrapping tool, or
embedded in the printed circuit board. The physical
wires are difficult to modify. However, the connections
in an FPGA circuit are dynamically defined in software
when the LabVIEW code compiles and the wiring list is
downloaded. The wiring list causes semiconductor
switches to turn on or off, thereby defining the
connections between gates.

ni.com/training
FPGA Family Specifications

Hardware Comparisons
• Most important specification is number of logic slices
• Slices help to represent the amount of logic that can implemented on a single FPGA
Component Type 1M Gate FPGA 3M Gate FPGA
(PCI-7831R) (PCI-7833R)
Equivalent number of logic cells 11,520 32,256
Number of logic slices 5,120 14,336

Available embedded RAM 81,920 196,608

(bytes)
Ways to conserve FPGA space are covered in more detail in
Lesson 8: FPGA Optimization

ni.com/training
The table above specifies the number of logic slices, cells, and RAM in different sized FPGAs.
A logic cell consists of a lookup table, a flip flop, and connection to adjacent cells. The lookup
table uses combinatorial logic to implement a 4-input expression (and, or, nand, addition, etc.)
A logic slice consists of 2 logic cells. Xilinx counts closer to 2.25 logic cells per slice because
they can do more per configurable logic block (CLB) than other architectures.
A configurable logic block (CLB) consists of 4 slices. This combined architecture gives benefits
in the final system such as increased performance of logic execution.
The Xilinx FPGA also includes other components such as memory blocks, each providing 2 KB of
storage, and multipliers.
The number of gates is number representing the combination of memory banks, cells, multipliers,
etc. It is important to note that the efficiency of a gate in an FPGA is not equivalent to that of a
gate in an ASIC. For example, a 1M gate FPGA is roughly equivalent to a 100K gate ASIC.
Note There is no set amount of logic slices used by any particular function. When the
application compiles, the compiler will optimize the code more heavily for large
applications than for smaller applications. Because of this code optimization
functions LabVIEW FPGA functions can not be directly correlated to the
space used in a compiled application. There are more details about compiling and
optimizing in Lesson 8: FPGA Optimization.

ni.com/training
B. Defining FPGA Logic with LabVIEW

• FPGA Module
• Do not have to learn VHDL
• True parallel execution
• Deterministic

ni.com/training
B. Defining FPGA Logic with LabVIEW
The FPGA circuitry is a parallel processing reconfigurable computing
engine that executes a LabVIEW VI in silicon circuitry on a chip. As
shown in the figure above, you can use the LabVIEW FPGA Module to
define FPGA logic using LabVIEW VIs instead of low-level languages
such as very high speed integrated circuit hardware description
language (VHDL). LabVIEW and FPGA can implement synchronous
or asynchronous parallel tasks in hardware to process and generate
synchronized analog and digital signals rapidly and deterministically.
Note You can import HDL code into LabVIEW FPGA by
using the HDL Interface Node. This is outside
of the scope of this course, but more information can be
found in the online tutorial: Importing HDL Code into FPGA VIs
Using the HDL Interface Node
(http://zone.ni.com/devzone/cda/tut/p/id/3483)

ni.com/training
 Compiling LabVIEW VIs to FPGA Hardware
• Convert the FPGA VI into • A bitstream file results
executable code • Bitstream loads at run time
− FPGA Module compiles VI • Bitstream reloads at power-up
− Graphical code translated to − On-board flash memory
VHDL
− Controller over PCI Bus
− Xilinx ISE compiler creates circuit
from VHDL
− Compiler optimizes
the implementation

ni.com/training
The LabVIEW FPGA Module compiles LabVIEW VIs to FPGA hardware using an
automatic multi-step process. Behind the scenes, the VI is translated to text-based
VHDL code. Then Xilinx ISE compiler tools optimize, reduce, and synthesize the
VHDL code into a hardware circuit realization of the LabVIEW design.
During the FPGA compilation, the VI is optimized to reduce digital logic and create an
optimal implementation of the LabVIEW application. The end result is a bitstream file
that contains the gate array configuration information. When the application runs, the
bitstream loads into the FPGA chip and reconfigures the gate array logic. On save
targets the bitstream also can load into nonvolatile flash memory and load rapidly when
power is applied to the target. There is no operating system on the FPGA chip.
When you run an FPGA VI, the block diagram is converted to intermediate files that
are sent to the compile server where they are compiled for the FPGA. The server
returns the FPGA bitstream to LabVIEW where it is stored in the VI. Because the
LabVIEW environment is a client, you can disconnect from the server and reconnect
while compiling. The compiled bitstream is unique to each category of LabVIEW
FPGA target. You can compile a VI to different LabVIEW FPGA targets and the
different bitstreams are stored separately from the FPGA VI. The bitstream downloads
automatically when you a compile the VI by clicking Run.

ni.com/training
Benefits of FPGA Logic in LabVIEW

• FPGA provides:
− Timing
− Triggering
− Processing
− Custom I/O
• Each fixed I/O uses a portion of the FPGA logic
• The PCI interface also uses a portion of the FPGA logic

ni.com/training
The FPGA logic provides timing, triggering, processing,
and custom I/O measurements. Each fixed I/O resource
used by the application uses a small portion of the
FPGA logic that controls the fixed I/O resource. The
bus interface also uses a small portion of the FPGA
logic to provide software access to the device. The
remaining FPGA logic is available for higher level
functions such as timing, triggering, and counting. The
functions use varied amounts of logic. The amount of
FPGA space your application requires depends on your
need for I/O recovery, I/O, and logic algorithms.

ni.com/training
C. FPGA VI Development Process

Keep in mind…
• No operating system on the FPGA
• Download and run one top-level VI at a time
• FPGA can run independently of the host
• FPGA can store data
• Editing a VI in the FPGA Target activates the FPGA palette
• Integer math and fixed-point math

ni.com/training
C. FPGA VI Development Process
The FPGA contains the I/O portion of your application as well as any hardware-based timing and triggering, low-level
signal processing, and so on. LabVIEW FPGA Module applications range from a single FPGA VI running on an FPGA
target to large LabVIEW solutions that include multiple FPGA targets, the LabVIEW Real-Time Module, and one or
more RT targets, and LabVIEW running on Windows. In any case, you need to create the FPGA VI that runs on the
FPGA target.
With the LabVIEW FPGA Module you can use high-level graphical dataflow programming to create a highly optimized
gate-array implementation of your analog or digital control logic. You can use normal LabVIEW programming
techniques to develop your FPGA application.
You can download and run one top-level FPGA VI at a time on a single FPGA target. If you download a second VI to the
FPGA target, the second VI overwrites the first VI.
When you add an FPGA VI under a hardware target, such as an R Series DAQ device, the LabVIEW Functions palette
adapts to contain only the VIs and functions that are designed to work on FPGA. The primary programming difference
compared to traditional LabVIEW is that FPGA devices use integer math and fixed-point math instead of floating-point
math. Also, there is no notion of multithreading or priorities because each loop executes in independent dedicated
hardware and does not have to share resources—in effect, each loop executes in parallel at time-critical priority.

Note Refer to the LabVIEW Help for more information about the FPGA VI
development process.

ni.com/training
D. Developing the FPGA VI

• FPGA is fast and reliable

• FPGA has limited space

FPGA RT and/or PC
Time critical control Extensive analysis
Acquisition File I/O
Timing in the FPGA User interface
In-line processing Supervisory control
Triggering

ni.com/training
D. Developing the FPGA VI
Because the FPGA is extremely fast and the hardware
implementation of the VI is more reliable than software,
you should put all of the time-critical control,
acquisition, and timing components of your application
in the FPGA. However, the FPGA has limited space, so
use the RT controller or Windows PC processors for
data analysis, file I/O, and user interface operations.

ni.com/training
Add a VI Under the FPGA Target

ni.com/training
You start building the FPGA VI from the Project
Explorer. Right-click the FPGA target and select
New»VI as shown in the figure above. Save the VI in
an appropriate folder and save the project.

ni.com/training
 Demonstration

Create an FPGA VI and explore the Functions palette

supported under FPGA.
GOAL

ni.com/training
E. Front Panel Communication

FPGA Front Panel

• Use simple controls and
indicators
• Use controls and indicators only
when the value will be needed
on the host
• Use temporary controls and
indicators for debugging

ni.com/training
E. Front Panel Communication
Create the front panel for FPGA applications similar to the figure
above. It is good practice to set default values for controls because the
FPGA VI is not controlled from a monitor display, but rather through
the Host VI. The front panel controls and indicators automatically
communicate with the Host PC. Remember that a host VI serves as the
user interface and that the FPGA has a limited number of gate. So, keep
the controls and indicators on the front panel of an FPGA VI simple to
conserve space and enhance performance. Use the minimum necessary
controls and indicators for programmatic front-panel communication to
a host. You might add some temporary controls and indicators for
testing that you remove later.
Note These considerations apply only to top-level VIs and
not to subVIs.

ni.com/training
Interactive Front Panel Communication

ni.com/training
You use Interactive Front Panel Communication to communicate
between the host computer and the VI running on the FPGA as
shown in the figure above. You use Programmatic FPGA
Interface Communication to programmatically control and
communicate with FPGA VIs from host computer VIs. You will
learn alternate communication processes later in this course.
You can run the FPGA VI in Windows to check the logic of the
application before compiling. The software emulation mode
simulates the I/O operations but does not duplicate the hardware
timing. Traditional LabVIEW debugging tools are available in
emulation mode. Refer to the Testing with the Emulator section
for more information about working in emulation mode.

ni.com/training
Interactive Front Panel Communication
(continued)
FPGA has no user interface
• Must communicate data from FPGA to host PC
− Requires no additional programming
• Front panel displays on host PC
• Block diagram executes on FPGA as compiled
• Communication layer shares all control and indicator values
• Cannot use debugging tools when running FPGA VI
− Test with Emulator first, or add indicators as probes

ni.com/training
Because there is no monitor connected to the FPGA, you must view the output and provide input
from a host computer. You can use Interactive Front Panel Communication to communicate with
an FPGA VI running on an FPGA target with no additional programming. With Interactive Front
Panel Communication, the host computer displays the FPGA VI front panel window and the
FPGA target executes the FPGA VI block diagram,
The LabVIEW front panel window communicates with the FPGA target block diagram to
exchange the state of the controls and indicators. You can communicate with an FPGA target
located on the host computer or with an FPGA target located on a remote system. As the FPGA
target block diagram continues to run, the host computer updates values on the FPGA VI front
panel window as often as possible. The execution rate of the FPGA VI is not affected by the host
computer updates to the controls and indicators. The front panel data you receive during
Interactive Front Panel Communication is not deterministic.
Use Interactive Front Panel Communication between the FPGA target and the host computer to
control and test VIs running on the FPGA target. After downloading and running the FPGA VI,
keep LabVIEW open on the host computer to display and interact with the front panel window of
the FPGA VI.
During Interactive Front Panel Communication, you cannot use LabVIEW debugging tools, so
test with the emulator or add temporary controls and indicators for debugging and remove them
after testing.

ni.com/training
F. Testing with the Emulator

• Compiling—few minutes to several hours

• Verify logic before compiling
• LabVIEW bit-accurate emulation mode
• Executes logic on the Windows PC
• Traditional debugging tools are available
• Two kinds of emulation
− Random data for inputs
− Target hardware for I/O

ni.com/training
F. Testing with the Emulator
Because compiling LabVIEW code to run on the FPGA chip can take a
few minutes to several hours, LabVIEW has a bit-accurate emulation
mode to verify the logic before you initiate the compile process. The
FPGA Device Emulator accesses I/O from the device and executes the
VI logic on the Windows development computer where traditional
LabVIEW debugging tools such as execution highlighting, probes, and
breakpoints are available.
When you run an FPGA VI with the emulator, the FPGA VI runs on the
development computer, and LabVIEW communicates with the
hardware connections for the R Series DAQ device. While the timing
and triggering will not have the precision of the compiled FPGA VI, the
signals acquired and output will be the same as seen in the emulation.
This is particularly helpful because it allows you can debug the
application before you compile.

ni.com/training
Using the Emulator

1. Right-click the FPGA Target

in the Project Explorer
window and select
Properties.
2. Select General.
3. Select an Emulator option.
4. Click OK.
5. Run the VI.
*Set the Emulator to Off after test

ni.com/training
Complete the following steps to use an emulator to test an FPGA
VI:
1.Right-click the FPGA Target in the Project Explorer and select
Properties. The FPGA Target Properties dialog box appears as
shown in the figure above.
2.Select General in the Category list in the FPGA Target
Properties dialog box.
3.Select an emulation option from the Emulator pull-down menu.
4.Click OK.
5.Click Run.
Note Remember to return to the FPGA Target Properties
dialog box and turn the emulator off before
compiling.

ni.com/training
 Exercise 3-1: Creating a LabVIEW FPGA VI

Create a VI that adds two numbers and runs a benchmark

in parallel that determines how fast code is running.
GOAL

Run the VI in emulation mode and use debugging tools.

ni.com/training
G. Compiling the FPGA VI

• Click Run
• Converts graphical code to VHDL
• Generates intermediate files

ni.com/training
G. Compiling the FPGA VI
After testing the VI using emulation, you must compile and
download the VI to the FPGA. Click the Run button to initiate
the process, or manually launch the LabVIEW FPGA Compile
Server by selecting Start»All Programs»National
Instruments»LabVIEW 8.x» LabVIEW FPGA
Utilities»Compile Server on the remote computer.
The compilation process converts the graphical code to VHDL
code, generates intermediate files, and displays the window
shown in the figure above. Then the Xilinx ISE compile tools
optimize, reduce, and synthesize the VHDL code into a hardware
circuit realization of the LabVIEW code. The end result is a
bitstream file that is loaded into the FPGA chip to configure the
gate array logic.

ni.com/training
Compiling VI for FPGA Dialog Box

• Disconnect – Disconnects from the Compile Server so that you can

continue working in LabVIEW
• Follow instructions in the dialog box to reconnect

ni.com/training
The Compiling VI for FPGA dialog box, shown above, displays status information while the FPGA VI compiles. From this dialog box you can
cancel the compilation, or disconnect from the LabVIEW FPGA Compile Server to continue working in LabVIEW while the server compiles
the FPGA VI. This dialog box includes the following components:
− Client ID—Displays a unique ID that is associated with the VI that is being compiled.
− Server ID—Displays the Server Service ID on the server side. To view previous compile records, launch the LabVIEW FPGA
Compile Server by selecting Start»All Programs»National Instruments» LabVIEW 8.5»LabVIEW FPGA Utilities»Compile
Server. Click Compile List and enter the Server ID in the numeric control.
− Status—Displays the status of the compilation throughout the process.
− Refresh—Updates the client with the latest information from the server. If you do not click the Refresh button, you experience a 20-
second delay between updates from the server.
− Disconnect—Disconnects LabVIEW from the LabVIEW FPGA Compile Server while the LabVIEW FPGA Compile Server compiles
the VI. Disconnect from the LabVIEW FPGA Compile Server to perform other operations in LabVIEW while the FPGA VI is
compiling. To reconnect to the LabVIEW FPGA Compile Server, right-click the FPGA VI in the Project Explorer window and select
Reconnect to Compilation. You also can reconnect to the compilation by clicking Run on the FPGA VI or using the Beginning
Compile dialog box.
Caution Do not make changes to the FPGA VI while the LabVIEW FPGA Compile Server is
compiling. If you do make changes, you must recompile the FPGA VI.
− Stop Compilation—Stops the LabVIEW FPGA Compile Server and closes the client without finishing the compilation.

ni.com/training
LabVIEW FPGA Compile Server Dialog Box

Tools»FPGA Module»Start Local Compile Server to view

previous compile reports
Click Compile List

ni.com/training
The LabVIEW FPGA Compile Server window, shown above, displays compilation information when
you compile a VI. You also can launch the LabVIEW FPGA Compile Server manually by selecting
Tools»FPGA Module»Start Local Compile Server. The LabVIEW FPGA Compile Server does not
close automatically when compilation finishes. Click Stop Server to close the window. The LabVIEW
FPGA Compile Server Window contains the following components:
− Compile Status—Displays status information for the current compile. The Compile Status section
is disabled until the compile begins.
− Server Service ID—Displays a number that is associated with the VI you are compiling. To view
past compiles, click Compile List and enter the Server Service ID in the numeric control to view
the compilation report.
− Client Name—Displays the name of the computer on which the FPGA VI resides.
− Client Service ID—Displays the ID that is associated with the VI that is being compiled.
− Status—Displays the status of the compilation. Status updates throughout the compilation.
− Start Time—Displays the time that the server started compiling the VI.
− Last Update Time—Displays the time that the Compile Status information was last updated.
− Details—Displays information about the conversion of the VI into the bitstream that is downloaded
to the FPGA.
− Stop Compile—Cancels the current compile. This button does not shut down the LabVIEW FPGA
Compile Server window.

ni.com/training
ni.com/training
− Compile List—Displays the Manage All Server Records dialog box, which
you can use to browse all past compiles and current compiles in the compile
queue. You also can use the Manage All Server Records dialog box to delete
information about old or unwanted LabVIEW FPGA Compile Server
compiles.
− Server Status—Displays the status of the LabVIEW FPGA Compile Server.
− Stop Server—Shuts down the server. Stopping the LabVIEW FPGA Compile
Server cancels current compilations.
− Configure—Displays the Configure Server dialog box. Use the Configure
Server dialog box to configure properties for the LabVIEW FPGA Compile
Server. You can fix timeout errors that appear when the LabVIEW FPGA
Compile Server sends or receives files by increasing the Network timeout
(ms) value. Modify the Port number if the default port, 96, conflicts with ports
on the network. If you modify the Port number, you must modify it in the
Configure Server dialog box and in the Configure Compile Settings dialog
box.

ni.com/training
Successful Compile Report

ni.com/training
The Successful Compile Report dialog box, shown above, reports the results of the compile process. The first
line displays the status or result of the compile, whether or not the compile was successful. If the program is too
big or if the clock speed is set too high, it may not be successful.
The report shows the resulting FPGA circuit uses about 7% of the slices. This dialog box includes the following
information:
Summary—This tab can include the following categories of information:
• Device Utilization Summary—Might contain the following information:
– Number of slices—Specifies how much of the FPGA logic the compiled FPGA VI uses. Slices are a
combination of LUTs and FFs
– Number of IOBs—Specifies the number of Input/Output Blocks used
– Number of MULT18X18s—Specifies how many multipliers the compiled FPGA VI uses
– Number of RAMB16s—Specifies how much RAM the compiled FPGA VI uses
– BUFGMUXs—Portal to the clock net, which is used to clock FFs
• Clock Rates—Might contain the following information:
– Requested Rate—Displays the clock rate at which the compiled FPGA VI runs, which is 40 MHz by
default
– Theoretical Maximum—Displays the theoretical maximum compile rate for the
FPGA VI.

ni.com/training
Advanced—This tab includes the xflow.log and .twr files.
If you have previously selected the Do not show this message in the future?
checkbox you will no longer see the compile report. To re-enable the compile
report you must modify the LabVIEW .ini file. Make sure the line
nirviShowCompileReport=TRUE exists in the .ini file.
For small applications, the compiler does not optimize as completely as for
larger applications. As the FPGA reaches 90% optimization, the compiler
performs heavy optimization.
After you click OK in the Successful Compile Report dialog box, the VI runs
on the FPGA and communicates with the Windows PC through Interactive
Front Panel Communication. Data for the front panel objects are
communicated over the CompactRIO bus to the controller and over the
Ethernet to the host PC several times per second, typically about 10 S/s.
To view previous compile reports from the Project Explorer window, select
Tools»FPGA Module»Start Local Compile Server to display the LabVIEW
FPGA Compile Server window. Click Compile List to display the Manage All
Server Records dialog box.

ni.com/training
 Exercise 3-2: Compile a LabVIEW FPGA VI

Compile the application created in Exercise 3-1.

GOAL

ni.com/training
Summary—Quiz

1. The FPGA VI runs in an 2. You must know VHDL

operating system on the programming to reconfigure
FPGA processor. the FPGA.
a. True a. True
b. False b. False

ni.com/training
Summary—Quiz

3. The FPGA can achieve true, 4. Interactive Front Panel

simultaneous parallel Communication runs the front
processing of parallel panel on the Windows PC and
operations. the circuit configured from the
a. True block diagram on the FPGA.
b. False a. True
b. False

ni.com/training
1.False
2.False
3. True
4. True

ni.com/training