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Compal Confidential
2 2

Cougar
LA-6851P Schematics Document
Intel Pine View Processor/ Tiger point
3
2010-10-10 3

REV: 1.0

Toshiba Satellite NB500 NB505


4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 1 of 36
A B C D E
A B C D E

Compal Confidential
Model Name : PBU00
File Name : LA-6851P
1
Thermal Sensor Low Power Clock Generator 1

Fan Control EMC1402 ICS9LVRS387AKLFT MLF


page 24
page 7 page 9

CRT Conn.
page 15
Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM
Intel Pineview-M page 10

LED Conn. LVDS


page 16 ONE CHANNEL (22x22mm) page 6,7,8 1.5V DDRIII 667

2
DMI x 2 2

PCIeMini Card
WWAN USB Conn X3 Int. Camera
(FULL)
USB port 6 USB USB USB port 0,1,4 USB port 7
page 16
5V 480MHz 5V 480MHz page 18,21 page 16
PCIeMini Card
PCIe 1x [2]
WLAN +BT COMBO (HALF) 1.5V 2.5GHz(250MB/s)
Tiger Pointer
PCIe port 2 USB
page 16 Card Reader Card Reader Conn.
RTL5137 page 23
PCIe 1x USB port 3 page 23
(17x17mm)
RJ45 RTL8105E 1.5V 2.5GHz(250MB/s) SATA port 0 SATA HDD
page 22
10/100 LAN 5V 1.5GHz(150MB/s)
page 19
PCIe port 3 page 22
page 11,12,13,14
3 3
RTC CKT.
page 13 HD Audio 3.3V 24.576MHz/48Mhz

3.3V 33 MHz
LPC BUS
DC/DC Interface CKT. HDA Codec
ALC269
page 26 page 20

ENE KB926 E0
page 24
Power Circuit DC/DC
Int.
page 27~35 MIC CONN MIC CONN HP CONN SPK CONN
page 20 page 21 page 21 page 21
Touch Pad Int.KBD SPI ROM (10A 1X) (10B 2X)
page 26 page 25 page 25
4
Power/B 4

page 26

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 2 of 36
A B C D E
A B C D E

Voltage Rails
1 SIGNAL 1
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5 G3
Full ON HIGH HIGH HIGH ON ON ON ON
VIN Adapter power supply (19V) ON ON ON OFF
B+ AC or battery power rail for power circuit. ON ON ON ON S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
+CPU_CORE Core voltage for CPU ON OFF OFF OFF
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
+0.89VS 0.89VS GFX support voltage ON OFF OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF OFF S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
+1.05VS VCCP switched power rail ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF OFF
+1.5V 1.5V power rail for DDR ON ON OFF OFF
+1.8VS 1.8VS switched power rail ON OFF OFF OFF
+3VALW 3.3V always on power rail ON ON ON OFF
+3V_LAN 3.3V power rail for LAN ON ON OFF OFF
BTO Option Table
+3V_WLAN 3.3V power rail for LAN ON ON OFF OFF
2 +3VS 3.3V switched power rail ON ON OFF OFF 2

+5VALW 5V always on power rail ON OFF ON OFF Function Mini PCI-E SLOT CAMERA & MIC BLUE TOOTH Clock gen
+5VS 5V switched power rail ON OFF OFF OFF
+VSB VSB always on power rail ON ON ON OFF
description
+RTCVCC RTC power ON ON ON ON explain Wi-Fi WiMax 3GGPS 3G CAMERA MIC BLUE TOOTH Tpye

BTO WLAN@ WIMAX@ 3GGPS@ 3G@ CAM@ MIC@ BT@ low@ normal@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Function
description
explain
BTO
3 3

EC SM Bus1 address EC SM Bus2 address


Device Address Device Address
Smart Battery 0001 011X b EMC1402 1001 010X b

ICH7M SM Bus address


Device Address

Clock Generator 1101 001Xb


(SLG8SP556VTR)
DDR DIMMA 1010 000Xb
WWAN/WLAN

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 3 of 36
A B C D E
5 4 3 2 1

D D

C C

B B

A
Security Classification Compal Secret Data Compal Electronics, Inc. A

Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 4 of 36
5 4 3 2 1
5 4 3 2 1

B+ DESIGN CURRENT 250mA Cougar Power Map


Ipeak=6.97A, Imax=4.88A
DESIGN CURRENT 522mA
+3VALWP +-5%
** The SW just is reserved.
The power passes by jump or
UP6182CQAG 0-ohm resistor. WOL_EN#
D ** P-CHANNEL +3V_LAN D
AO3413 DESIGN CURRENT 300mA

Ipeak=3.98A, Imax=2.8A +5VALWP +-5%


DESIGN CURRENT 3010mA

SUSP
N-CHANNEL +5VS
DESIGN CURRENT 2286mA
SI4800BDY

SUSP
N-CHANNEL DESIGN CURRENT 5586mA
+3VS
C C

SI4800BDY ENVDD
P-CHANNEL +LCD_VDD
AO3413 DESIGN CURRENT 2000mA

SUSP#

DESIGN CURRENT 2640mA


+0.89VSP
SY8033BDBC
SUSP#

SY8033BDBC Ipeak=1.308A, Imax=4A +1.05VSP +-5%


DESIGN CURRENT 3489mA

VR_ON

B Imax=3.5A DESIGN CURRENT 6000mA +CPU_CORE B

ADP3211AMNR2G

SYSON
Ipeak=19.6A, Imax=13.72A +1.5VP +-5%
DESIGN CURRENT 2000mA
G5603RU1U
SUSP#
DESIGN CURRENT 2112mA +1.5VSP
IRF8113PBF

SUSP

DESIGN CURRENT 500mA


+0.75VSP
UP7711U8
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401986 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 02, 2011 Sheet 5 of 36
5 4 3 2 1
5 4 3 2 1

<10> DDR_A_DQS#[0..7]
PINEVIEW_M
N455@ N475@
U1 U1 <10> DDR_A_D[0..63]
U80610006237AA SLBX9 A0 1.66G AU80610006240AA SLBX5 U1B
REV = 1.1
<10> DDR_A_DM[0..7]
PINEVIEW_M DDR_A_MA0 AH19 AD3 DDR_A_DQS0
U1A <10> DDR_A_DQS[0..7] DDR_A_MA1 DDR_A_MA_0 DDR_A_DQS_0 DDR_A_DQS#0
AJ18 DDR_A_MA_1 DDR_A_DQS#_0 AD2
DDR_A_MA2 AK18 AD4 DDR_A_DM0
<10> DDR_A_MA[0..14] DDR_A_MA3 DDR_A_MA_2 DDR_A_DM_0
REV = 1.1 AK16 DDR_A_MA_3
DMI_RXP0_C F3 G2 DMI_TXP0 <12> DDR_A_MA4 AJ14 AC4 DDR_A_D0
DMI_RXN0_C DMI_RXP_0 DMI_TXP_0 DDR_A_MA5 DDR_A_MA_4 DDR_A_DQ_0 DDR_A_D1
F2 DMI_RXN_0 DMI_TXN_0 G1 DMI_TXN0 <12> AH14 DDR_A_MA_5 DDR_A_DQ_1 AC1
DMI_RXP1_C H4 H3 DMI_TXP1 <12> DDR_A_MA6 AK14 AF4 DDR_A_D2
DMI_RXN1_C DMI_RXP_1 DMI_TXP_1 DDR_A_MA7 DDR_A_MA_6 DDR_A_DQ_2 DDR_A_D3
G3 DMI_RXN_1 DMI_TXN_1 J2 DMI_TXN1 <12> AJ12 DDR_A_MA_7 DDR_A_DQ_3 AG2
DDR_A_MA8 AH13 AB2 DDR_A_D4
D DMI DDR_A_MA9 DDR_A_MA_8 DDR_A_DQ_4 DDR_A_D5 D
AK12 DDR_A_MA_9 DDR_A_DQ_5 AB3
DDR_A_MA10 AK20 AE2 DDR_A_D6
DDR_A_MA11 DDR_A_MA_10 DDR_A_DQ_6 DDR_A_D7
AH12 DDR_A_MA_11 DDR_A_DQ_7 AE3
DDR_A_MA12 AJ11
DDR_A_MA13 DDR_A_MA_12 DDR_A_DQS1
<9> CLK_CPU_EXP# N7 EXP_CLKINN EXP_RCOMPO L10 AJ24 DDR_A_MA_13 DDR_A_DQS_1 AB8
<9> CLK_CPU_EXP N6 L9 DMI_IRCOMP R492 DDR_A_MA14 AJ10 AD7 DDR_A_DQS#1
EXP_CLKINP EXP_ICOMPI R493 49.9_0402_1% DDR_A_MA_14 DDR_A_DQS#_1 DDR_A_DM1
EXP_RBIAS L8 DDR_A_DM_1 AA9
R10 750_0402_1%
EXP_TCLKINN DDR_A_WE# DDR_A_D8
R9 EXP_TCLKINP RSVD_TP N11 T1 <10> DDR_A_WE# AK22 DDR_A_WE# DDR_A_DQ_8 AB6
N10 P11 Pull-down must be placed DDR_A_CAS# AJ22 AB7 DDR_A_D9
RSVD RSVD_TP T2 <10> DDR_A_CAS# DDR_A_CAS# DDR_A_DQ_9
N9 DDR_A_RAS# AK21 AE5 DDR_A_D10
RSVD within 500 mils from Pineview-M <10> DDR_A_RAS# DDR_A_RAS# DDR_A_DQ_10
AG5 DDR_A_D11
DDR_A_BS0 DDR_A_DQ_11 DDR_A_D12
<10> DDR_A_BS0 AJ20 DDR_A_BS_0 DDR_A_DQ_12 AA5
DDR_A_BS1 AH20 AB5 DDR_A_D13
<10> DDR_A_BS1 DDR_A_BS_1 DDR_A_DQ_13
K2 K3 DDR_A_BS2 AK11 AB9 DDR_A_D14
RSVD RSVD <10> DDR_A_BS2 DDR_A_BS_2 DDR_A_DQ_14
J1 L2 AD6 DDR_A_D15
RSVD RSVD DDR_A_DQ_15
M4 RSVD RSVD M2
L3 N2 AD8 DDR_A_DQS2
RSVD RSVD DDR_CS0# DDR_A_DQS_2 DDR_A_DQS#2
<10> DDR_CS0# AH22 DDR_A_CS#_0 DDR_A_DQS#_2 AD10
DDR_CS1# AK25 AE8 DDR_A_DM2
1 OF 6 <10> DDR_CS1# DDR_A_CS#_1 DDR_A_DM_2
AJ21
PINEVIEW-M_FCBGA8559 AJ25
DDR_A_CS#_2
AG8 DDR_A_D16
DDR_A_CS#_3 DDR_A_DQ_16 DDR_A_D17
DDR_A_DQ_17 AG7
N550@ DDR_CKE0 AH10 AF10 DDR_A_D18
<10> DDR_CKE0 DDR_A_CKE_0 DDR_A_DQ_18
DDR_CKE1 AH9 AG11 DDR_A_D19
<10> DDR_CKE1 DDR_A_CKE_1 DDR_A_DQ_19
SMPWROK AK10 AF7 DDR_A_D20
DDR_A_CKE_2 DDR_A_DQ_20

0.1U_0402_16V4Z
AJ8 AF8 DDR_A_D21
DDR_A_CKE_3 DDR_A_DQ_21 DDR_A_D22
DDR_A_DQ_22 AD11

10K_0402_5%
M_ODT0 AK24 AE10 DDR_A_D23
<10> M_ODT0 DDR_A_ODT_0 DDR_A_DQ_23
<12> DMI_RXP0 C9481 2 DMI_RXP0_C M_ODT1 AH26
<10> M_ODT1 DDR_A_ODT_1

2
0.1U_0402_10V6K 1 AH24 AK5 DDR_A_DQS3
DDR_A_ODT_2 DDR_A_DQS_3

1
D DDR_A_DQS#3
AK27 DDR_A_ODT_3 DDR_A_DQS#_3 AK3
C C9491 DMI_RXN0_C SYSON# Q37 DDR_A_DM3 C
<12> DMI_RXN0 2 <27> SYSON# 2 DDR_A_DM_3 AJ3
0.1U_0402_10V6K G
S 2N7002_SOT23 2 DDR_A_D24
AH1

1
DDR_A_DQ_24

R880

C1063
<12> DMI_RXP1 C9501 2 DMI_RXP1_C M_CLK_DDR0 AG15 AJ2 DDR_A_D25
<10> M_CLK_DDR0 DDR_A_CK_0 DDR_A_DQ_25
0.1U_0402_10V6K M_CLK_DDR#0 AF15 AK6 DDR_A_D26
<10> M_CLK_DDR#0 DDR_A_CK_0# DDR_A_DQ_26
@ M_CLK_DDR1 AD13 AJ7 DDR_A_D27
<10> M_CLK_DDR1 DDR_A_CK_1 DDR_A_DQ_27
<12> DMI_RXN1 C9511 2 DMI_RXN1_C @ M_CLK_DDR#1 AC13 AF3 DDR_A_D28
<10> M_CLK_DDR#1 DDR_A_CK_1# DDR_A_DQ_28
0.1U_0402_10V6K AH2 DDR_A_D29
+1.5V DDR_A_DQ_29 DDR_A_D30
DDR_A_DQ_30 AL5
AC15 AJ6 DDR_A_D31
DDR_A_CK_3 DDR_A_DQ_31
AD15 DDR_A_CK_3#

1
Close to CPU AF13 AG22 DDR_A_DQS4
+5VALW @ R885 DDR_A_CK_4 DDR_A_DQS_4 DDR_A_DQS#4
AG13 DDR_A_CK_4# DDR_A_DQS#_4 AG21
10K_0402_5% AD19 DDR_A_DM4
DDR_A_DM_4

1
AE19 DDR_A_D32

3 2
@ R884 DDR_A_DQ_32 DDR_A_D33
AD17 RSVD DDR_A_DQ_33 AG19
1K_0402_5% AC17 AF22 DDR_A_D34
@Q40B
@ Q40B RSVD DDR_A_DQ_34 DDR_A_D35
<32> SM_PWROK 1 2 AB15 RSVD DDR_A_DQ_35 AD22
R881 0_0402_5% AB17 AG17 DDR_A_D36

2
RSVD DDR_A_DQ_36 DDR_A_D37
5 AF19
XDP Reserve +1.05VS
<10> DRAMRST#
DDR_A_DQ_37
DDR_A_DQ_38 AE21 DDR_A_D38

6
2N7002DW-T/R7_SOT363-6 AD21 DDR_A_D39

4
@Q40A DDR_A_DQ_39
<7> XDP_TDI XDP_TDI R495@ 1 2 @ R882 AE26 DDR_A_DQS5
51_0402_5% +1.5V @R878
@ R878 SMPWROK AB4 DDR_A_DQS_5 DDR_A_DQS#5
<13,24> PM_SLP_S4# 1 2 2 DRAM_PWROK DDR_A_DQS#_5 AG27
<7> XDP_TMS XDP_TMS R496@ 1 2 +1.5V 1 2 AK8 AJ27 DDR_A_DM5
51_0402_5% 0_0402_5% 2N7002DW-T/R7_SOT363-6 DRAM_RST# DDR_A_DM_5
1

1
<7> XDP_TDO XDP_TDO R499@ 1 2 @ R886 10K_0402_5% AE24 DDR_A_D40
51_0402_5% R500 DDR_A_DQ_40 DDR_A_D41
<24,27,32> SYSON 1 2 DDR_A_DQ_41 AG25
<7> XDP_PREQ# XDP_PREQ# R501@ 1 2 T3 AB11 AD25 DDR_A_D42
51_0402_5% 0_0402_5% 1K_0402_1% RSVD_TP DDR_A_DQ_42 DDR_A_D43
T4 AB13 RSVD_TP DDR_A_DQ_43 AD24
B DDR_A_D44 B
AC22

2
DDR_VREF DDR_A_DQ_44 DDR_A_D45
AL28 DDR_VREF DDR_A_DQ_45 AG24
DDR_RPD AK28 AD27 DDR_A_D46
DDR_RPD DDR_A_DQ_46

1
<7> XDP_TRST# XDP_TRST# R502@ 1 2 Reserve PM_SLP_S4# to turn on DRAM_PWROK 1 DDR_RPU AJ26 AE27 DDR_A_D47
51_0402_5% R504 C953 DDR_RPU DDR_A_DQ_47

<7> XDP_TCK XDP_TCK R505@ 1 2 AK29 AE30 DDR_A_DQS6


51_0402_5% 1K_0402_1% 0.1U_0402_16V4Z RSVD DDR_A_DQS_6 DDR_A_DQS#6
DDR_A_DQS#_6 AF29
2 DDR_A_DM6
AF30

2
DDR_A_DM_6
+1.5V DDR_A AG31 DDR_A_D48
DDR_A_DQ_48 DDR_A_D49
DDR_A_DQ_49 AG30
AD30 DDR_A_D50
DDR_A_DQ_50 DDR_A_D51
# MP Remove XDP resistor for ESD DDR_A_DQ_51 AD29
AJ30 DDR_A_D52
DDR_A_DQ_52 DDR_A_D53
DDR_A_DQ_53 AJ29
AE29 DDR_A_D54
R497 DDR_RPU DDR_A_DQ_54 DDR_A_D55
DDR_A_DQ_55 AD28
1
80.6_0402_1% AB27 DDR_A_DQS7
C952 DDR_A_DQS_7 DDR_A_DQS#7
DDR_A_DQS#_7 AA27
0.01U_0402_16V7K R503 DDR_RPD AB26 DDR_A_DM7
+5VALW +1.5V 2 DDR_A_DM_7
80.6_0402_1% AA24 DDR_A_D56
DDR_A_DQ_56 DDR_A_D57
DDR_A_DQ_57 AB25
W24 DDR_A_D58
DDR_A_DQ_58 DDR_A_D59
DDR_A_DQ_59 W22
AB24 DDR_A_D60
DDR_A_DQ_60 DDR_A_D61
DDR_A_DQ_61 AB23
AA23 DDR_A_D62
DDR_A_DQ_62 DDR_A_D63
1 1 1 1 DDR_A_DQ_63 W27
C1050 C1065
C203 C204
A 68P_0402_50V8J 0.1U_0402_16V4Z 68P_0402_50V8J 0.1U_0402_16V4Z A
2 OF 6
2 2 2 2
PINEVIEW-M_FCBGA8559

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title
2010.07.12 RF request
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401986 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 02, 2011 Sheet 6 of 36
5 4 3 2 1
5 4 3 2 1

PINEVIEW_M
U1C U1D PINEVIEW_M

T8 D12 XDP_RSVD_00 REV = 1.1 REV = 1.1


T18 A7 M30 U25 E7 H_SMI#
XDP_RSVD_01 CRT_HSYNC GMCH_CRT_HSYNC <15> <16> LCD_TXCLK- LA_CLKN SMI# H_SMI# <11>
T9 D6 M29 U26 H7 H_A20M#
XDP_RSVD_02 CRT_VSYNC GMCH_CRT_VSYNC <15> <16> LCD_TXCLK+ LA_CLKP A20M# H_A20M# <11>
T10 C5 <16> LCD_TXOUT0- R23 H6 H_FERR#
XDP_RSVD_03 LA_DATAN_0 FERR# H_FERR# <11>
T19 C7 <16> LCD_TXOUT0+ R24 F10 H_INTR
XDP_RSVD_04 LA_DATAP_0 LINT0 H_INTR <11>
D T11 C6 N31 GMCH_CRT_R <16> LCD_TXOUT1- N26 F11 H_NMI D
XDP_RSVD_05 CRT_RED GMCH_CRT_R <15> LA_DATAN_1 LINT1 H_NMI <11>
T20 D8 P30 GMCH_CRT_G <16> LCD_TXOUT1+ N27 E5 H_IGNNE#
XDP_RSVD_06 CRT_GREEN GMCH_CRT_G <15> LA_DATAP_1 IGNNE# H_IGNNE# <11>
T12 B7 P29 GMCH_CRT_B <16> LCD_TXOUT2- R26 F8 H_STPCLK#
XDP_RSVD_07 CRT_BLUE GMCH_CRT_B <15> LA_DATAN_2 STPCLK# H_STPCLK# <11>

ICH
T13 A9 XDP_RSVD_08 CRT_IRTN N30 <16> LCD_TXOUT2+ R27 LA_DATAP_2
XDP_RSVD_9 D9

VGA
XDP_RSVD_09 H_DPRSTP#
T14 C8 XDP_RSVD_10 DPRSTP# G6 H_DPRSTP# <13>
T15 B8 R510 be placed <500 mils to U1.P28 R509 L_IBG R22 G10 H_DPSLP#
XDP_RSVD_11 LIBG DPSLP# H_DPSLP# <13>
T44 C10 L31 2.37K_0402_1% J28 G8 H_INIT#
XDP_RSVD_12 CRT_DDC_DATA GMCH_CRT_DATA <15> LVBG INIT# H_INIT# <11>
T17 D10 XDP_RSVD_13 CRT_DDC_CLK L30 GMCH_CRT_CLK <15> R509 be placed U1.R22 N22 LVREFH PRDY# E11 T48
T21 B11 N23 F15 XDP_PREQ#
XDP_RSVD_14 R510 665_0402_1% LVREFL PREQ# XDP_PREQ# <6>
T22 B10 P28 DAC_IREF ENBKL L27
XDP_RSVD_15 DAC_IREF <24> ENBKL LBKLT_EN

LVDS
T23 B12 XDP_RSVD_16 <16> GMCH_INVT_PWM L26 LBKLT_CTL Close to CPU
T24 C11 Y30 CPU_DREFCLK L23 E13 H_THERMTRIP#
XDP_RSVD_17 REFCLKINP CPU_DREFCLK <9> LCTLA_CLK THERMTRIP# H_THERMTRIP# <11>
Y29 CPU_DREFCLK# K25
REFCLKINN CPU_DREFCLK# <9> LCTLB_DATA
AA30 CPU_SSCDREFCLK K23
REFSSCLKINP CPU_SSCDREFCLK <9> <16> LCD_EDID_CLK LDDC_CLK +1.05VS
AA31 CPU_SSCDREFCLK# <16> LCD_EDID_DATA K24 Close to CPU
REFSSCLKINN CPU_SSCDREFCLK# <9> LDDC_DATA
<16> GMCH_ENVDD H26 LVDD_EN
T25 L11 C18 H_PROCHOT# 68_0402_5% R511
RSVD +3VS PROCHOT# H_PWRGD
CPUPWRGOOD W1 H_PWRGD <13>
0_0402_5%
R512

1
K29 PM_EXTTS#1
PM_EXTTS#_1/DPRSLPVR PM_DPRSLPVR <13>
J30 PM_EXTTS#0 R513 A13 H_GTLREF
PM_EXTTS#_0 PM_EXTTS#0 <10> GTLREF
L5 PCH_POK 10K_0402_5% H27
PWROK PCH_POK <13> VSS
AA3 PLTRST#
RSTIN# PLTRST# <13,17,22>
Close to Processor pin

2
PM_EXTTS#0
W8 CLK_CPU_HPLCLK# L6
HPL_CLKINN CLK_CPU_HPLCLK# <9> RSVD
W9 CLK_CPU_HPLCLK E17
HPL_CLKINP CLK_CPU_HPLCLK <9> RSVD
C G11 C
T43 BPM_1_0#
AA7 E15 H10 CLK_CPU_BCLK#
MISC

T26 RSVD_TP T47 BPM_1_1# BCLKN CLK_CPU_BCLK# <9>


T27 AA6 T46 G13 J10 CLK_CPU_BCLK
RSVD_TP BPM_1_2# BCLKP CLK_CPU_BCLK <9>
T28 R5 RSVD_TP T45 F13 BPM_1_3#
T29 R6 K5 CPU_BSEL0
RSVD_TP BSEL_0 CPU_BSEL0 <9>
To be placed <250 mils to U1 ball Close to CPU T30 B18 H5 CPU_BSEL1
BPM_2_0#/RSVD BSEL_1 CPU_BSEL1 <9>
T31 AA21 T32 B20 K6 CPU_BSEL2
RSVD_TP BPM_2_1#/RSVD BSEL_2 CPU_BSEL2 <9>

CPU
T33 W21 RSVD_TP R514 T34 C20 BPM_2_2#/RSVD
T35 T21 GMCH_CRT_R 1 2 T36 B21 H30 CPU_VID0
RSVD_TP BPM_2_3#/RSVD VID_0 CPU_VID0 <35>
T37 V21 150_0402_1% H29 CPU_VID1
RSVD_TP VID_1 CPU_VID1 <35>
GMCH_CRT_G 1 R515 2 Close to CPU H28 CPU_VID2
VID_2 CPU_VID2 <35>
150_0402_1% G30 CPU_VID3
VID_3 CPU_VID3 <35>
GMCH_CRT_B 1 R516 2 T38 G5 G29 CPU_VID4
RSVD VID_4 CPU_VID4 <35>
150_0402_1% XDP_TDI D14 F29 CPU_VID5
<6> XDP_TDI TDI VID_5 CPU_VID5 <35>
ENBKL R517 XDP_TDO D13 E29 CPU_VID6
<6> XDP_TDO TDO VID_6 CPU_VID6 <35>
100K_0402_5% XDP_TCK B14
<6> XDP_TCK TCK
XDP_TMS C14 L7
<6> XDP_TMS TMS RSVD
XDP_TRST# C16 D20
<6> XDP_TRST# TRST# RSVD
To be placed <500 mils to U1 ball RSVD H13
RSVD D18
H_THERMDA D30
H_THERMDC THRMDA_1
E30 THRMDC_1 RSVD_TP K9 T39
RSVD_TP D19 T40
RF@C205
RF@C205 K7 H_EXTBGREF
LCD_EDID_CLK 1 EXTBGREF
2

12P_0402_50V8J

RF@C206
RF@ C206
B LCD_EDID_DATA 1 B
2 C30 THRMDA_2/RSVD
D31 THRMDC_2/RSVD
XDP_RSVD_9 12P_0402_50V8J
3 OF 6
4 OF 6
PINEVIEW-M_FCBGA8559 PINEVIEW-M_FCBGA8559
2

R518 placed within 0.5" placed within 0.5" of processor


1K_0402_5% 2010.07.12 RF request H_DPRSTP# C954 1 @2 220P_0402_50V7K of processor pin. pin and 5 mils spacing
1

H_DPSLP# C955 1 @2 220P_0402_50V7K


# PVT C205, C206 change to +1.05VS +1.05VS
12p and stuff for RF H_PWRGD C956 1 @2 220P_0402_50V7K

H_A20M# C957 1 @2 220P_0402_50V7K


R519 R520
+3VS H_IGNNE# C958 1 @2 220P_0402_50V7K 1K_0402_1% 976_0402_1%
CPU THERMAL SENSOR H_INIT# C959 1 2 220P_0402_50V7K
H_GTLREF H_EXTBGREF
H_INTR C960 1 2 220P_0402_50V7K
0.1U_0402_16V4Z

1
2 1
C961 H_FERR# C962 1 @2 220P_0402_50V7K C963 R521 C964 R522
U2 @ 2K_0402_1% 3.3K_0402_1%
2 H_NMI C965 1 @2 220P_0402_50V7K 220P_0402_50V7K 1U_0402_6.3V6K
1 2
1 8 EC_SMB_CK2 EC_SMB_CK2 <24> H_SMI# C966 1 @2 220P_0402_50V7K
VDD SMCLK
A A
H_THERMDA 2 7 EC_SMB_DA2 H_STPCLK# C967 1 @2 220P_0402_50V7K
DP SMDATA EC_SMB_DA2 <24>
C968
1 2 H_THERMDC 3 6 2 1 +3VS ESD request
2200P_0402_50V7K DN ALERT# @ R523 10K_0402_5% # PVT C959, C960 stuff for ESD
CPU_THERM# 4 5
THERM# GND
+3VS 1 2
Security Classification Compal Secret Data Compal Electronics, Inc.
R524 10K_0402_5% 2010/06/27 2011/6/27 Title
EMC1402-1-ACZL-TR_MSOP8
Issued Date Deciphered Date
Address:0100_1100 EMC1402-1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
Address:0100_1101 EMC1402-2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 7 of 36
5 4 3 2 1
5 4 3 2 1

+1.05VS

R525
1 2 +VCCA_VCCD
U1F PINEVIEW_M
0_0805_5%

22U_0805_6.3V6M
0.1U_0402_10V6K

0.1U_0402_10V6K

1U_0402_6.3V6K
4.7U_0603_6.3V6K
U1E +CPU_CORE A11 REV = 1.1
F24
VSS VSS
PINEVIEW_M 3500mA 1U_0402_6.3V6K 1 2 1 1 1 A16 VSS VSS F28
1U_0402_6.3V6K

C969

C970

C971

C972

C973
VCC A23 A19 VSS VSS F4
VCC A25 A29 RSVD_NCTF VSS G15
+0.89VS REV = 1.1
A27 A3 G17
VCC 1 1 1 1 RSVD_NCTF VSS
1380mA B23 C974 C975 C976 C977 @2 @1 2 2 2
A30 G22
D VCC RSVD_NCTF VSS D
T13 VCCGFX VCC B24 A4 RSVD_NCTF VSS G27
T14 B25 1U_0402_6.3V6K AA13 G31
VCCGFX VCC 2 2 2 2 VSS VSS
T16 VCCGFX VCC B26 AA14 VSS VSS H11
T18 VCCGFX VCC B27 AA16 VSS VSS H15
T19 VCCGFX VCC C24 1U_0402_6.3V6K AA18 VSS VSS H2
V13 VCCGFX VCC C26 +1.05VS AA2 VSS VSS H21
V19 VCCGFX VCC D23 AA22 VSS VSS H25
W14 VCCGFX VCC D24 R526 AA25 VSS VSS H8
W16 D26 Please closed U1 ball 1 2 +RING_EAST AA26 J11
VCCGFX VCC VSS VSS

1U_0402_6.3V6K
W18 D28 0_0603_5% AA29 J13

GFX/MCH
VCCGFX VCC VSS VSS
W19 VCCGFX VCC E22 1 AA8 VSS VSS J15
+1.5V

C978
R527 VCC E24 AB19 VSS VSS J4
E27 +CPU_CORE AB21 K11

CPU
VCC VSS VSS
1 2 1U_0402_6.3V6K 1U_0402_6.3V6K +VCC_SM
VCC F21 2 x 330uF(9mohm/2) AB28 VSS VSS K13
2
VCC F22 AB29 VSS VSS K19
0_1206_5% 2 2 2 2 2 F25 1 1 AB30 K26
VCC VSS VSS
VCC G19 AC10 VSS VSS K27
C979 C980 C981 C982 C983 G21 + C984 + C985 1 R528 2 +RING_WEST AC11 K28
VCC VSS VSS

1U_0402_6.3V6K

1U_0402_6.3V6K
VCC G24 AC19 VSS VSS K30
1 1 1 1 1 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M 0_0603_5%
H17 1 1 AC2 K4

GND
VCC 2 2 VSS VSS

C986

C987
VCC H19 AC21 VSS VSS K8
22U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K H22 AC28 L1
VCC VSS VSS
VCC H24 AC30 VSS VSS L13
2 2
VCC J17 AD26 VSS VSS L18
+VCC_SM AK13 J19 AD5 L22
VCCSM VCC +CPU_CORE VSS VSS
Please closed U1 ball AK19 VCCSM VCC J21 AE1 VSS VSS L24
AK9 VCCSM VCC J22 1 R529 2 +LGI_VID AE11 VSS VSS L25

1U_0402_6.3V6K
AL11 VCCSM VCC K15 AE13 VSS VSS L29
AL16 K17 0_0603_5% @ 1 AE15 M28
VCCSM VCC VSS VSS

C988
AL21 VCCSM VCC K21 AE17 VSS VSS M3
+1.5V

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
AL25 VCCSM VCC L14 AE22 VSS VSS N1
VCC L16 1 1 1 AE31 VSS VSS N13
2

C989

C990

C991
C 22U_0805_6.3V6M +VCCCK_DDR C
1 2 VCC L19 AF11 VSS VSS N18
VCC L21 AF17 VSS VSS N24
R530 2270mA N14 AF21 N25
0_0603_5% VCC 2 2 2 +VCC_DMI VSS VSS
1 1 VCC N16 1 R531 2 AF24 VSS VSS N28

1U_0402_6.3V6K

1U_0402_6.3V6K
C992 C993 +VCCCK_DDR AK7 N19 AF28 N4
VCCCK_DDR VCC 0_0603_5% VSS VSS
AL7 VCCCK_DDR VCC N21 1 1 AG10 VSS VSS N5

C994

C995
1U_0402_6.3V6K AG3 N8
2 2 VSS VSS
AH18 VSS VSS P13
+VCCA_VCCD U10 AH23 P14
VCCA_DDR 2 2 VSS VSS
DDR

1880mA U5 VCCA_DDR AH28 VSS VSS P16


U6 +CPU_CORE AH4 P18
VCCA_DDR VSS VSS
Please closed U1 ball U7 VCCA_DDR AH6 VSS VSS P19
POWER

U8 VCCA_DDR AH8 VSS VSS P21

1
U9 VCCA_DDR AJ1 RSVD_NCTF VSS P3
V2 R532 AJ16 P4
VCCA_DDR VSS VSS
V3 VCCA_DDR AJ31 RSVD_NCTF VSS R25
V4 100_0402_5% AK1 R7
VCCA_DDR RSVD_NCTF VSS
W10 AK2 R8

2
VCCA_DDR RSVD_NCTF VSS
W11 VCCA_DDR AK23 VSS VSS T11
C29 VCCSENSE AK30 U22
VCCSENSE VCCSENSE <35> +1.8VS RSVD_NCTF VSS
AA10 B29 VSSSENSE AK31 U23
VCCACK_DDR VSSSENSE VSSSENSE <35> RSVD_NCTF VSS
AA11 VCCACK_DDR VCCA Y2 +1.5VS AL13 VSS VSS U24
80mA AL19 VSS VSS U27

1
+1.05VS 1 AL2 RSVD_NCTF VSS V14
420mA R533 1 R534 2 +VCCSFR_AB_DPL AL23 V16
0_0603_5% VSS VSS
D4 C996 AL29 V18
VCCP 100_0402_5% RSVD_NCTF VSS
0.01U_0402_16V7K 1 1 AL3 V28
2 RSVD_NCTF VSS
B4 1 AL30 V29

2
VCCP C999 C997 C998 RSVD_NCTF VSS
VCCP B3 AL9 VSS VSS W13
@ 1U_0402_6.3V6K 1U_0402_6.3V6K B13 W2
0.1U_0402_10V6K 2 2 VSS VSS
AA19 VCCD_AB_DPL
Please closed U1.Y2 B16 VSS VSS W23
2
B19 VSS VSS W25
B B
B22 VSS VSS W26
Please closed U1.D4 +VCCA_VCCD 1 2 B30 W28
C159 22P_0402_50V8J RSVD_NCTF VSS
V11 VCCD_HMPLL 1 R535 2 +VCC_CRT_DAC B31 RSVD_NCTF VSS W30
RF@ 0_0603_5% B5 VSS VSS W4
1 B9 VSS VSS W5
+VCCSFR_AB_DPL AC31 C1 W6
VCCSFR_AB_DPL +VCC_ALVD C1000 RSVD_NCTF VSS
VCCALVDS V30 C12 VSS VSS W7
W31 +VCC_DLVD 1U_0402_6.3V6K C21 Y28
VCCDLVDS 2 VSS VSS
154mA 60mA C22 VSS VSS Y3
+VCCCK_DDR 1 2 C25 Y4
LVDS

+VCC_CRT_DAC C150 22P_0402_50V8J VSS VSS


T30 C31
EXP\CRT\PLL

VCCACRTDAC +DMI_HMPLL RSVD_NCTF


RF@ 1 R536 2 D22 VSS
+3VS 0_0603_5% E1 RSVD_NCTF
5mA 1 E10 VSS
T31 T1 +VCC_DMI E19
+RING_EAST VCC_GIO VCCA_DMI +0.89VS C1001 VSS
J31 VCCRING_EAST VCCA_DMI T2 480mA E21 VSS
+RING_WEST C3 T3 1U_0402_6.3V6K E25 T29
DMI

VCCRING_WEST VCCA_DMI 2 VSS VSS


305mA B2 VCCRING_WEST 1 2 E8 VSS
C2 P2 T41 C153 22P_0402_50V8J F17
+LGI_VID VCCRING_WEST RSVD +DMI_HMPLL VSS
A21 VCC_LGI VCCSFR_DMIHMPLL AA1 RF@ F19 VSS
104mA 1 R537 2 +VCC_ALVD
VCCP E2 +1.05VS 0_0603_5% 6 OF 6
1 PINEVIEW-M_FCBGA8559

+CPU_CORE C1002
5 OF 6 22U_0805_6.3V6M
2
PINEVIEW-M_FCBGA8559 1 2
C156 22P_0402_50V8J

+0.89VS RF@ R538


1 2 +VCC_DLVD
0_0603_5%
1
A A
0.1U_0402_10V6K

C1003
330U_D2_2.5VY_R9M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0805_10V4Z
2.2U_0603_10V6K

1U_0402_6.3V6K
1 2010.07.12 RF request 2
C1006

C1007

C1008

C1009

C1010

C1011

C1012

2 1 1 1 1 1 1 1 2 1
C1005

C1013

C1014

C1004

1 2 2 2 2 2 2 2 1 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

Close Chipset pin THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 8 of 36
5 4 3 2 1
5 4 3 2 1

+3VM_CK505 2010.03.23 Change R81 from bead to 0 ohm


FSC FSB FSA CPU SRC PCI REF DOT_96 USB R81 250 mA CPU_SSCDREFCLK CPU_SSCDREFCLK#
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz +3VS 1 2
1 1 1 1 1 1
0_0603_5% C126 C127 C128 C129 C133
0 0 0 266 100 33.3 14.318 96.0 48.0 C940 @ C941 @
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 47P_0402_50V8J 33P_0402_50V8K 33P_0402_50V8K
2 2 2 2 2 2
0 0 1 133 100 33.3 14.318 96.0 48.0
+1.05VM_CK505 7/13 For RF request 7/13 Add 33pFfor RF request
R82
0 1 0 200 100 33.3 14.318 96.0 48.0 80 mA 7/21 Reserve 33pFfor RF request
+1.05VS 1 2
FBMH1608HM601-T_0603 1 1 1 1 1 1 +3VS
0 1 1 166 100 33.3 14.318 96.0 48.0 C134 C135 C136 C137 C138 C139 C141
D D
7/13 For RF request 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 47P_0402_50V8J
2 2 2 2 2 2 R83 R84
1 0 0 333 100 33.3 14.318 96.0 48.0
2010.03.23 Change R477 from bead to 0 ohm 2.2K_0402_5% 2.2K_0402_5%
1 0 1 100 100 33.3 14.318 96.0 48.0 +1.5VM_CK505
8/27 Delete C93, C94, C95, C102 for low power CLK GEN Q1A
R477 2N7002DW-T/R7_SOT363-6
1 1 0 400 100 33.3 14.318 96.0 48.0 +1.5VS 1 2 <13> PCH_SMBDATA 6 1 CLK_SMBDATA

10U_0805_10V4Z
0_0603_5% 1
SA00003H610 (ICS :CS9LVRS387AKLFT MLF)

C942
1 1 1 @
Reserved

2
+3VS
Low power CLK Gen.

5
2
7/13 For RF request @
7/21 Delete C296, C297 for RF request
U4 7/13 Add 22pF to gnd and close to U3 for RF request CLK_SMBCLK
Normal Power Low Power RTM875N-397-GR
<13> PCH_SMBCLK 3 4
+3VM_CK505 +3VM_CK505 Q1B 2N7002DW-T/R7_SOT363-6
@ U4
7/21 Reserve 22pF to gnd and close to U3 for RF request
R477 @ Stuff @ R478 9 CLK_SMBDATA
+3VM_1.5VM_R SDA CLK_SMBDATA <10,17>
R478 Stuff @ +1.5VM_CK505
1 2 55 VDD_SRC
10 CLK_SMBCLK SRC PORT LIST
0_0603_5% SCL CLK_SMBCLK <10,17>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R479 Stuff @ @ R483 1 1 1
6 VDD_REF

C943

C944

C945
R480 @ Stuff 1
0_0603_5%
2 12 VDD_PCI CPU_0 71 CLK_CPU_BCLK
CLK_CPU_BCLK <7> PORT DEVICE
CLK_CPU_BCLK#
R483 @ Stuff 2 2 2
72 VDD_CPU CPU_0# 70 CLK_CPU_BCLK# <7>
@
1
R479
2 19 68 CLK_CPU_HPLCLK
SRC0 CPU_DREFCLK
+1.05VM_CK505 VDD_48 CPU_1 CLK_CPU_HPLCLK <7>
0_0603_5% 27 67 CLK_CPU_HPLCLK#
CLK_CPU_HPLCLK# <7>
SRC2 CPU_EXP
VDD_PLL3 CPU_1#
@ R480 +1.05VM_CK505
SRC3
+1.05VS +1.05VM_1.5VM_R CPU_DREFCLK
C +1.5VM_CK505 1 2 66 VDD_CPU_IO SRC_0/DOT_96 24 CPU_DREFCLK <7> SRC4 PCIE_SATA C

47P_0402_50V8J
0.1U_0402_16V4Z
0_0603_5% CPU_DREFCLK#
1 31 VDD_PLL3_IO SRC_0#/DOT_96# 25 CPU_DREFCLK# <7> SRC6 PCIE_WLAN
1

C946

C947
@
R481
470_0402_5%
62 VDD_SRC_IO
28 CPU_SSCDREFCLK
CPU_SSCDREFCLK <7>
SRC7
R482 2 LCDCLK/27M
2.2K_0402_5%
7/13 For RF request 52 VDD_SRC_IO CPU_SSCDREFCLK# SRC8
29 CPU_SSCDREFCLK# <7>
2

FSA 2 LCDCLK#/27M_SS
1 23 VDD_IO SRC9 PCIE_LAN
8/24 Change net name to FSB for U3.2 CLK_CPU_EXP
<7> CPU_BSEL0 1
R86
2 38 VDD_SRC_IO SRC_2 32 CLK_CPU_EXP <6> SRC10 PCIE_PCH
0_0402_5% 7/13 Add 33pF to GND for RF request 10_0402_5% 1 2 R92 CLK_CPU_EXP#
SRC_2# 33 CLK_CPU_EXP# <6> SRC11 PCIE_WWAN
1

<23> CLK_48M_CR
@ R484 7/21 Reserve 33pF to GND for RF request 10_0402_5% 1 2 R91 FSA 20
<12> CLK_PCH_48M USB_0/FS_A
SRC_3 35
1K_0402_5% 8/27 C303, C324, C325, C326, C327 to GND for RF request 1 2 FSB 2
C143 22P_0402_50V8J FS_B/TEST_MODE
36
2

33_0402_5% 1 SRC_3#
2 R93 FSC 7 REF_0/FS_C/TEST_
<13> CLK_PCH_14M
1 2 8 39 CLK_PCIE_SATA
REF_1 SRC_4 CLK_PCIE_SATA <11> +3VS
+3VS R65 1 2 H_STP_CPU# C868 22P_0402_50V8J
10K_0402_5% 40 CLK_PCIE_SATA#
SRC_4# CLK_PCIE_SATA# <11>
VGATE 1
+1.05VS <13,24,35> VGATE CKPWRGD/PD#
7/22 Add R241 pull up to +3VS for RF Intel request 11 57 CLK_PCIE_WLAN WLAN_CLKREQ# R99 2 1 10K_0402_5%
NC SRC_6 CLK_PCIE_WLAN <17>
WWAN_CLKREQ# R100 2 1 10K_0402_5%
1

56 CLK_PCIE_WLAN# LAN_CLKREQ# R101 2 1 10K_0402_5%


SRC_6# CLK_PCIE_WLAN# <17>
R485
470_0402_5% H_STP_CPU# 53
R486 <13> H_STP_CPU# CPU_STOP#
SRC_7 61
1K_0402_5% R427 1 2 @ 0_0402_5% H_STP_PCI#_R 54 CLK_PCIE_PCH 1 2
2

FSB <13> H_STP_PCI# PCI_STOP# @ C1067 56P_0402_50V8


2 1 SRC_7# 60
CLK_PCIE_PCH# 1 2
1 2 CLK_XTAL_IN 5 @ C1066 56P_0402_50V8
<7> CPU_BSEL1 XTAL_IN
B R487 64 B
0_0402_5% CLK_XTAL_OUT SRC_8/CPU_ITP
4 XTAL_OUT
1

R608 1 2 H_STP_PCI#_R 1 2 63
@ R488
+3VS
10K_0402_5% C144 22P_0402_50V8J SRC_8#/CPU_ITP# 2010.07.12 RF request
0_0402_5% 33_0402_5% 1 2 R103 CLK_PCI_DDR_R 13 CLK_PCIE_LAN
<17> CLK_PCI_DDR PCI_1 SRC_9 44 CLK_PCIE_LAN <22>
REQ PORT LIST
2

PCI2_TME 14 45 CLK_PCIE_LAN#
PCI_2 SRC_9# CLK_PCIE_LAN# <22>
1 2
C145 22P_0402_50V8J 15 PCI_3
50 CLK_PCIE_PCH
CLK_PCIE_PCH <12>
PORT DEVICE
+1.05VS 33_0402_5% 1 PCI4_SEL SRC_10
8/14 Add R250 pull up for Intel request <24> CLK_PCI_LPC 2 R107 16 PCI_4/SEL_LCDCL
33_0402_5% 1 2 R108 ITP_EN 17
SRC_10# 51 CLK_PCIE_PCH#
CLK_PCIE_PCH# <12> REQ_3#
<11> CLK_PCI_PCH PCIF_5/ITP_EN
1

R489 7/13 Add 33pF to GND for RF request 1 2 48 CLK_PCIE_WWAN


CLK_PCIE_WWAN <17>
REQ_4#
470_0402_5% C146 22P_0402_50V8J SRC_11
R490 18 47 CLK_PCIE_WWAN#
CLK_PCIE_WWAN# <17>
REQ_6# PEIC_WLAN
10K_0402_5% VSS_PCI SRC_11#
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# REQ_7#
2

FSC 2 1 3 VSS_REF
For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96# REQ_9# PCIE_LAN
<7> CPU_BSEL2 1 2 22 37
R104 Pin28/29 : LCDCLK / LCDCLK# VSS_48 CLKREQ_3#
0_0402_5% 1 = Pin24/25 : SRC_0 / SRC_0# 26 41
REQ_10#
VSS_IO CLKREQ_4#
1

@ R491 Pin28/29 : 27M/27M_SS 69 58 WLAN_CLKREQ#


WLAN_CLKREQ# <17>
REQ_11# PEIC_WWAN
VSS_CPU CLKREQ_6#
For PCI2_TME:0=Overclocking of CPU and SRC allowed REQ_A#
0_0402_5% 30 65
(ICS only) 1=Overclocking of CPU and SRC NOT allowed VSS_PLL3 CLKREQ_7#
2

34 43 LAN_CLKREQ#
VSS_SRC CLKREQ_9# LAN_CLKREQ# <22>
+3VS 59 49
VSS_SRC SLKREQ_10#
7/22 Add R242 to R253 for Intel request WWAN_CLKREQ#
42 VSS_SRC CLKREQ_11# 46 WWAN_CLKREQ# <17>
2

A A
R112 73 21
CLK_XTAL_IN VSS USB_1/CLKREQ_A#
C147 22P_0402_50V8J 10K_0402_5% 7/21 Change WWAN_CLKREQ# from REQ4 to REQ11
1

ICS9LVRS387AKLFT MLF
1

Y1
14.31818MHZ 20PF 7A14300003 ITP_EN PCI4_SEL PCI2_TME
2

CLK_XTAL_OUT
2

C148 22P_0402_50V8J @
R113 R114 R115 Security Classification Compal Secret Data Compal Electronics, Inc.
Routing the trace at least 10mil Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title
10K_0402_5% 10K_0402_5% 10K_0402_5%
SCHEMATIC MB A6851
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2010.03.09 Change Y1 to 5 x3.2 size D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 9 of 36
5 4 3 2 1
5 4 3 2 1

+DIMM_VREF +1.5V +1.5V


3A@1.5V

<6> DDR_A_DQS#[0..7]

<6> DDR_A_D[0..63] JDDR1


+1.5V +DIMM_VREF 1 2
VREF_DQ VSS1 DDR_A_D4
<6> DDR_A_DM[0..7] 3 VSS2 DQ4 4
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5
<6> DDR_A_DQS[0..7] Layout Note: 7 DQ1 VSS3 8

0.1U_0402_16V4Z
9 10 DDR_A_DQS#0
Place near JDDR1 DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS0
<6> DDR_A_MA[0..14] 1 11 DM0 DQS0 12

1
C117

1K_0402_1%
13 VSS5 VSS6 14
DDR_A_D2 15 16 DDR_A_D6
DQ2 DQ6

R74
DDR_A_D3 17 18 DDR_A_D7
2 DQ3 DQ7
D R879 19 VSS7 VSS8 20 D
DDR_A_D8 21 22 DDR_A_D12

2
DDR_A_D9 DQ8 DQ12 DDR_A_D13
1 2 +DIMM_VREF 23 DQ9 DQ13 24
0_0402_5% 25 26
VSS9 VSS10

1
1K_0402_1%
DDR_A_DQS#1 27 28 DDR_A_DM1
+1.5V DDR_A_DQS1 DQS#1 DM1 DRAMRST#
29 DQS1 RESET# 30 DRAMRST# <6>

R75
31 VSS11 VSS12 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36

2
DQ11 DQ15
2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K
37 VSS13 VSS14 38
2 2 2 2 2 2 DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
C99

C100

C101

C102

C103

C116
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
1 1 1 1 1 1 DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
+DIMM_VREF 49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
0.1U_0402_16V4Z
20mils DDR_A_D19
51 DQ18 DQ23 52
53 DQ19 VSS19 54
55 56 DDR_A_D28
DDR_A_D24 VSS20 DQ28 DDR_A_D29
1 1 1 57 DQ24 DQ29 58
220U_B2_2.5VM_R35

C115 C104 C105 DDR_A_D25 59 60


DQ25 VSS21
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 61 62 DDR_A_DQS#3
2.2U_0603_6.3V6K DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
1 1 1 1 1 1 63 DM3 DQS3 64
+ 2 2 2
C106

65 VSS23 VSS24 66
C107

C108

C109

C110

CZ03

CZ04
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
2 2 2 2 2 2 @ 2 0.1U_0402_16V4Z 71 VSS25 VSS26 72

@ +1.5V
<6> DDR_CKE0 DDR_CKE0 73 74 DDR_CKE1
CKE0 CKE1 DDR_CKE1 <6>
75 VDD1 VDD2 76
2010.03.27 Add CZ03,CZ04 for ESD 77 NC1 A15 78
<6> DDR_A_BS2 DDR_A_BS2 79 80 DDR_A_MA14
C BA2 A14

0.1U_0402_16V4Z
C
81 VDD3 VDD4 82

1
1K_0402_1%
1 DDR_A_MA12 83 84 DDR_A_MA11
A12/BC# A11

C118

R77
DDR_A_MA9 85 86 DDR_A_MA7
+V_DDR_CPU_REF A9 A7
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
2 DDR_A_MA5 A8 A6 DDR_A_MA4
Layout Note: 91 92

2
A5 A4
93 VDD7 VDD8 94
Place one cap close to every 2 pullup DDR_A_MA3 95 96 DDR_A_MA2
A3 A2

1
1K_0402_1%
resistors terminated to +0.75VS DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
99 VDD9 VDD10 100

R76
<6> M_CLK_DDR0 M_CLK_DDR0 101 102 M_CLK_DDR1
CK0 CK1 M_CLK_DDR1 <6>
<6> M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 <6>
105 106

2
DDR_A_MA10 VDD11 VDD12 DDR_A_BS1
107 A10/AP BA1 108 DDR_A_BS1 <6>
<6> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
BA0 RAS# DDR_A_RAS# <6>
111 VDD13 VDD14 112
<6> DDR_A_WE# DDR_A_WE# 113 114 DDR_CS0_DIMMA#
WE# S0# DDR_CS0# <6>
+0.75VS <6> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <6>
117 VDD15 VDD16 118
DDR_A_MA13 M_ODT1 +V_DDR_CPU_REF
119 A13 ODT1 120 M_ODT1 <6>+VREF_CA
<6> DDR_CS1# DDR_CS1_DIMMA# 121 122
S1# NC2
123 VDD17 VDD18 124
125 126 +VREF_CA 1 2
NCTEST VREF_CA R877 0_0402_5%
127 VSS27 VSS28 128

2.2U_0402_6.3V6M
0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_A_D32 129 130 DDR_A_D36 1 1 1
DQ32 DQ36
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1 1 DDR_A_D33 131 132 DDR_A_D37


DQ33 DQ37

C213

C215

C214
133 VSS29 VSS30 134
C111

C112

C113

C114

DDR_A_DQS#4 135 136 DDR_A_DM4


DDR_A_DQS4 DQS#4 DM4 2 @ 2 2
137 DQS4 VSS31 138
2 2 2 2 DDR_A_D38
139 VSS32 DQ38 140
DDR_A_D34 141 142 DDR_A_D39
DDR_A_D35 DQ34 DQ39
143 DQ35 VSS33 144
145 146 DDR_A_D44
B DDR_A_D40 VSS34 DQ44 DDR_A_D45 B
147 DQ40 DQ45 148
DDR_A_D41 149 150
DQ41 VSS35 DDR_A_DQS#5
151 VSS36 DQS#5 152
DDR_A_DM5 153 154 DDR_A_DQS5
DM5 DQS5
155 VSS37 VSS38 156
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170 DDR_A_DM6
DDR_A_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_A_D54
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178
DQ51 VSS45 DDR_A_D60
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 DM7 DQS7 188
189 VSS49 VSS50 190
DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
1 R207 2 195 VSS51 VSS52 196
10K_0402_5% 197 198 PM_EXTTS#0
SA0 EVENT# PM_EXTTS#0 <7>
199 200 CLK_SMBDATA
+3VS VDDSPD SDA CLK_SMBDATA <9,17>
2.2U_0402_6.3V6M

0.1U_0402_16V4Z

201 202 CLK_SMBCLK


SA1 SCL CLK_SMBCLK <9,17>
1 1 1 203 VTT1 VTT2 204 +0.75VS

10K_0402_5%
C219

C220

R208 205 206 0.65A@0.75V


G1 G2
2 @ 2 FOX_AS0A621-U4SG-7H
A +0.75VS A
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401986
Date: Friday, September 02, 2011 Sheet 10 of 36
5 4 3 2 1
5 4 3 2 1

+3VS

U15A TGP
R539 1 2 8.2K_0402_5% RSVD01
A5 PAR AD0 B22
R540 1 2 8.2K_0402_5% RSVD02 PCI_DEVSEL# B15 D18
CLK_PCI_PCH DEVSEL# AD1
<9> CLK_PCI_PCH J12 PCICLK AD2 C17
PCI_RST# A23 C18
<24> PCI_RST# PCIRST# AD3
PCI_IRDY# B7 B17
+3VS IRDY# AD4
C22 PME# AD5 C19

1
100K_0402_5%
RP7 PCI_SERR# B11 B18 PCI_RST#
PCI_PIRQB# R541 PCI_STOP# SERR# AD6
D 1 8 F14 STOP# AD7 B19 D
2 7 PCI_PIRQF# PCI_PLOCK# A8 D16
PCI_PIRQC# PCI_TRDY# PLOCK# AD8 CLK_PCI_PCH
3 6 A10 TRDY# AD9 D15
PCI_PIRQA# PCI_PERR#

0.1U_0402_16V4Z
4 5 D10 A13

2
PERR# AD10

1
PCI_FRAME# A16 E14 1
8.2K_0804_8P4R_5% FRAME# AD11 R542 @
AD12 H14

C1015
For EC request. L14 @ 10_0402_5%
+3VS AD13
AD14 J14
RP8 2
A18 E10 1

2
PCI_PIRQE# GNT1# AD15 @
1 8 E16 GNT2# AD16 C11
2 7 PCI_PLOCK# E12 C1016
PCI_PIRQG# REQ1# AD17 8.2P_0402_50V8D
3 6 G16 B9
4 5 PCI_IRDY# REQ2# A20
REQ1# PCI AD18
B13
2
REQ2# AD19
AD20 L12
8.2K_0804_8P4R_5% B8
AD21
G14 GPIO48/STRAP1# AD22 A3
+3VS A2 B5
RP16 GPIO22 GPIO17/STRAP2# AD23
C15 GPIO22 AD24 A6
1 8 PCI_SERR# GPIO1 C9 G12
PCI_PERR# GPIO1 AD25
2 7 AD26 H12
3 6 PCI_TRDY# R543 R544 C8 For EMI, close to TigerPoint
GPIO1 10K_0402_5% 10K_0402_5% AD27
4 5 AD28 D9
@ @ PCI_PIRQA# B2 C7
8.2K_0804_8P4R_5% PCI_PIRQB# PIRQA# AD29
D7 PIRQB# AD30 C1
+3VS PCI_PIRQC# B3 B1
RP10 PCI_PIRQD# PIRQC# AD31
H10 PIRQD#
1 8 GPIO22 PCI_PIRQE# E8
PCI_DEVSEL# PCI_PIRQF# PIRQE#/GPIO2
2 7 D6 PIRQF#/GPIO3
3 6 PCI_PIRQD# PCI_PIRQG# H8 H16
C PCI_PIRQH# PCI_PIRQH# PIRQG#/GPIO4 C/BE0# C
4 5 F8 PIRQH#/GPIO5 C/BE1# M15
C/BE2# C13
8.2K_0804_8P4R_5% D11 L16
RSVD01 STRAP0# C/BE3#
K9 RSVD01
RSVD02 M13 RSVD02
+3VS 2 1
RP11 R545
1 8 REQ2# @ 1K_0402_5% +1.05VS
TIGERPOINT_ES1_BGA360
2 7 REQ1#
PCI_STOP# U15C TGP
3 6
1

4 5 PCI_FRAME#
R12 AE6 SATA_IRX_C_DTX_N0 <19> R546
8.2K_0804_8P4R_5% RSVD03 SATA0RXN 56_0402_5%
AE20 RSVD04 SATA0RXP AD6 SATA_IRX_C_DTX_P0 <19>
AD17 RSVD05 SATA0TXN AC7 SATA_ITX_DRX_N0 <19>
AC15 RSVD06 SATA0TXP AD7 SATA_ITX_DRX_P0 <19>
AD18 AE8 T63 PAD H_FERR#
RSVD07 SATA1RXN
Y12 RSVD08 SATA1RXP AD8 T64 PAD
AA10 RSVD09 SATA1TXN AD9 T65 PAD R111 closed TigerPoint within 1"
AA12 RSVD10 SATA1TXP AC9 T66 PAD
Y10 RSVD11
AD15 RSVD12

SATA
W10 RSVD13
V12 RSVD14
AE21 RSVD15
AE18 RSVD16
AD19 RSVD17
U12 RSVD18
SATA_CLKN AD4 CLK_PCIE_SATA# <9> Please closed Tiger point
AC17 AC4 CLK_PCIE_SATA <9> +3VS
B
AB13
RSVD19 SATA_CLKP PIN within 500 mils B
RSVD20
AC13 RSVD21 SATARBIAS# AD11 SATARBIAS R547 24.9_0402_1%
AB15 RSVD22 SATARBIAS AC11 R548
Y14 RSVD23 SATALED# AD25 SATALED# <26>
SATALED#
AB16 RSVD24 10K_0402_5%
AE24 RSVD25
AE23 R549
RSVD26 GATEA20
10K_0402_5%
AA14 U16 GATEA20 GATEA20 <24> R550
RSVD27 A20GATE H_A20M# SERIRQ
V14 RSVD28 A20M# Y20 H_A20M# <7> 1 2
CPUSLP# Y21
Y18 H_IGNNE# 8.2K_0402_5%
IGNNE# H_IGNNE# <7>
AD16 AD21 +1.05VS
RSVD29 INIT3_3V# H_INIT#
AB11 RSVD30 INIT# AC25 H_INIT# <7>
+3VS AB10 AB24 H_INTR
RSVD31 INTR H_INTR <7>
HOST

1
R551 Y22 H_FERR#
FERR# H_FERR# <7>
1 2 AD23 T17 H_NMI R552 R110 to be within 1" from the Tiger
GPIO36 NMI H_NMI <7>
AC21 EC_KBRST# EC_KBRST# <24>
8.2K_0402_5% RCIN#
AA16 SERIRQ SERIRQ <24> 56_0402_5% Point chipset.
SERIRQ H_SMI#
SMI# AA21 H_SMI# <7>

2
V18 H_STPCLK#
STPCLK# H_STPCLK# <7>
THRMTRIP# AA20 H_THERMTRIP# <7>

3
A A
TIGERPOINT_ES1_BGA360

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 11 of 36
5 4 3 2 1
5 4 3 2 1

D D
USB PORT LIST

PORT #EVT DEVICE


TGP
U15B
USB0 USB1(Left)
<6> DMI_TXN0 R23
R24
DMI0RXN USBP0N H7
H6
USB20_N0
USB20_P0
USB20_N0 <18> USB1(Right) USB1 USB2(Left)
<6> DMI_TXP0 DMI0RXP USBP0P USB20_P0 <18>
<6> DMI_RXN0 P21
P20
DMI0TXN USBP1N H3
H2
USB20_N1
USB20_P1
USB20_N1 <18> USB2(Right) USB2 NC
<6> DMI_RXP0 DMI0TXP USBP1P USB20_P1 <18>
<6> DMI_TXN1 T21
T20
DMI1RXN USBP2N J2
J3
T49 PAD USB3 Card-reader
<6> DMI_TXP1 DMI1RXP USBP2P T50 PAD
<6> DMI_RXN1 T24
T25
DMI1TXN USBP3N K6
K5
USB20_N3 <23> Card-reader USB4 USB3(Right)
<6> DMI_RXP1 DMI1TXP USBP3P USB20_P3 <23>

DMI
PAD T51 T19 DMI2RXN USBP4N K1 USB20_N4
USB20_P4
USB20_N4 <18> USB5 WWAN
PAD T52 T18 DMI2RXP USBP4P K2
USB20_N5_L
USB20_P4 <18> USB3(Left) USB6
PAD T53 U23
U24
DMI2TXN USBP5N L2
L3 USB20_P5_L WLAN + BT
PAD T54 DMI2TXP USBP5P USB20_N6 WWAN USB7
V21
V20
DMI3RXN USBP6N M6
M5 USB20_P6
USB20_N6 <17> CMOS
PAD T57 V24
DMI3RXP USBP6P
N1 USB20_N7
USB20_P6 <17> WLAN + BT (Combo) #6/27 EVT
DMI3TXN USBP7N USB20_N7 <16>
USB20_P7
PAD T58 V23 DMI3TXP USBP7P N2 USB20_P7 <16> CMOS
D4 USB_OC#0_1_PCH
OC0# USB_OC#0_1_PCH <18>
USB_OC#0_1_PCH

USB
PAD T59 K21 PERN1 OC1# C5
PAD T60 K22 D3 USB_OC#2
PERP1 OC2# USB_OC#3
PAD T61 J23 PETN1 OC3# D2 #DVT USB_OC# control by EC PCH reserve
PAD T62 J24 E5 USB_OC#4_PCH
C PETP1 OC4# USB_OC#4_PCH <18> C
PCIE_PTX_C_IRX_N2 M18 E6 SLP_CHG_M3_PCH
<17> PCIE_PTX_C_IRX_N2 PERN2 OC5#/GPIO29 SLP_CHG_M3_PCH <18> +3VALW
WLAN+BT Combo PCIE_PTX_C_IRX_P2 M19 C2 SLP_CHG_M4_PCH
<17> PCIE_PTX_C_IRX_P2 PERP2 OC6#/GPIO30 SLP_CHG_M4_PCH <18>
<17> PCIE_ITX_C_PRX_N2 C1017 2 1 0.1U_0402_10V6K PCIE_ITX_PRX_N2 K24 C3 USB_OC#7 RP12
C1018 2 PCIE_ITX_PRX_P2 PETN2 OC7#/GPIO31 USB_OC#0_1_PCH 4
<17> PCIE_ITX_C_PRX_P2 1 0.1U_0402_10V6K K25 PETP2 #EVT 6/27 support sleep charge function 5
PCIE_PTX_C_IRX_N3 L23 SLP_CHG_M4_PCH 3 6
<22> PCIE_PTX_C_IRX_N3 PERN3

PCI-E
PCIE_PTX_C_IRX_P3 L24 USB_OC#7 2 7
<22> PCIE_PTX_C_IRX_P3 PERP3
LAN <22> PCIE_ITX_C_PRX_N3 C1019 2 1 0.1U_0402_10V6K PCIE_ITX_PRX_N3 L22 G2 1 8
C1020 2 PETN3 USBRBIAS
<22> PCIE_ITX_C_PRX_P3 1 0.1U_0402_10V6K PCIE_ITX_PRX_P3 M21 PETP3 USBRBIAS# G3 R553 10K_0804_8P4R_5%
PCIE_PTX_C_IRX_N4 P17 22.6_0402_1% Please closed Tiger point
<17> PCIE_PTX_C_IRX_N4 PERN4
PCIE_PTX_C_IRX_P4 P18 RP13
<17> PCIE_PTX_C_IRX_P4 PERP4 PIN within 200 mils
WWLAN <17> PCIE_ITX_C_PRX_N4 C1021 2 1@ 0.1U_0402_10V6K PCIE_ITX_PRX_N4 N25 USB_OC#3 4 5
C1022 2 PETN4
<17> PCIE_ITX_C_PRX_P4 1@ 0.1U_0402_10V6K PCIE_ITX_PRX_P4 N24 PETP4
USB_OC#2 3 6
F4 CLK_PCH_48M USB_OC#4_PCH 2 7
CLK48 CLK_PCH_48M <9>
SLP_CHG_M3_PCH 1 8
10K_0804_8P4R_5%

1
Please closed Tiger point 33_0402_5%

@ C225 PIN within 500 mils @ # DVT For RF need stuff


PCIE_ITX_PRX_N21 2 R554
+1.5VS

2
12P_0402_50V8J R555 24.9_0402_1% 1
1 2 H24 @
@ C226 DMI_ZCOMP C1023
J22 DMI_IRCOMP 1 2
PCIE_ITX_PRX_P21 2 22P_0402_50V8J R3 0_0402_5%
2 RF@ L2
<9> CLK_PCIE_PCH# W23 DMI_CLKN
12P_0402_50V8J W24 For EMI, Close to TigerPoint USB20_N5_L 1 1 2 USB20_N5
<9> CLK_PCIE_PCH DMI_CLKP 2 USB20_N5 <17>
2

TIGERPOINT_ES1_BGA360 USB20_P5_L 4 3 USB20_P5


4 3 USB20_P5 <17>
WCM-2012-900T_0805
1 2
B R4 0_0402_5% B
# PVT C225, C226 add
12p to GND for RF 2010.07.12 RF request

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401986 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 02, 2011 Sheet 12 of 36
5 4 3 2 1
5 4 3 2 1

+3VALW

2.2K_0402_5% 1 R560 2 PCH_SMBCLK


7/2 For EMI, Close to TigerPoint
2.2K_0402_5% 1 R561 2 PCH_SMBDATA
9/1 C207 change to SE071100J80 for EMI request
+3VALW
HDA_BITCLK
+3VALW

1
D @ D

2 PM_CLKRUN# 1 2 R610
R598 10K_0402_5% 10K_0402_5%
10K_0402_5% 2 R562 1 SYS_RST# C1024
10P_0402_50V8J EVT# For EC request 7/5

2
1 BOARD_ID

1
8.2K_0402_5% R563 ICH_RI# @
R611
10K_0402_5% 2 R564 1 EC_SWI# U15D TGP
10K_0402_5%
10K_0402_5% 2 R565 1 SLP_CHG# AA5 T15 GPIO0

2
LDRQ1#/GPIO23 BMBUSY#/GPIO0 GPIO6
<24> LPC_AD0 V6 LAD0/FWH0 GPIO6 W16

LPC
AA6 W14 SLPIOVR
<24> LPC_AD1 LAD1/FWH1 GPIO7
12/17 Add Pull high Resistor for GPIO14 Y5 K18 EC_SMI#
<24> LPC_AD2 LAD2/FWH2 GPIO8 EC_SMI# <24>
W8 H19 EC_SCI#
<24> LPC_AD3 LAD3/FWH3 GPIO9 EC_SCI# <24>
9/1 R125 change to SM010027780 for EMI request Y8 M17 PCH_ACIN
+3VALW LDRQ0# GPIO10 GPIO12
<24> LPC_FRAME# Y4 LFRAME#/FWH4 GPIO12 A24
C23 EC_LID_OUT#
R582 GPIO13 EC_LID_OUT# <24>
33_0402_5%
1 2 BITCLK_PCH P6 P5 SLP_CHG#
<20> HDA_BITCLK R567 HDA_BIT_CLK GPIO14 SLP_CHG# <18>
33_0402_5%
1 2 RST#_PCH U2 E24 GPIO15
<20> HDA_RST# HDA_RST# GPIO15

AUDIO
<20> HDA_SDIN0 W2 HDA_SDIN0 DPRSLPVR AB20 PM_DPRSLPVR <7>
V2 HDA_SDIN1 STP_PCI# Y16 H_STP_PCI# <9>
P8 HDA_SDIN2 STP_CPU# AB19 H_STP_CPU# <9>
33_0402_5%
1 R568 2 SDOUT_PCHAA1 R3
<20> HDA_SDOUT HDA_SDOUT GPIO24
RP14 33_0402_5%
1 R569 2 SYNC_PCH Y1 C24 R570 1 2 1K_0402_5%
<20> HDA_SYNC HDA_SYNC GPIO25
5 4 LINKALERT# <9> CLK_PCH_14M AA3 CLK14 GPIO26 D19 BOARD_ID

1
6 3 GPIO11 GPIO27 D20 12/31 Add HW Board ID function
7 2 SMLINK0 R571 U3 EE_CS GPIO28 F22
8 1 SMLINK1 # MP C1026 4.7P change to AE2 EE_DIN CLKRUN# AC19 PM_CLKRUN# 2010.04.22 Add C1064 for ESD solution PLTRST#
10_0402_5% T6 U14
10K_0804_8P4R_5% 10p for RF request RF@ V3
EE_DOUT EPROM GPIO33
AC1

2
C C1025 EE_SHCLK GPIO34 C
GPIO38 AC23

2
18P_0402_50V8J 1 T4 AC24 1
LAN_CLK GPIO39 BT_PWR# <17>
2 1 RTCX1 RF@ P7 R573
C1026 LANR_RSTSYNC H_PWRGD C1064 100K_0402_5%
B23 LAN_RST# CPUPWRGD/GPIO49 AB22 H_PWRGD <7>

10M_0402_5%
+3VALW Y2 AA2 0.1U_0402_16V4Z

LAN

MISC
LAN_RXD0

1
RP15 32.768KHZ_12.5PF_Q13MC14610002 2 10P_0402_50V8J EC_THERM# 2
AD1 AB17 EC_THERM# <24>

1
R572 LAN_RXD1 THRM#
1 8 GPIO15 2 NC OSC 1 AC2 LAN_RXD2 VRMPWRGD V16 VGATE
2 7PCH_LOW_BAT# W3 LAN_TXD0 MCH_SYNC# AC18 MCH_SYNC#
3 6 GPIO12 3 NC OSC 4 T7 LAN_TXD1 PWRBTN# E21 PBTN_OUT#
PBTN_OUT# <24>
4 5 EC_LID_OUT# U4 H23 ICH_RI#
2

C1027 LAN_TXD2 RI# T42


SUS_STAT#/LPCPD# G22 7/20 Add test point
8.2K_0804_8P4R_5% 18P_0402_50V8J EC_CLK
W4 D22 EC_CLK <24> 01/11 Reserve EC_CLK for KBC

RTC
RTCX2 RTCX1 SUSCLK SYS_RST#
2 1 V5 RTCX2 SYS_RESET# G18
RTCRST# T5 G23 PLTRST#
RTCRST# PLTRST# PLTRST# <7,17,22>
C25 EC_SWI#
WAKE# EC_SWI# <24>
GPIO11 E20 T8 INTRUDER#
PCH_SMBCLK SMBALERT#/GPIO11 INTRUDER# PCH_POK
<9> PCH_SMBCLK H18 SMBCLK PWROK U10 8/24 Add R254 pull down for EC request

SMB
+RTCVCC R574 1 2 <9> PCH_SMBDATA PCH_SMBDATA E23 AC3 PCH_RSMRST#
20K_0402_5% LINKALERT# SMBDATA RSMRST# INTVRMEN
H21 LINKALERT# INTVRMEN AD3
SMLINK0 F25 J16 PCH_SPKR +3VALW
+RTCVCC J1 SMLINK0 SPKR PCH_SPKR <20>
@ SMLINK1 F24 SMLINK1
1 1 2 2 SLP_S3# H20 PM_SLP_S3# <24>

2
1M_0402_5% 1 R575 INTRUDER#
2 R2 SPI_MISO SLP_S4# E25 PM_SLP_S4# <6,24>
T1 F21 R578
JUMP_43X39 SPI_MOSI SLP_S5# PM_SLP_S5# <24>
1 R576

SPI
332K_0402_1% 2 INTVRMEN M8 330K_0402_5%
C1028 SPI_CS# PCH_LOW_BAT#
P9 SPI_CLK BATLOW# B25
1U_0402_6.3V4Z R4 AB23 H_DPRSTP#
H_DPRSTP# <7>

1
SPI_ARB DPRSTP# H_DPSLP# D44
1 2 DPSLP# AA18 H_DPSLP# <7>
F20 PCH_ACIN 2 1
+3VS RSVD31 ACIN <24,30>

CH751H-40PT_SOD323-2
B 8.2K_0402_5% R577
7/20 Add SLPIOVR pull up 8.2k to +3vs B
SLPIOVR TIGERPOINT_ES1_BGA360

8.2K_0402_5%
9/23 Change RP17 to R256, R257, R258 for layout request
@R579 PM_CLKRUN#
D45
8.2K_0402_5% R580 GPIO0 PCH_POK 2 1 PCH_RSMRST#
8.2K_0402_5% R581 GPIO6
CH751H-40PT_SOD323-2
PCH_POK 1 2 D46
+3VS R583 10K_0402_5% 1 2
<29,31> POK
EC_PWROK 1 2
R584 10K_0402_5% CH751H-40PT_SOD323-2

1K_0402_5% 1 R585 2 MCH_SYNC#


1 2
R586 0_0402_5%
+3VS R587 2 1 0_0402_5%

PCH_RSMRST# 1 3

C
EC_RSMRST# <24>
1 1 2 @ Q36

E
@ R588 MMBT3906_SOT23-3
C1030 10K_0402_5%

B
2
0.1U_0402_16V4Z 1 2 +3VALW
2 @ R589

1
4.7K_0402_5%
5

+RTCBATT @ U5 @ D7B @D7A


@ D7A
1 BAV99DW-7_SOT363 BAV99DW-7_SOT363
P

<24> EC_PWROK B
Y 4 PCH_POK <7>
+RTCVCC +RTCBATT_R 2
<9,24,35> VGATE A
G

JRTC

6
1 3 TC7SH08FUF_SSOP5 2 1
D6 RSMRST# circuit
3

A 1 GND R126 @ R590


@R590 A
2 2 GND 4
2 1 2 +RTCBATT 2.2K_0402_5%
ACES_85205-0200N 1 1K_0402_5%
CONN@ 3 2010.03.22 Un-stuff RSMRST# circuit and use 0 ohm bypass
+3VL
1 2010.03.22 Un-stuff U5 and C1030
C1029
1U_0402_6.3V6K DAN202U_SC70

2 Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401986 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 02, 2011 Sheet 13 of 36
5 4 3 2 1
5 4 3 2 1

D U15F TGP D
TGP
+5VS +3VS U15E A1
VSS01
VSS02 A25
F12 +V5REF_RUN B6
VCC5REF VSS03
1

VSS04 B10
R591 D8 B16
VSS05
VSS06 B20
100_0402_5% RB751V-40TE17_SOD323-2 F5 +V5REF_SUS B24
VCC5REF_SUS VSS07
E18
2

+SATAPLL VSS08
VCCSATAPLL Y6 VSS09 F16
+V5REF_RUN 2mA G4
VSS10
1 6mA VCCRTC AE3 +RTCVCC VSS11 G8
C1031

0.01U_0402_16V7K
H1

0.1U_0402_10V6K
1U_0402_6.3V6K +DMIPLL VSS12
VCCDMIPLL Y25 1 1 VSS13 H4

C1033
VSS14 H5
2

C1032
VCCUSBPLL F6 VSS15 K4
1432mA R592 K8
+VCC1_5 1 2 2 VSS16
2 +1.5VS VSS17 K11

1U_0402_6.3V6K

1U_0402_6.3V6K
0.1U_0402_10V6K

0.1U_0402_10V6K

10U_0805_10V4Z
VSS18 K19
W18 0_0603_5% K20
V_CPU_IO VSS19
14mA 2 2 1 1 1 L4

C1034

C1035
+5VALW +3VALW VSS20

C1036

C1037

C1038
VSS21 M7
VSS22 M11
VCC1_5_1 AA8 VSS23 N3
1

D47 1 1 2 2 2
VCC1_5_2 M9 VSS24 N12
R593 M20 N13
VCC1_5_3 VSS25

POWER
VCC1_5_4 N22 VSS26 N14
10_0402_5% RB751V-40TE17_SOD323-2 N23
R594 VSS27
P11
2

C +V5REF_SUS +VCC1_05 1 VSS28 C


2 +1.05VS VSS29 P13

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0805_10V4Z
P19
10mA 955mA 0_0603_5% VSS30
R14
C1039 1 1 1 1 VSS31

C1040

C1041

C1042
VCC1_05_1 J10 VSS32 R22
VCC1_05_2 K17 VSS33 T2
0.1U_0402_10V6K P15 T22
2 VCC1_05_3 2 2 2 VSS34
VCC1_05_4 V10 VSS35 V1
VSS36 V7
VSS37 V8
VSS38 V19
216mA R596 V22
+VCC33 VSS39
VCC3_3_1 H25 1 2 +3VS VSS40 V25

0.1U_0402_10V6K

0.1U_0402_10V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VCC3_3_2 AD13 VSS41 W12
F10 1 1 1 1 1 1 1 0_0603_5% W22

C1043

C1044
VCC3_3_3 VSS42

C1045

C1046

C1047

C1048

C1049
G10 @ @ Y2
VCC3_3_4 VSS43
VCC3_3_5 R10 VSS44 Y24
VCC3_3_6 T9 VSS45 AB4
2 2 2 2 2 2 2
VSS46 AB6
VSS47 AB7
VCCSUS3_3_1 F18 VSS48 AB8
VCCSUS3_3_2 N4 VSS49 AC8
K7 R599 AD2
VCCSUS3_3_3 +VCCSUS33 VSS50
VCCSUS3_3_4 F1 1 2 +3VALW VSS51 AD10

0.1U_0402_10V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0805_6.3V4Z
VSS52 AD20
92mA 0_0603_5% AD24
VSS53
1 1 1 1 VSS54 AE1

C1051

C1052

C1053

C1054
@ AE10
VSS55
VSS56 AE25
2 2 2 2
5
B B

TIGERPOINT_ES1_BGA360

VSS57 G24
Place closely pin Y25 within 100mlis. VSS58 AE13
VSS59 F2
+1.5VS
+1.5VS
R601
1 2 RSVD32 AE16
1 2 +DMIPLL RF@C1068
RF@C1068 2200P_0402_50V7K
+3VS
0.01U_0402_16V7K

4.7U_0603_6.3V6K

24mA 1 2
0_0603_5% 1 1 RF@C207
RF@ C207 68P_0402_50V8J
1 2
C1055

C1056

@ RF@C1069
RF@ C1069 2200P_0402_50V7K TIGERPOINT_ES1_BGA360
+3VALW 1 2
2 2 RF@C208
RF@ C208 68P_0402_50V8J
1 2
RF@C1070
RF@ C1070 2200P_0402_50V7K
+1.05VS 1 2
RF@C209
RF@ C209 68P_0402_50V8J
Place closely pin Y6 within 100mlis. RF@C1071
RF@ C1071
1 2
2200P_0402_50V7K
1 2
+1.5VS RF@ C210 68P_0402_50V8J
R602
1 2
1 2 +SATAPLL RF@C1072
RF@ C1072 0.1U_0402_10V6K
10U_0805_10V4Z

0.1U_0402_10V6K

45mA
0_0603_5% 1 2
C1057

C1058

A 2010.07.12 RF request A

2 1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401986 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 02, 2011 Sheet 14 of 36
5 4 3 2 1
A B C D E

Place closed to conn.


CRT CONNECTOR

1
D2 D3 D4

DAN217_SC59

DAN217_SC59

DAN217_SC59
2/16 DVT: Mount C504 for EMI request
+3VS

3
@ @ @
3/16 PVT: Change to high speed bead
1 1 1
C504

Place closed to conn. 0.1U_0402_16V4Z


2
L6
GMCH_CRT_R 1 2 CRT_R_L
<7> GMCH_CRT_R
NBQ100505T-800Y_0402
L7
GMCH_CRT_G 1 2 CRT_G_L
<7> GMCH_CRT_G
NBQ100505T-800Y_0402
L8
GMCH_CRT_B 1 2 CRT_B_L
<7> GMCH_CRT_B
NBQ100505T-800Y_0402

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
1

1
150_0402_1%

150_0402_1%

150_0402_1%
1 1 1 1 1 1
R145 R146 R147 C190 C191 C192 C193 C194 C195

2 2 2 2 2 2

2
2 2
+CRT_VCC

1 2 1 2
C196 0.1U_0402_16V4Z R148 10K_0402_5%
5

1
P U13
OE# CRT_HSYNC_1 R149 1
<7> GMCH_CRT_HSYNC 2 A Y 4 2 39_0402_5% HSYNC
G

SN74AHCT1G125DCKR_SC70-5 CRT_VSYNC_1 R150 1 2 39_0402_5% VSYNC


3

33P_0402_50V8K

33P_0402_50V8K
+CRT_VCC
1 1
1 2
C197 0.1U_0402_16V4Z C198 C199
5

1
U14
2 2
P

OE#

<7> GMCH_CRT_VSYNC 2 A Y 4
G

SN74AHCT1G125DCKR_SC70-5 3/29 PVT:Change F1 from SC04301P000 to SP04301P120.


3

If=1A
+5VS
D5 +CRT_VCC_R +CRT_VCC
2 F1 30mil
1 1 2
3 RB491D_SOT23-3 1.1A_6V_MINISMDC110F-2 1
3 3
C200
+3VS +CRT_VCC 0.1U_0402_16V4Z
2

+3VS
1

+CRT_VCC
1

R151 R152 JCRT


R153 R154 6
4.7K_0402_5% 4.7K_0402_5% RGND
PAD T55 11 ID0
4.7K_0402_5% 4.7K_0402_5% CRT_R_L 1
2

Red
7
2

GGND
5

CRT_DDC_DAT 12
Q3B CRT_G_L SDA
2 Green
4 3 CRT_DDC_DAT 8
<7> GMCH_CRT_DATA HSYNC BGND
13 Hsync
2N7002DW-T/R7_SOT363-6 CRT_B_L 3 Blue
2

9 +5V
VSYNC 14
CRT_DDC_CLK Vsync
<7> GMCH_CRT_CLK 1 6 PAD T56 4 res
Q3A 10
2N7002DW-T/R7_SOT363-6 CRT_DDC_CLK SGND
1 1 15 SCL
5 GND
C201 C202
470P_0402_50V8J 470P_0402_50V8J 16
@ 2 2 @ GND
17 GND
SUYIN_070546FR015S263ZR
4 4
@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 15 of 36
A B C D E
5 4 3 2 1

LCD POWER CIRCUIT

D D
+LCDVDD
1/22 DVT:Change R117 from 47K to 100K
+3VS W=40mils

1
R116 +3VS
150_0603_5%
1

1
C149

2
1 @
R117 C183 4.7U_0805_10V4Z

3
100K_0402_5% 2
Q2B 0.1U_0402_16V7K 2A

3
2
S
G
2N7002DW-T/R7_SOT363-6 5 2 1 2
R141 47K_0402_5% 1/22 DVT:Change Q11 from SI2301BDS to A03413
D Q11

1
1 AO3413_SOT23
# MP Add C227~C232 for RF request C498
+LCDVDD

6
0.01U_0402_25V7K W=40mils
@ C227 2
1 2 LCD_TXOUT0- Q2A
<7> GMCH_ENVDD 2 1 1

1
12P_0201_50V8J 2N7002DW-T/R7_SOT363-6 C186 C187 +3VS
@ C228 @

1
1 2 LCD_TXOUT0+ R142 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2

2.2K_0402_5%

2.2K_0402_5%
C 12P_0201_50V8J 100K_0402_5% C

2
@ C229

R143

R144
1 2 LCD_TXOUT1-
1/22 DVT:Add C498 with 0.01uF
12P_0201_50V8J
@ C230

1
1 2 LCD_TXOUT1+
LCD_EDID_CLK LCD_EDID_CLK <7>
12P_0201_50V8J
@ C231 LCD_EDID_DATA
1 2 LCD_TXOUT2- LED/PANEL BD. Conn. LCD_EDID_DATA <7>

12P_0201_50V8J
@ C232
1 2 LCD_TXOUT2+

12P_0201_50V8J
JLVDS1

+LCDVDD R377 1 2 0_0805_5% (20 MIL) +LCDVDD_R 1 1


2 2
RF@C1074
RF@C1074 +3VS 3
LCD_TXCLK- LCD_EDID_CLK 3
2 1 1 4 4
C468 1 LCD_EDID_DATA 5
10P_0402_50V8J @ C469 LCD_TXOUT0- 5
<7> LCD_TXOUT0- 6 6
RF@C1075
RF@C1075 680P_0402_50V7K @ <7> LCD_TXOUT0+ LCD_TXOUT0+ 7
2 7
2 1 LCD_TXCLK+ 680P_0402_50V7K 8 8
2 LCD_TXOUT1- CH751H-40PT_SOD323-2 D55
<7> LCD_TXOUT1- 9 9
10P_0402_50V8J <7> LCD_TXOUT1+ LCD_TXOUT1+ 10 2 1 INVT_PWM_R
B 10 <24> INVT_PWM B
<7> LCD_TXOUT2- LCD_TXOUT2- 11 11

1
<7> LCD_TXOUT2+ LCD_TXOUT2+ 12 12 R420 1
# PVT Add C1074, C1075 13 13 <7> GMCH_INVT_PWM 2 @ 0_0402_5% R11
10p and stuff for RF 2011.01.5 Change R421 to D56 LCD_TXCLK- 14 10K_0402_5%
<7> LCD_TXCLK- 14
LCD_TXCLK+ 15
and R12 pull down for KBC ESD protection <7> LCD_TXCLK+ 15
16

2
16
17 17 2011.01.5 Change R419 to D55
18
680P_0402_50V7K 2 1 C188 CH751H-40PT_SOD323-2 D56 INVT_PWM_R 19
18 and R11 pull down for KBC ESD protection
BKOFF# 19
<24> BKOFF#_L 2 1 20 20
21 21
68P_0402_50V8J 2 1 C189 1
2 +LCD_INV 22
C306
0.1U_0402_16V4Z 22
23 23
1 2 24 24
R12 10K_0402_5% +3VS_LVDS_CAM 25 34
R376 0_0805_5% USB20_N7_R 25 MGND4
250mA B+ 1 2 +LCD_INV 26 26 MGND3 33
USB20_P7_R 27 27
28
<20> DMIC_CLK
DMIC_CLK
DMIC_DAT
29
30
28
29 MGND2 32
31
Int. Camera 1 @
R392
2
0_0402_5%
+3VS_LVDS_CAM <20> DMIC_DAT 30 MGND1
R105 L13
1 1 2 2
0_0603_5% W=20mils 0.1U_0402_16V4Z #6/27 EVT I-PEX_20143-030E-20F~D USB20_N7_R
USB20_N7 <12>
+3VS 1 2 1 2 @ USB20_P7_R
USB20_P7 <12>
C313 4 3
D9 4 3
3 DMIC_CLK WCM2012F2S-900T04_0805
1 1 2
2 DMIC_DAT R393 0_0402_5%
A A
@
PACDN042Y3R_SOT23-3

For EMI request


Security Classification Compal Secret Data Compal Electronics, Inc.
LCD_TXCLK+ C871 1 2 10P_0402_50V8J LCD_TXCLK- 2010/06/27 2011/6/27 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2/25 PVT:Mount C871 with 10pF D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 16 of 36
5 4 3 2 1
A B C D E

Mini-Express Card for WLAN/WiMax 2/25 PVT:Mount C479,C480 with 47pf


3/16 PVT:Add BOM Config of C481,C482 to WLAN@
+3V_WLAN +1.5V_WLAN
120 mil
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1
C258 C259 C260 C479 C261 C262 C263 C480
WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ WLAN@
2 2 2 47P_0402_50V8J 2 2 2 47P_0402_50V8J
1 0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z 1
For WWAN request For WWAN request
+1.5V_WLAN
+1.5VS
+3V_WLAN +3VS
BT_CTRL 2 1 EC_RX_P80_CLK_R 1 2 PJ20
1K_0402_5% R888 0_0805_5% 2 1
R326 JWLAN 2 1
1 @ JUMP_43X79
1
# MP Add R326 1K for WB195 pin 51 3 3 2 2
BT_CTRL 5 4
WLAN_CLKREQ# 5 4
<9> WLAN_CLKREQ# 7 7 6 6
9 8 LPC_FRAME#_R
9 8 LPC_FRAME#_R <24>
11 10 LPC_AD3_R
<9> CLK_PCIE_WLAN# 11 10 LPC_AD3_R <24>
13 12 LPC_AD2_R #EVT WLAN&BT Combo module circuits
<9> CLK_PCIE_WLAN 13 12 LPC_AD2_R <24>
15 14 LPC_AD1_R
15 14 LPC_AD1_R <24>
16 LPC_AD0_R BT BT
16 LPC_AD0_R <24>
on module on module
PLTRST# 17 Enable Disable
CLK_PCI_DDR 17
<9> CLK_PCI_DDR 19 19 18 18
21 20 WL_OFF_R#
21 20 PLTRST#
<12> PCIE_PTX_C_IRX_N2 23 23 22 22 PLTRST# <7,13,22> BT_CRTL HI LO
<12> PCIE_PTX_C_IRX_P2 25 25 24 24
27 27 26 26
29 29 28 28 # MP Add R328
<12> PCIE_ITX_C_PRX_N2 31 31 30 30 CLK_SMBCLK <9,10> by pass for cost down
<12> PCIE_ITX_C_PRX_P2 33 33 32 32 CLK_SMBDATA <9,10>
35 34 +3VS BT_CTRL
35 34
37 37 36 36 USB20_N6 <12>
WLAN/ WiFi +3V_WLAN 39 39 38 38 USB20_P6 <12>

2
41 41 40 40
2 @ R259 R328 @ 2
43 43 42 42
45 44 LED_WIMAX#_R 1 2 LED_WIMAX# 100K_0402_5% 0_0402_5%
45 44 LED_WIMAX# <24,26>
47 47 46 46
R425 1 2 0_0402_5% 49 48 R428 R229@
<24> EC_TX_P80_DATA

1
49 48

1
R426 1 EC_RX_P80_CLK_R 0_0402_5% 100K_0402_5% D
<24> EC_RX_P80_CLK 2 51 51 50 50
0_0402_5% 52 1 2 +3VS 2 Q41
52 <13> BT_PWR#
Debug card using 53 GND
G
1

54 S 2N7002_SOT23

3
R429 GND WLAN@
100K_0402_5% CONN@ ACES_88910-5204
#DVT WLAN,WWAN and BT LED #DVT Q41 due die
control by EC and HW reserve @ D49 change to single
2

WL_OFF_R# 2 1 WL_OFF# <24>


CH751H-40PT_SOD323-2

Mini-Express Card for 3G/GPS 1 2

3G current need to 2750mA 3/16 PVT:Add BOM Config of C481,C482 to 3GGPS@ R430
0_0402_5%
+3V_WWAN +1.5V_WWAN
120 mil
#DVT R430 reserve for leakage power
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1
C265 C266 C267 C482 C268 C269 C270 C481
WWAN@ WWAN@ WWAN@ WWAN@ WWAN@ WWAN@ WWAN@ WWAN@ D14
2 2 2 47P_0402_50V8J 2 2 2 47P_0402_50V8J 1 V I/O V I/O 6
0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z
For WWAN request For WWAN request 2 Ground V BUS 5 +UIM_PWR
2/25 PVT:Mount C482,C481 with 47pf +UIM_PWR
3 +3V_WWAN +3VS 3 4 3
+1.5VS +1.5V_WWAN V I/O V I/O
IP4223CZ6_SO6-6

1
1 2 R231
1 2 R889 0_0805_5% @ 4.7K_0402_5%
R890 0_0805_5% J3GSIM @
JGPS WWAN@
WWAN@ +UIM_PWR +UIM_PWR 1 4
UIM_RST VCC GND UIM_VPP
1 120 mil 2 5

2
1 RST VPP
1

Reserve 3 2 1 UIM_CLK 3 6 UIM_DATA


3 2 D13 CLK I/O
5 5 4 4
<9> WWAN_CLKREQ# WWAN_CLKREQ# 7 6 +1.5V_WWAN C296 GLZ20A LL-34 7 8
7 6 +UIM_PWR 0.1U_0402_16V4Z GND GND
9 9 8 8 +UIM_PWR 3G@
UIM_DATA 3G@ 2 SUYIN_254020MA006S522ZL~D
<9> CLK_PCIE_WWAN# 11 10 1
2

11 10 UIM_CLK
<9> CLK_PCIE_WWAN 13 13 12 12 12P_0402_50V8J 1 1 12P_0402_50V8J
15 14 UIM_RST C297
15 14 UIM_VPP C307 C298 CONN@ 22P_0402_50V8J
16 16
3G@ 3G@ 2 3G@
2 2
17 17
19 18 # DVT For RF need stuff
19 18 UWB_OFF#_R
21 20 # DVT For RF need stuff
21 20 PLTRST#
<12> PCIE_PTX_C_IRX_N4 23 23 22 22
<12> PCIE_PTX_C_IRX_P4 25 25 24 24
27 27 26 26
29 29 28 28
31 30 CLK_SMBCLK
<12> PCIE_ITX_C_PRX_N4 31 30
33 32 CLK_SMBDATA D52 @
<12> PCIE_ITX_C_PRX_P4 33 32 UWB_OFF#_R 2
35 35 34 34 1 UWB_OFF# <24>
37 37 36 36 USB20_N5 <12>
+3V_WWAN 39 38 CH751H-40PT_SOD323-2
39 38 USB20_P5 <12>
41 41 40 40
43 42 LED_WIMAX#_R
4 43 42 4
45 45 44 44 1 2
47 47 46 46
49 48 WWAN@ R431
49 48 0_0402_5%
51 51 50 50
52 52 #DVT R431reserve for leakage power
53 GND
54 GND
P-TWO_A54402-A0G16-N
Security Classification Compal Secret Data Compal Electronics, Inc.
CONN@ Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 17 of 36
A B C D E
5 4 3 2 1

USB CONN- -Left W=30mils


+5VALW 1.4A +USB_VCCB
U24
1 GND OUT 8
SLP_CHG_M3 SLP_CHG_M4 2
3
IN OUT 7
6
IN OUT USB_OC#4
<24> USB_CHG_EN# 1 2 4 EN# OC# 5
Mode 3 R88
HIGH LOW 0_0402_5% APL3510BXI-TRG MSOP 8
<24> USB_EN# 1 2 1
Mode 4 @ R87 C288
LOW HIGH 0_0402_5% @
4.7U_0805_10V4Z
2
#PVT R88 CHG@ change to
SLP_CHG FUNCTION +3VALW always stuff for OC protect
D U11 CHG@ actioc same D
+USB_VCCB
LOW D=1D USB20_P4_S 1 1D+ VCC 10 W=30mils
USB20_N4_S +USB_VCCB 0.1U_0402_16V4Z
HIGH D=2D 2 1D- S 9 SLP_CHG# <13>
1
USB20_P4 3 8 USB20_P4_R 1 1 1
<12> USB20_P4 2D+ D+ + C2
C1 C3 C4
USB20_N4 4 7 USB20_N4_R
<12> USB20_N4 2D- D- 220U_6.3V_M_R17
USB_CHG_EN# 2 2 2 2
5 GND OE# 6

470P_0402_50V8J 1000P_0402_50V7K JUSB1


1 VCC
TS3USB221RSER_QFN10_2x1P5~D USB20_N4_RL 2
USB20_P4_RL D-
3 D+
1 2 nonCHG@ 4 GND
R221 0_0402_5%
1 2 nonCHG@ 5 GND1
R222 0_0402_5% 6 GND2
7 GND3
CHG@ 8
R211 0_0402_5% GND4 C5
2 1 SLP_CHG_M3 1 2 SUYIN_020133GB004M25MZL 0.1U_0402_16V4Z
<12> SLP_CHG_M3_PCH
@ R1 0_0402_5% CONN@ D1
CHG@ L1 1 6 1 2
R213 0_0402_5% USB20_N4_R USB20_N4_RL I/O1 I/O4
1 1 2 2
2 1 SLP_CHG_M4 2 5 +5VALW
<12> SLP_CHG_M4_PCH REF1 REF2
USB20_P4_R 4 3 USB20_P4_RL USB20_P4_RL 3 4 USB20_N4_RL
4 3 I/O2 I/O3

Use PCH 0120 reserve both EC and PCH.


+USB_VCCB
WCM-2012-900T_0805
1
@ R2
2
0_0402_5%
CM1293A-04SO_SOT23-6

For EMI request

1
CHG@ R215 R216
U12 75K_0402_1% 43K_0402_1%
C SLP_CHG_M3 1 CHG@ CHG@ C
1OE#
4
2

2
SLP_CHG_M4 2OE#
10 3OE#
13 USB20_P4_S_O
4OE# USB20_N4_S_O @
USB20_P4_S 2 3 USB20_P4_S_O <12> USB_OC#0_1_PCH 1 2 USB_OC#0_1 1 2 USB_OC#0_1_EC <24>
1A 1B
1

USB20_N4_S 5 6 USB20_N4_S_O R7 0_0402_5% R9 0_0402_5%


2A 2B USB_OC#4
9 3A 3B 8 R220 1 CHG@ 2 R218 R219 <12> USB_OC#4_PCH 1 2 1 2 USB_OC#4_EC <24>
12 4A 4B 11 100_0402_5% 51K_0402_1% 51K_0402_1% R8 0_0402_5% R10 0_0402_5%
CHG@ CHG@ @
+USB_VCCB 14 7
2

VCC GND
2
SN74CBT3125PWRG4_TSSOP14
C361
0.1U_0402_16V4Z
1 CHG@
#DVT USB_OC# control by EC

For EMI request For EMI request


2/3 DVT: Change D38,D37 from PRTR5V0U2X_SOT143-4 to CM1293A-04SO_SOT23-6

USB CONN H2 H3 H4 H11 H12 H13 H14

@ @ @ @ @ @ @
1

1
H_2P3 H_2P3 H_2P3 H_3P3 H_3P3 H_2P0N H_2P0X2P6N

+5VALW 1.4A +USB_VCCA


W=60mils # PVT Add H14 and remove H1
U18 H6 H7 H8 H9 H10
B B
1 GND OUT 8
2 IN OUT 7
3 6 1 @ @ @ @ @
USB_EN# IN OUT C283
4 5
1

1
EN# OC# @ H_2P3 H_2P3 H_1P2 H_1P2 H_1P2
APL3510BXI-TRG MSOP 8 4.7U_0805_10V4Z
2

Add 0.1u Caps for each screw hole for ESD rule
+3VS +5VALW
USB_OC#0_1

0.1U_0402_16V4Z
+USB_VCCA
1 1 1 1 1 1 @ 1
0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z
JP1
1 @ C530 @ C531 @ C528 @ C535 C534 C526@ C527
1 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2
3 3
4 4
USB20_P0 5
<12> USB20_P0 5
USB20_N0 6
<12> USB20_N0 6
7 7 Close to H1,H7 Close to H2 Close to H9,H6
USB20_P1 8
<12> USB20_P1 8
USB20_N1 9
<12> USB20_N1 9
10 10
# PVT Close to H4
11 GND
12 GND 2010.07.20 Add for ESD solution
ACES_85201-1005N_10P
CONN@ FIDUCIAL_C40M80
FM1 FM2

@ @
1

A A

FM3 FM4

@ @
1

Close to H5

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 18 of 36
5 4 3 2 1
A B C D E F G H

SATA Conn.
For 1.8" SSD
+5VS +3VS SSD HDD need 400mA for 3V(PHISON)
Place closely JHDD SATA CONN.
1.2A

1 1 1 1 1 1 1 1
1 C275 C276 C277 C278 C279 C280 C281 C282 1
@ @ @ @
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2

JSATA

GND 1
2 SATA_ITX_C_DRX_P0 C284 1 2 0.01U_0402_25V7K
A+ SATA_ITX_DRX_P0 <11>
3 SATA_ITX_C_DRX_N0 C285 1 2 0.01U_0402_25V7K
A- SATA_ITX_DRX_N0 <11>
GND 4
5 SATA_IRX_DTX_N0 C286 1 2 0.01U_0402_25V7K
B- SATA_IRX_C_DTX_N0 <11>
6 SATA_IRX_DTX_P0 C287 1 2 0.01U_0402_25V7K
B+ SATA_IRX_C_DTX_P0 <11>
GND 7

V33 8 +3VS
V33 9
V33 10
GND 11
GND 12
GND 13
V5 14 +5VS
V5 15
V5 16
GND 17
Reserved 18
2 19 2
GND
V12 20
V12 21
V12 22

GND 23
GND 24

SUYIN_127043FR022G226ZL_NR
CONN@

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401986
Date: Friday, September 02, 2011 Sheet 19 of 36
A B C D E F G H
A B C D E

Speaker Connector
RA2
+PVDD1 600 mA 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z +5V_CODEC placement near Audio Codec
1 1 0_0603_1% 1 1
CA57 CA44 RA13
place close to chip CA56 CA43 SPKL+ 2 1 SPK_L1
SPK_L1 <21>

2
0_0603_1% 1
JA1 2 2 2 2

2
0.1U_0402_16V4Z JUMP_43X39 10U_0805_10V4Z 10U_0805_10V4Z CA19
470P_0402_50V8J 2
2

1
1 1 @ place close to chip @ CA24
CA2 CA1 1 1U_0402_6.3V4Z

1
1 +3VS_DVDD @ 1
10U_0805_10V4Z +3VS_DVDD RA11 470P_0402_50V8J CA20 1
2 2
# DVT For RF
+PVDD2 2 1 +5V_CODEC RA14
0_0603_1% SPKL- 2
1 1 1 2 1 @ SPK_L2
SPK_L2 <21>
0.1U_0402_16V4Z 0.1U_0402_16V4Z CA60 @ 0_0603_1%
1 2 35 mA CA61 C224 @ RA15
+3VS +AVDD
RA1 FBMH1608HM601-T 1 1 68P_0402_50V8J SPKR+ 2 1 SPK_R1
2 2 RF@ 2 10U_0805_10V4Z SPK_R1 <21>
0_0603_1% 1
CA8 CA7
10U_0805_10V4Z RA3 CA25
2 2 68 mA 10U_0805_10V4Z 0.1U_0402_16V4Z 2 470P_0402_50V8J
1 +5V_CODEC 2
0_0603_1% @ 2 CA27
ALC259@ 1 1U_0402_6.3V4Z
UA1 ALC269@ @

39

46

25

38
1 1 1 1

9
ALC259-VB5-GR_QFN48_7X7 UA1 CA3 CA4 CA5 CA6 470P_0402_50V8J CA26 1
Change CA9 and CA10 RA16

DVDD

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2
SPKR- 2
Ext. Mic/LINE IN 2 1 @ SPK_R2
SPK_R2 <21>
to 1U at pre-MP 2 2 2 2
place close to chip 0_0603_1%
10U_0805_10V4Z 0.1U_0402_16V4Z
CA9 1U_0402_6.3V4Z
MIC1_LINE1_R_L 2 1 LINE1_L 23 40 SPKL+
<21> MIC1_LINE1_R_L
CA10 LINE1_R 24 LINE1_L SPK_OUT_L+
41 SPKL- Beep sound
<21> MIC1_LINE1_R_R
MIC1_LINE1_R_R 2 11U_0402_6.3V4Z
LINE1_R SPK_OUT_L- EC Beep RA7
14 45 SPKR+ 1 2
LINE2_L SPK_OUT_R+ <24> EC_BEEP
15 44 SPKR- 47K_0402_5%
4.7U_0805_10V4Z CA21 LINE2_R SPK_OUT_R-
MIC1_LINE1_R_L 2 1 MIC_L 21 32
MIC1_L HP_OUT_L HP_L <21>
MIC_R 22 33
MIC1_LINE1_R_R 2 1
MIC1_R HP_OUT_R HP_R <21> PCI Beep RA8
CA13
16 1 2 1 2 MONO_IN
4.7U_0805_10V4Z CA22 MIC2_L <13> PCH_SPKR
17 MIC2_R 47K_0402_5%
10 HDA_SYNC 0.1U_0402_16V4Z
2 SYNC HDA_SYNC <13> 2
DMIC_DAT 2 6 HDA_BITCLK
<16> DMIC_DAT GPIO0/DMIC_DATA BCLK HDA_BITCLK <13>
DMIC_CLK_R 3 GPIO1/DMIC_CLK

1
5 HDA_SDOUT HDA_SDOUT <13> 1
SDATA_OUT RA12 100P_0402_50V8J
EC_MUTE# 4 8 HDA_SDIN0_R 2 1 CA18
<24> EC_MUTE# PD# SDATA_IN HDA_SDIN0 <13>
RA6 33_0402_5% 4.7K_0402_5%
2

2
HDA_RST# 11 47
<13> HDA_RST# RESET# EAPD
1

48 #DVT PC beep R,C change 4.7K and 100P


MONO_IN SPDIFO
1 2 12 PCBEEP
RA40 CA11 CA12 100P_0402_50V8J 20
100K_0402_5% 0.01U_0402_25V7K MONO_OUT
@ @ SENSE_A 13
2

SENSE A
For EMI MIC2_VREFO 29
+5VALW +5VS
18 SENSE B +5V_CODEC
MIC1_VREFO_R 30 +MIC1_VREFO_R CA23 10U_0805_10V4Z
1 2 36 CBP LDO_CAP 28 1 2
CA15 ALC269@
2.2U_0603_6.3V4Z 35 27 AC_VREF 1 2
CBN VREF RA53 0_0805_5%
+MIC1_VREFO_L 31 19 AC_JDREF2 RA9 1 20K_0402_1% 1 2
MIC1_VREFO_L JDREF RA54 0_0805_5%
1 2
EC_MUTE# 43 34 CPVEE 1 2 ALC259@
PVSS2 CPVEE CA14 2.2U_0603_6.3V4Z CA17 CA16
42 PVSS1
49 DVSS2 AVSS1 26 2.2U_0603_6.3V4Z
1

2 1
7 DVSS1 AVSS2 37
RA45 0.1U_0402_16V4Z
4.7K_0402_5% Add RA45 and un-mount RA43 at PVT ALC269Q-VB2-GR_QFN48_7X7 MIC_SENSE
for audio noise issue place close to chip

1
3 3
DGND AGND
2

RA55 ALC259@
# DVT For RF need stuff 0_0402_5%

6
for EMI request
EC control EC_MUTE# behavior: High-state / low-state QA1A

2
HDA_BITCLK 1 2 1 2 ALC269@ RA28 100K_0402_5%
# DVT For RF need stuff CA47 1 2 0.1U_0603_50V7K RA42 10_0402_5% 2N7002DW-T/R7_SOT363-6 2
RF@ CA62 12P_0402_50V8J ALC269@
CA48 1 2 0.1U_0603_50V7K RF@

1
<16> DMIC_CLK 1 2DMIC_CLK_R
RA47 39_0402_5% CA49 1 2 0.1U_0603_50V7K Add RA43 for S/M battery mode at PVT
2
CA50 1 2 0.1U_0603_50V7K
C438 +3VL RA44 100K_0402_5%
100P_0402_50V8J 1 2
1 RA18 FBMH1608HM601-T for RF request

<24> SM_SENSE#

3
place close to chip For EMI
QA1B
Sense Pin Impedance Codec Signals Function ALC269@
MIC_SENSE 2 1 SENSE_A 5
+3VS B+ BACK_SENSE <21>
39.2K PORT-I (PIN 32, 33) Headphone out RA10 20K_0402_1% 2N7002DW-T/R7_SOT363-6

4
20K PORT-B (PIN 21, 22) Ext. MIC
SENSE A 1
@ CA28
2
1U_0402_6.3V4Z
<21> NBA_PLUG
10K PORT-C (PIN 23, 24) RA21 39.2K_0402_1% 1 2
4 @ CA29 1U_0402_6.3V4Z 4

5.1K (PIN 48) #EVT EMI for DMIC_CLK solution

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401986 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 02, 2011 Sheet 20 of 36
A B C D E
A B C D E

# PVT for DC mode only detect


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