LAB WORK

Retaish Raman

15534013

M.Tech(MeV)

Program:-

module counter (clk,rst,enable,count);

input clk;

input rst;

input enable;

output [3:0] count;

reg [3:0] count;

always @ (posedge clk)

begin

if (rst==1)

count = 4'b0000;

else if (enable==1)

count=count+1;

end

endmodule

Test Bench:-
`timescale 1ns / 100ps

module counter_testBench;

// Inputs
 reg clk;

reg rst;

reg enable;

// Outputs

wire [3:0] count;

// Instantiate the Unit Under Test (UUT)

counter uut (

.clk(clk),

.rst(rst),

.enable(enable),

.count(count)

);

initial begin

// Initialize Inputs

clk = 0;

rst = 0;

enable = 0;

#10 rst=1;

#21 rst=0;

#23 enable=1;

// Wait 100 ns for global reset to finish

#100;
 // Add stimulus here

end

always

begin

#5 clk=~clk;

end

endmodule

Result:- design a 4-bit counter successfully.