energies

Article
A Duty Cycle Space Vector Modulation Strategy for a
Three-to-Five Phase Direct Matrix Converter
Rutian Wang 1, * ID
, Xue Wang 1 ID
, Chuang Liu 1 and Xiwen Gao 2
1 School of Electrical Engineering, Northeast Electric Power University, Jilin 132012, China;
angeliar@163.com (X.W.); victorliuchuang@163.com (C.L.)
2 Jilin Electric Power Survey Design Limited Company, Jilin 132000, China; gxw3307@126.com
* Correspondence: wrtmail@163.com; Tel.: +86-159-4869-6698

Received: 18 January 2018; Accepted: 31 January 2018; Published: 5 February 2018

Abstract: The duty cycle space vector (DCSV) modulation strategy is of universal significance,
and the method can be utilized for different modulation approaches. In this paper, the vectors of
input voltages and currents are equivalently represented by a complex two-dimensional space vector,
and the vectors of output voltages and currents are equivalently represented by two two-dimensional
space vectors. Then, input–output relationships in both the d1-q1 space and the d3-q3 space are
obtained. Because the desired output voltages are only mapped onto a reference voltage space vector
in the d1-q1 space, the reference in the d3-q3 space is regarded as zero, in order to reduce harmonics
of output voltages to the greatest extent. Then, the duty cycle space vector modulation strategy
of the three-to-five phase direct matrix converter (DMC) is deduced. Considering the influence of
the zero vector on system performance, the duty cycles are decomposed and recomposed to obtain
the space vector pulse width modulation (SVPWM) strategy based on the duty cycle space vector.
Finally, the accuracy and feasibility of the theory are verified through experiments.

Keywords: five-phase matrix converter; modulation strategy; duty cycle space vector; space vector
pulse width modulation

1. Introduction
Multiphase drive systems involving more than three phases have been receiving increasing
attention because of their inherent advantages over the traditional three-phase motor drives.
They reduce the amplitude and increase the frequency of torque pulsations, reduce the rotor harmonic
current losses, reduce the current per phase without increasing the voltage per phase, and lower the
DC link current harmonics [1–4]. Therefore, it is necessary to develop multiphase power electronic
converters to supply such multiphase systems. Consequently, the multiphase matrix converter (MC)
has been widely studied and used in many different applications such as wind energy conversion
systems, diesel generators, microturbines, electric aircraft, and ship propulsion [5–10].
The three-to-five phase direct matrix converter is a typical multiphase power converter, and its
topology is shown in Figure 1. It has become a focus of research in the field of power transmission
and conversion due to its excellent performance. The advantages of DMCs include their sinusoidal
input and output currents, simple and compact power circuits due to the lack of electrolytic capacitors,
bidirectional power flow, and controllable input power factors [11,12]. However, modulation strategies
become more complex due to the increasing number of output phases.
Recently, many modulation strategies for the multiphase MC have been developed, including
direct duty ratio pulse width modulation (DPWM), space vector pulse width modulation,
and carrier-based pulse width modulation (CBPWM) [13–17]. The pulse width modulation (PWM)
technique is presented in [13] for a generalized three-to-k phase MC topology based on direct duty ratio
control. SVPWM is discussed in [14] for a three-to-five phase MC considering only outer large length

Energies 2018, 11, 370; doi:10.3390/en11020370 www.mdpi.com/journal/energies

 Energies 2018, 11, x FOR PEER REVIEW    2 of 14 

technique is presented in [13] for a generalized three‐to‐k phase MC topology based on direct duty 
Energies 2018, 11, 370 2 of 13
ratio control. SVPWM is discussed in [14] for a three‐to‐five phase MC considering only outer large 
length space vectors. However, for SVPWM implementation, only 93 vectors (90 active and 3 zero 
vectors) 
space can  be 
vectors. used,  and 
However, for the  complete 
SVPWM space  vector only
implementation, model 
93 of  three‐to‐five 
vectors phase 
(90 active and MC  topology 
3 zero vectors)is 
presented in [15]. To simplify the SVPWM, the CBPWM method has been adopted by researchers. 
can be used, and the complete space vector model of three-to-five phase MC topology is presented
The CBPWM technique is proposed in [16] to achieve the maximum voltage transfer ratio (VTR) in 
in [15]. To simplify the SVPWM, the CBPWM method has been adopted by researchers. The CBPWM
the  linear 
technique and  over‐modulation 
is proposed in [16] to achieve modes.  A  novel  method 
the maximum of  CBPWM 
voltage transfer based in
ratio (VTR) on 
thespace 
linearvector 
and
modulation  analysis 
over-modulation modes.is  presented 
A novel methodin  [17], 
ofusing 
CBPWM only  one  symmetrical 
based on space vector triangular  carrier 
modulation signal isto 
analysis
generate in
presented the  PWM 
[17], signals 
using only onefor symmetrical
all  of  the  switches.  Obviously, 
triangular the to
carrier signal performance 
generate theof 
PWMDMC  is  highly 
signals for
dependent on the control algorithms. 
all of the switches. Obviously, the performance of DMC is highly dependent on the control algorithms.

 
Figure 1. Topology of a three‐to‐five phase MC. 
Figure 1. Topology of a three-to-five phase MC.

InIn this paper, a new generalized strategy—duty cycle space vector modulation—is proposed to 
this paper, a new generalized strategy—duty cycle space vector modulation—is proposed to
control the three-to-five phase DMC. According to this strategy, the duty cycles have been deduced
control the three‐to‐five phase DMC. According to this strategy, the duty cycles have been deduced 
and the general expression of them has been obtained. In addition, the proposed strategy is a general
and the general expression of them has been obtained. In addition, the proposed strategy is a general 
solution
solution toto the
the modulation
modulation problem
problem ofof the three-to-five
the  three‐to‐five phase
phase DMC.
DMC.  InIn 
addition,
addition, this modulation
this  modulation 
strategy
strategy  can  be  easily  applied  to  multiphase  DMCs  in  the  future.  Then,  the  previously proposed
can be easily applied to multiphase DMCs in the future. Then, the previously proposed 
modulation (DPWM, SVPWM, CBPWM) strategies are considered as a particular case of the DCSV.
modulation (DPWM, SVPWM, CBPWM) strategies are considered as a particular case of the DCSV. 
InIn this paper, the SVPWM based on DCSV is obtained by decomposing and recombining the duty 
this paper, the SVPWM based on DCSV is obtained by decomposing and recombining the duty cycles
ofcycles 
15 switches. Finally, inFinally, 
of  15  switches.  order toin 
show theto 
order  validity of the
show  the  proposed
validity  DCSV
of  the  strategy,
proposed  an experimental
DCSV  strategy,  an 
platform is established.
experimental platform is established 

2.2. Modeling of the Three‐to‐Five Phase DMC 
Modeling of the Three-to-Five Phase DMC
The
The  topology
topology  of the three-to-five
of  the  three‐to‐five  phasephase 
DMCDMC  is shown in Figure
is  shown  in 1.Figure 
Fifteen1. 
bidirectional switches
Fifteen  bidirectional 
(BDSs) are used to connect five output phases to three input
switches (BDSs) are used to connect five output phases to three input phases, and they are defined  phases, and they are defined as SxX
(the subscripts of x and X are employed to describe the inputs and outputs,
as  SxX  (the  subscripts  of  x  and  X  are  employed  to  describe  the  inputs  and  outputs,  respectively),  respectively), where
∈ {a, b,x c},
x where  ∈ X ∈b, 
{a,  {A,
c}, B,X C,∈ D,
{A, E};B, uC, 
a , uD, 
b, u ua,  uiab,, iub c , and 
c and
E};  ic areia, three-phase input voltages
ib,  ic  are  three‐phase  input and currents,
voltages  and 
respectively, and u
currents,  respectively, 
A , u , u
B and  ,
C uDu , u
A,  uB
and i
E,  uC,  uA , i , i
D,  uBE  and 
, i , i are five-phase output voltages and
C DiA, EiB,  iC,  iD,  iE  are  five‐phase  output  voltages  currents,
and 
respectively. Lf and Cf aref and C
currents, respectively. L the inductor and capacitor of the input filter, respectively, which smooth the
f are the inductor and capacitor of the input filter, respectively, which 
current waveform.
smooth the current waveform.   
The
The  output
output voltages
voltages and and 
inputinput currents of the three-to-five
currents  phase DMC
of  the  three‐to‐five  are expressed
phase  DMC  are  respectively
expressed 
asrespectively as the following forms: 
the following forms:
   
uA daA dbA dcA    

 uB  
  daB dbB dcB  u
 a ua
uC = daC dbC dcC   ub  = D ub  (1)
      

   
 uD   daD dbD dcD  uc uc
uE daE dbE dcE
Energies 2018, 11, 370 3 of 13

 T    
  daA dbA dcA iA iA
ia 
 daB dbB dcB 


 iB 


 iB 

T
 ib  =  daC dbC dcC iC =D  iC (2)
      
  
     
ic  daD dbD dcD   iD   iD 
daE dbE dcE iE iE
where T represents transposition; the variables dxX (x ∈ {a, b, c}, X ∈ {A, B, C, D, E}) are duty cycles of
SxX ; and D is the modulation matrix.
In order to avoid short circuits on the input side and open circuits on the output side, only one
switch in every output phase is kept in the ON state at any time. Thus, the constraints of the duty
cycles are expressed as daX + dbX + dcX = 1.

3. Space Vector Expression of the Three-to-Five Phase DMC

3.1. Space Vector of the Input Side

In the three-phase symmetric system, except for the (6n ± 3)th harmonics corresponding to
zero sequence components, all the (6n ± 1)th harmonics of three-phase variables are equivalently
represented by a two-dimensional complex space vector [18]. Thus, the space vector of the input side
of the three-to-five phase DMC can be represented as follows:

2 2 4

Ui = ua + ub ej 3 π + uc ej 3 π (3)
3
2 2 4

Ii = ia + ib ej 3 π + ic ej 3 π (4)
3
where U i is the space vector of input voltages, and Ii is the space vector of input currents.

3.2. Space Vector of the Output Side

Similarly, the concept of the space vector can be extended to the five-phase symmetric system.
Each five-dimensional variable has four freedom degrees (except zero sequence components), and can
be mapped to two spaces (d1-q1 space and d3-q3 space) according to Park’s transformation of the
five-dimensional space vector. Therefore, two orthogonal space vectors synchronously rotating in the
d1-q1 and d3-q3 spaces can equivalently express five-phase variables except for the zero sequence
components. All the (10n ± 1)th harmonics of five-phase variables can be equivalently expressed as AC
components with the frequency of (10n ± 1)ω in the stationary d1-q1 space, whereas the (10n ± 3)th
harmonics of five-phase variables can be equivalently expressed as AC components with the frequency
of (10n ± 3)ω in the stationary d3-q3 space [19]. Thus, the space vectors of the output side of the
three-to-five phase DMC can be represented as follows:

2 2 4 6 8

Uo1 = uA + uB ej 5 π + uC ej 5 π + uD ej 5 π + uE ej 5 π (5)
5
2 2 4 6 8

Io1 = iA + iB ej 5 π + iC ej 5 π + iD ej 5 π + iE ej 5 π (6)
5
2 6 2 8 4

Uo3 = uA + uB ej 5 π + uC ej 5 π + uD ej 5 π + uE ej 5 π (7)
5
2 6 2 8 4

Io3 = iA + iB ej 5 π + iC ej 5 π + iD ej 5 π + iE ej 5 π (8)
5
where U o1 and Io1 are the space vectors of the output voltages and currents in the d1-q1 space,
respectively; and U o3 and Io3 are in the d3-q3 space.
Energies 2018, 11, 370 4 of 13

4. Duty Cycle Space Vector Approach

4.1. Single-Phase Duty Cycle Space Vector

The duty cycle space vector of an arbitrary output phase is defined in [20], and is expressed
as follows:
2 2 4

DX = daX + dbX ej 3 π + dcX ej 3 π (9)
3
Due to the constraint daX + dbX + dcX = 1, the expression of each duty cycle can be derived
as follows:
1 2
d xX = + DX · ej(k−1) 3 π (10)
3
where x = a, b, c; k = 1, 2, 3.

4.2. Five-Phase Duty Cycle Space Vector

The duty cycle space vector DX , instead of the modulation matrix D, can be used to express the
relationships of output voltages and input currents. Then, Equations (1) and (2) can be rewritten in the
d1-q1 space as follows:
   
Uo1 = 3 ∗ + D∗ ej 25 π + D∗ ej 45 π + D∗ ej 65 π + D∗ ej 85 π + 3 ∗ 2 4 6 8
DA + DB ej 5 π + DC ej 5 π + DD ej 5 π + DE ej 5 π (11)
10 Ui DA B C D E 10 Ui

 8 6 4 2
  2 4 6 8

Ii1 = 12 Io DA + DB ej 5 π + DC ej 5 π + DD ej 5 π + DE ej 5 π + 21 Io∗ DA + DB ej 5 π + DC ej 5 π + DD ej 5 π + DE ej 5 π (12)

Likewise, the input–output relationships in the d3-q3 space can be rewritten as follows:
   
Uo3 = 3 ∗ + D∗ ej 65 π + D∗ ej 25 π + D∗ ej 85 π + D∗ ej 45 π + 3 ∗ 6 2 8 4
DA + DB ej 5 π + DC ej 5 π + DD ej 5 π + DE ej 5 π (13)
10 Ui DA B C D E 10 Ui

 4 8 2 6
  6 2 8 4

Ii3 = 21 Io DA + DB ej 5 π + DC ej 5 π + DD ej 5 π + DE ej 5 π + 12 Io∗ DA + DB ej 5 π + DC ej 5 π + DD ej 5 π + DE ej 5 π (14)

Five new variables—D1 , D2 , D3 , D4 , and D0 —as defined by the Equations (11)–(14), can be defined
as follows:  
2 4 6 8
D1 = 51 DA + DB ej 5 π + DC ej 5 π + DD ej 5 π + DE ej 5 π
 4 8 2 6

D2 = 15 DA + DB ej 5 π + DC ej 5 π + DD ej 5 π + DE ej 5 π
 6 2 8 4

D3 = 15 DA + DB ej 5 π + DC ej 5 π + DD ej 5 π + DE ej 5 π (15)
 8 6 4 2

D4 = 15 DA + DB ej 5 π + DC ej 5 π + DD ej 5 π + DE ej 5 π
D0 = 15 (DA + DB + DC + DD + DE ).
The inverse transformation expressions of Equation (15) are

DA = D1 + D2 + D3 + D4 + D0
8 6 4 2
DB = D1 ej 5 π + D2 ej 5 π + D3 ej 5 π + D4 ej 5 π + D0
6 2 8 4
DC = D1 ej 5 π + D2 ej 5 π + D3 ej 5 π + D4 ej 5 π + D0 (16)
j 54 π j 85 π j 25 π j 65 π
DD = D1 e + D2 e + D3 e + D4 e + D0
2 4 6 8
DE = D1 ej 5 π + D2 ej 5 π + D3 ej 5 π + D4 ej 5 π + D0 .

Then, the following equations can be obtained by substituting Equation (16) into
Equations (11) and (12):
Uo1 = 23 Ui D4∗ + 32 Ui∗ D1
(17)
Ii1 = 25 Io D4 + 52 Io∗ D1 .
Energies 2018, 11, 370 5 of 13

Equation (17) shows the input–output relationship of the three-to-five phase DMC effectively and
compactly. In order to obtain the desired input power factor, suppose that ψ is the desired phase angle
for the input current space vector. Then, Equation (17) can be rewritten in the following form:

Uo1 = 23 Ui D4∗ + 32 Ui∗ D1

(18)
(Io D4 + Io∗ D1 ) · jψ = 0.

The general solution of Equation (18), which is valid for any value of the parameter λ1 , is

Uo1 ψ
D1 = + Uλ∗1I∗
3(Ui ·ψ) i o
Uo1∗ ψ
λ1
(19)
D4 = − U ∗ Io .
3 ( Ui · ψ ) i

Similarly, from substituting Equation (16) into Equations (13) and (14), D2 and D3 also can be
deduced as follows:
Uo3 ψ
D3 = + Uλ∗2I∗
3(Ui ·ψ) i o
Uo3∗ ψ
λ2
(20)
D2 = − U ∗ Io .
3 ( Ui · ψ ) i

In Equations (19) and (20), λ1 and λ2 are the degrees of freedom, which can be utilized
only if the phase angle of the output current is known. In practical applications, the method of
selecting λ1 = λ2 = 0, which does not take the output load into account, is still universal [20]. As seen
from Equations (19) and (20), when the reference voltage is synthesized in the d1-q1 space, the space
vectors in the d3-q3 space—which can cause serious distortion of the currents—are synthesized at the
same time. Since the desired output voltage is a sinusoidal waveform, the space vector of U o3 in the
d3-q3 space should be regarded as zero [17]. Then, Equations (19) and (20) can be rewritten as
q jαo jβ i
D1 = 3 cos ϕi e e ; D2 = 0
q (21)
D3 = 0; D4 = 3 cos ϕi e−jαo ejβi

where cos ϕi is the input power factor.

Then, from substituting Equation (21) into Equation (16), the general expression for duty cycle
space vectors of the three-to-five phase DMC can be obtained:

2 cos αo − (k − 1) 2π
 
DX = q 5
ejβi + D0 (22)
3 cos ϕi

According to Equations (22) and (10), when the input power factor is fixed at 1, the expressions of
15 duty cycles of the three-to-five phase DMC can be obtained as follows:
   
1 2 2π 2π 2
d xX = + q cos αo − (k − 1) cos β i − (l − 1) + D0 · ej(l −1) 3 π (23)
3 3 5 3

where k = 1, 2, 3, 4, 5 and l = 1, 2, 3; q is the voltage transfer ratio; αo is the angle of the space vector
of the output voltage; βi is the angle of the space vector of the input current; and D0 is an arbitrary
zero sequence vector. This expression is a new and compact solution for determining the modulation
method for the three-to-five phase DMC.

4.3. Discussion on the Permissible Maximum Value of the VTR

The expression of five duty cycle vectors at any moment is described by Equation (22).
As can be seen from Figure 2, the end of the five duty cycle vectors is on a line segment. The effect
of D0 is to move the duty cycle vectors, which demonstrates a strong positive relationship between the
lengths of these line segments and the voltage transfer ratio (VTR) q. The maximum difference among
Energies 2018, 11, 370 6 of 13

the five cosine functions is 2sin(2π/5), and the maximum length of any line segment in the triangle is
1. Therefore, the following expression can be obtained:

2 2 sin 2π


5
q ≤ 1. (24)
3 cos ϕi

When the input side is the unity power factor, the maximum voltage transfer ratio is obtained,
Energies 2018, 11, x FOR PEER REVIEW 
and q = 0.7886.   7 of 14 

 
Figure  2.
Figure 2.  Decomposition 
Decomposition and 
and simplification 
simplification of 
of duty 
duty cycles 
cycles of 
of the 
the three‐to‐five 
three-to-five phase  DMC:   
phase DMC:
(a) decomposition of five duty‐cycle space vectors; (b) simplification of a decomposed duty cycle. 
(a) decomposition of five duty-cycle space vectors; (b) simplification of a decomposed duty cycle.

5. SVPWM Based on DCSV 
5. SVPWM Based on DCSV  

5.1. Decomposition and Simplification of Duty Cycles of the Three-to-Five Phase DMC
5.1. Decomposition and Simplification of Duty Cycles of the Three‐to‐Five Phase DMC 
From
From Equation
Equation (1), thethe 
(1),  relationships between
relationships  line-to-line
between  outputoutput 
line‐to‐line  voltages and phase
voltages  input
and  voltages
phase  input 
can be obtained as follows:
voltages can be obtained as follows: 

uAB  uAB  daA daA−ddaB  ddbB cA− 

   
aB ddbAbA − bB ddcA dcB
dcB
     
 u
 BC  
 uBC 
 daB−ddaC
daB aC ddbB  ddbC
bB − bC ddcBcB−
dcCdcC  u
a  ua
  ub 
  u 

  
 u=  d d −ddaD ddbC −
CD  aC bC  dbD
 uCD  dbD ddcCcC−dcDdcD (25)
 
   aC aD
   b  (25) 
   uc
 DE   daD−ddaE ddbD − dbE ddcD−d dcE
  
bD  dbE
 uDE u  daD
aE cD cE   uc 
uEA  u  daE − d d − d d − d 
 EA   daE  daA aA bE  dbA
dbE bA d cE d cA
cE cA 

Equation
Equation (25)(25) shows
shows  that thethe 
that  line-to-line
line‐to‐line output voltages
output  only depend
voltages  on the difference
only  depend  between
on  the  difference 
the two duty cycles. From Equation (23), which gives 15 duty cycles of switches,
between  the  two  duty  cycles.  From  Equation  (23),  which  gives  15  duty  cycles  of  switches,  the difference beween the 
the two duty cycles in Equation (25) is irrelevant to D . For instance,
difference beween the two duty cycles in Equation (25) is irrelevant to D0. For instance, uAB, uBC, uEA
0 u AB , u BC , u CD , u DE , and u CD, 
only depend
uDE, and  on DAB (DA − DBD),ABD(D
uEA only depend on  BCA(D −B), 
 −  D DDC ), DCD
BC(D DCC), −DD
 − (D CD DCD − 
D(), DED(D
D), 
DD −DED (DE ), and DEA (DD
D −  DE), and 
−(D
E EA DEA − 
).
According to the geometrical representation proposed in [17], five duty cycle vectors (DA , DB , D
DA). According to the geometrical representation proposed in [17], five duty cycle vectors ( DCA,, D
DDB,, 
D ) of the three-to-five phase DMC can be decomposed, as
DC, DD, DE) of the three‐to‐five phase DMC can be decomposed, as shown in Figure 2a. 
E shown in Figure 2a.
As shown in Figure 2a, there is an equilateral triangle and its height is 1. The points represent
As shown in Figure 2a, there is an equilateral triangle and its height is 1. The points represent 
the
the ends
ends ofof five
five duty
duty cycle
cycle vectors
vectors (D (DAA, , DDBB,, D
DCC,,  D and D
DDD, , and  ). The 
DEE).  The size 
size of 
of the 
the duty 
duty cycles
cycles  isis  the
the 
distance between each point and the equilateral triangle’s edge. Thus,
distance between each point and the equilateral triangle’s edge. Thus, duty cycles of 15 switches are  duty cycles of 15 switches
are obtained.
obtained.  By the
By  the  example
example  given
given  in  in Figure
Figure  2a, 2a, theconstraint 
the  constrainton  onthe 
theangle 
angleof  of the 
the input 
input current
current  is is 
expressed as − π/6 ≤ β < π/6, while the relationships between the five
expressed as −π/6 ≤  βi < π/6, while the relationships between the five output voltages are expressed 
i output voltages are expressed
as uD < uC < uE < uB < uA. DD, DC, DE, DB, and DA are arranged sequentially in the positive direction of 
the  βi.  The  15  duty  cycles  in  the  modulation  matrix  can  be  expressed  by  12  differences  in  duty 
cycles, and the relationships are as follows:” 
Energies 2018, 11, 370 7 of 13
Energies 2018, 11, x FOR PEER REVIEW    8 of 14 

as uD < uC < uE < uB < uA . DD , DC , DE , DB , and DA are arranged sequentially in the positive direction
aD + 15  +  daE in the +modulation
 daB  daE  +  dmatrix  ; bedaEexpressed
=daD +  daC 
bydaD12 +differences
 daE  daC  ; in duty cycles,
daA
of the β .=dThe  daDcycles
daCduty  daC aA  daBcan
 i
and the
d = d +  d
aB relationships
aD aC  d  + 
aD are asd  d  +
aE follows:”
aC  daB  daE  ; daC = daD +  daC  daD  ; daD = daD ;

dbA =dbA ; dbB =dbA +  dbB  dbA  ; dbC =dbA +  dbB  dbA  +  dbE  dbB  +  dbC  dbE  ;  
daA = daD + (daC − daD ) + (daE − daC ) + (daB − daE ) + (daA − daB ); d = d + (daC − daD ) + (daE − daC ); (26) 
ddbD==ddbA ++ (ddbB −dbA  +  dbE  dbB  +  dbC  dbE  +  dbD  dbC  ;  dbB  dbA  +  dbE  dbB  ;


 dbE =aEdbA +aD
daD ) + (daE − daC ) + (daB − daE ); daC = daD + (daC − daD ); daD = daD ;

daB =d aD; d aC
 d+cB (dbB
dcA− d; bA );dcC =ddbC + ddbA dbB +− d  d (dbE
+ −dcC cE(d;bC − dbE );


 d(cA dbB)d+



dbAcA= dcA
bA ; cB dbB=d= cAd+bA cA = cB + bA ) +cB
dcE
(26)



ddbD = dbA++
 cD =dcA  d(cBdbB d−cAdbA
 +)+dcE(dbEdcB− d+bB)d+cC (dbC
dcE− +dbE
 d)cD+(ddbD
cC  ; bCdcE =dcA
− d ); dbE+=  dcBdbA+dcA(dbB+ −dcEdbA)d+cB (d. bE − dbB );
dcA = dcA ; dcB = dcA + (dcB − dcA ); dcC = dcA + (dcB − dcA ) + (dcE − dcB ) + (dcC − dcE );




= dcA + (dcB − dcA ) + (dcE − dcB ) + (dcC − dcE ) + (dcD − dcC ); dcE = dcA + (dcB − dcA ) + (dcE − dcB ).

dcD Given the known geometric properties of equilateral triangles, it is easy to obtain the following 
relation: 
Given the known geometric properties of equilateral triangles, it is easy to obtain the
following relation: daC  daD =  dbD  dbC  +  dcD  dcC 
daC −  daC
daEdaD ==(ddbD − dbC +) +dcC(dcDdcE− dcC )
bC  dbE
  (27) 
daE d− daCd ==(ddbC −ddbE +) + dcB− dcE )
dcE(dcC
aB aE bE bB (27)
aB  bB  dbA  +  dcB  dcA  .
daB d− daEd ==(ddbE − dbB ) + (dcE − dcB )
aA
daA − daB = (dbB − dbA ) + (dcB − dcA ).
Taking Equation (27) into account, 15 duty cycles of the three‐to‐five phase DMC can be gained 
Taking Equation (27) into account, 15 duty cycles of the three-to-five phase DMC can be gained
using  eight  differences  in  duty  cycles,  as  shown  in  Figure  2b.  Then,  the  eight  differences  in  duty 
using eight differences in duty cycles, as shown in Figure 2b. Then, the eight differences in duty cycles
cycles can be redefined as follows: 
can be redefined as follows:
δ1 = 1d=bB
dbB−ddbAbA ;  22=dbE 
; δ = dbEdbB − ;dbB ;
δ3 = 3d=bC
dbC  dbEbE ;  44 =dbD bD
− d ; δ = d −
 dbC d; bC ;
δ5 = d=cD − dcC ; δ6 = dcC − d cE ; (28) (28)
5 dcD  dcC ;  6 =dcC  dcE ;
d −ddcB ;; δ8=d= dcBd −.dcA .
δ7 = d=cE
7 cE cB 8 cB cA

Then, defining the equalities daD = doa, dbA = dob, and dcA = doc, and substituting Equations (27) and (28)
Then,  defining  the  equalities  daD =  doa,  dbA  =  dob, and  dcA  =  doc,  and  substituting Equations  (27) 
into Equation (26) leads to
and (28) into Equation (26) leads to 

daA = doa +δd1aA+=δd2oa+ +δ13++  2 δ+4 +

3 +
δ54 ++ 5δ+6+6 +δ77 +
+δ88; ; daBdaB =+d oa
2 +
+3 +δ2 4++δ53++
 6δ+4+

=doa 7 ; δ5 + δ6 + δ7 ;


daC = doa +δd4aC+=δd5oa; +d4 aD
+ 5= +δ33++  4 +δ4 5++δ65;+ δ6 ;

; daDoa ;=doad;aE d= aE =ddoaoa+




 d = d ;  d = d +δ ;
 ob ob 1 1 δ22 +
 +δ33; ;

bA ob  bAbB ob ob bB 1 ob bC
d = d ; d = d + d 1 ; = ddbC =+d δ+ + +
   (29) (29)
 dbD = dob +
  1+
dδbD δ2 ++
=dob  1δ+3+2 +43 + 4 ; bE dbE =ob
δ ; d = d dob++δ11++  2δ; 2 ;
d = doc ; ddcAcB=d=oc d; ocdcB

+=δd8oc; + 8d; cC = dcCd=ocdoc++δ66 ++ 7δ+7 +8 ;δ8 ;

 cA




oc + 5 + 6 + 7 + 8 ;cE dcE =doc +77 + 88.
dcD = doc + δd5 +=δd6 + δ7 + δ8 ; d = doc + δ + δ .
cD 
Since thethe 
Since  average value
average  of the
value  output
of  the  voltages
output  in one
voltages  in  switching period
one  switching  is decided
period  by theby 
is  decided  turn-on
the 
turn‐on time of switches rather than the order of the switching sequence, the method in this paper 
time of switches rather than the order of the switching sequence, the method in this paper rearranges
therearranges 
switchingthe  switching 
sequence, assequence, 
given byas  given  by 
Equation Equation 
(29). (29).  Therefore, 
Therefore, the  arrangement 
the arrangement of  the 
of the switching
switching sequence can be expressed as shown in Figure 3.
sequence can be expressed as shown in Figure 3.  

d 01 1  2  3  4 d 02  5  6  7  8 d 03 d 03  8  7  6  5 d 02  4  3  2 1 d 01
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Figure 3. Arrangement of a switching sequence.
Figure 3. Arrangement of a switching sequence.  
Energies 2018, 11, 370 8 of 13
Energies 2018, 11, x FOR PEER REVIEW    9 of 14 

5.2. Segment Partition for Output Voltage and Input Current 
5.2. Segment Partition for Output Voltage and Input Current
As shown
As shown inin  Figure 
Figure 2,  the 
2, the decomposition 
decomposition and and  simplification 
simplification of theof 
dutythe cycles
duty will
cycles 
not will  not  be 
be changed
changed  when  −π/6  ≤  β i  <  π/6  and  the  relationship  between  the  five  output  voltages  does  not 
when −π/6 ≤ βi < π/6 and the relationship between the five output voltages does not change.
change. Therefore, one period of input currents can be divided into six segments, while one period 
Therefore, one period of input currents can be divided into six segments, while one period of expected
of expected five output voltages can be divided into 10 segments, as shown in Figure 4, where 
five output voltages can be divided into 10 segments, as shown in Figure 4, where θ j (0 ≤ θ j < π/5) θj (0 
≤  θj  <  π/5)  and  θk  (0  ≤  θk  <  π/3)  are  the  relative  position  angles  of  the  output  voltage  and  input 
and θ k (0 ≤ θ k < π/3) are the relative position angles of the output voltage and input current in each
current in each segment, respectively.
segment, respectively.  

Figure 4. Segment partition (a) output voltages and (b) input currents. 
Figure 4. Segment partition (a) output voltages and (b) input currents.

5.3. General Expression of the Recombined Duty Cycles 
5.3. General Expression of the Recombined Duty Cycles
The case illustrated in Figure 2 refers to the vectors of output voltage and input current lying 
The case illustrated in Figure 2 refers to the vectors of output voltage and input current lying
in the
in the corresponding
corresponding sector
sector 1,
1, while   = ααoo and
while θθj j= and θθk  =  βi  +  π/6.  By  substituting  Equation  (23)  into 
k = βi + π/6. By substituting Equation (23) into
Equation (28), the expressions of eight recombined duty cycles can be obtained as follows: 
Equation (28), the expressions of eight recombined duty cycles can be obtained as follows:
  π
  π 
 π π

44 π 4 2π
 δ1 = sin π5 − θjj  cos θkk +
sinπ5 sin
1 =3 qqsin + π6  ;; δ22 == 43qsinq sin 2π5sin
sin jθcos   kθ+k + 6;
;
j cos
 δ = 43q sin 2π 5 π 5   6 π 34 5π  6π




3 5 sin 5 − θj cos
θk + 6 ; δ4 = 3 q sin 5 sin θj cos θk
+ 6 ;
 344 (30)
δ5 ==3 qqsin π2π
sin 5 sin θj cos
π θ − π ;
 kj  cos
π  δ =4 4 q sinπ 2π sin π− θ πcos
2 
 k +  ;  5  j cos 5 k +
 θ − π
;
sin  6 = 3qsin sin j  ; k 2


  43
 3 4
δ7 = 3 q sin 2π 5 5  π 6  δ8 =3 4 q sin5 π sin π −  θj cos6 θ −π ;


 5 sin θj cos θk − 2 ; 3 5 5 k 2   (30) 
 = 4 qsin π sin cos    π  ; 4
 6 =andqsin
2π π
sin    j the
  π
where θ j = αo −5 (s3− 1)π/5,     k   ;numbers of
cos segment
5 θ kj = βi −k (t 2−1)π/3 + π/6, 3 s and 5 t represent
5   2

the output voltage and input current, respectively, as shown in Figure 4.
 = 4 qsin 2π sin cos    π  ; 4
 8 = inqsin
π π   π
 7 3
The expressions of eight jrecombined k  duty cycles othersin    j combinations
segment cos   k   ; also can be
 5  2  3 5  5   2
required, and are related to the parity of the sum of the input current and the output voltage segment.
The expressions
where  θj = αo − (of the dutyθcycles
s − 1)π/5,  k = βi − ( are shown in Equations and 
t − 1)π/3 + π/6, and  (30) when the sum of segments is even, while
t represent the segment numbers of the 
they are shown in Equation (31) when the sum is odd. The relationship
output voltage and input current, respectively, as shown in Figure 4.   between odd (denoted by δ0 )
and even (denoted by of 
The  expressions  δ) can berecombined 
eight  expressed asduty  follows:cycles  in  other  segment  combinations  also  can  be 
required,  and  are  related  to  the  parity  of  the  sum  of  the  input  current  and  the  output  voltage 
δ10 = δ4 ; δ20 = δ3 ; δ30 = δ2 ; δ40 = δ1 ;
segment. The expressions of the duty cycles are shown in Equation (30) when the sum of segments  (31)
δ50 = δ8 ; δ60 = δ7 ; δ70 = δ6 ; δ80 = δ5 .
is even, while they are shown in Equation (31) when the sum is odd. The relationship between odd 
(denoted by δ’) and even (denoted by δ) can be expressed as follows: 
Due to the constraint daX + dbX + dcX = 1 on all duty cycles, the duty cycle of the zero space vector
can be obtained:  1ʹ   4 ;  2ʹ   3 ;  3ʹ   2 ;  4ʹ   1 ;
  (31) 
 5ʹ   8 ;  6ʹ   7 ;  7ʹ   6 ;  8ʹ   5 .
d0 = d01 + d02 + d03 = 1 − (δ1 + δ2 + δ3 + δ4 + δ5 + δ6 + δ7 + δ8 ) (32)
Due to the constraint daX + dbX + dcX = 1 on all duty cycles, the duty cycle of the zero space vector 
As seen from Equations (30)–(32), all active duty cycles and the zero duty cycle would be obtained
can be obtained: 
easily if output voltages and input currents could be received. Thus, the method of SVPWM based on
DCSV presented in thisd0paper  d01 isdsimpler
02  d03  1  the
than  1 traditional   5  6  7  8   
 2   3   4SVPWM. (32) 

As  seen  from  Equations  (30)–(32),  all  active  duty  cycles  and  the  zero  duty  cycle  would  be 
obtained  easily  if  output  voltages  and  input  currents  could  be  received.  Thus,  the  method  of 
SVPWM based on DCSV presented in this paper is simpler than the traditional SVPWM. 
Energies 2018, 11, x FOR PEER REVIEW 
Energies 2018, 11, 370   10 of 14 
9 of 13

6. Experimental Results 
6. Experimental Results
To  validate  the  accuracy  and  feasibility  of  the  proposed  modulation  strategy,  the  DMC 
To validate
topology  the accuracy
was  built  and feasibility
in  the  laboratory,  of thein 
as  shown  proposed
Figure  5. modulation
The  control  strategy,
system the
was  DMC topology
implemented 
was built in the laboratory, as shown in Figure 5. The control system
using the 32‐bit digital signal processor (DSP) TMS320F28335 for calculating modulation waves and  was implemented using
the 32-bit digital signal processor (DSP) TMS320F28335 for calculating modulation waves and the
the field programmable gate array (FPGA) XC6SLX9 for implementing the switching sequences and 
field programmableprocess. 
the  commutation  gate array (FPGA) XC6SLX9 for implementing
Metal‐oxide‐semiconductor  field‐effect  thetransistor 
switching (MOSFET) 
sequences and the
power 
commutation process. Metal-oxide-semiconductor field-effect transistor
switches  were  used  to  implement  the  power  circuit.  The  MOSFET  model  was  2SK1940,  with  (MOSFET) power switches
were used to implement the power circuit. The MOSFET model was 2SK1940, with maximal turn-on
maximal turn‐on and turn‐off times of 135 ns and 330 ns, respectively. Therefore, the dead time was 
and turn-off times of 135 ns and 330 ns, respectively. Therefore, the dead time was set to 500 ns in the
set to 500 ns in the program. In the experiment, the reference output voltage as set in the program 
program. In the experiment, the reference output voltage as set in the program beforehand. The DSP
beforehand. The DSP was applied to collect the input voltage, and generate PWM signals according 
was applied to collect the input voltage, and generate PWM signals according to the modulation
to the modulation strategy. PWM signals were transmitted from the DSP to the FPGA, and four‐step 
strategy.
commutation  PWM[21] signals
was were transmitted
achieved  through  from
logic theprogramming 
DSP to the FPGA, in  the and four-step
FPGA.  commutation [21]
The clamp circuit was 
was achieved through logic programming in the FPGA. The clamp circuit was designed to protect the
designed to protect the DMC against overvoltage of the input and/or output of the matrix converter. 
DMC against overvoltage of the input and/or output of the matrix converter.
Experimental tests were carried out using a three‐phase power supply (f Experimental tests were
in = 50 Hz). The input filter’s 

carried out using a three-phase power supply (f = 50 Hz). The input filter’s
parameters  were  R  =  2  Ω,  Lf  =  0.2  mH,  and  Cinf  =  20  μF,  and  the  five‐phase  loads  were parameters were R = 2 Ω,
five‐phase 
L f = 0.2 mH, and Cf = (RL) 
resistance–inductance  20 µF, and theloads (R 
balanced  five-phase loadsL were
= 16 Ω,  = 12 five-phase resistance–inductance
mH).  The switching  frequency  of (RL) the 
balanced loads (R = 16 Ω, L = 12 mH). The switching frequency of the bidirectional power switch was
bidirectional power switch was fixed at 10 kHz. 
fixedThe experiments were divided into four cases. In one case, the input phase voltage value U
at 10 kHz. in 

The experiments were divided into fouroutcases.

was 80 Vrms, the output voltage frequency f In one case, the input phase voltage value Uin
 was 20 Hz, and the voltage transfer ratio (VTR) was 
was 80 Vrms,
0.5.  The  the outputwaveforms 
experimental  voltage frequency
are  shown f out in 
was 20 Hz,6. and
Figure  The the voltage
input  transfer
phase  ratio
voltage  ua (VTR) was
and  input 
0.5. The experimental
phase current i waveforms are shown in Figure 6. The input phase voltage ua and input
a in Figure 6a clearly show the unity power factor at the input side. However, there is 

phase current ia angle 

a  displacement  in Figure 6a clearly
between  showvoltage 
the  input  the unity and power
input factor
current at the inputof 
because  side.
the However, there
input  LC  filter. 
is a displacement angle between the input voltage and input current because
Figure  6b  shows  the  waveforms  of  the  line‐to‐line  output  voltage  uAB  and  zoom  of  uAB.  Figure  of the input LC filter.
6c 
Figure
shows  6b the shows the waveforms
fast  Fourier  transform  of (FFT) 
the line-to-line
analysis  of  output and  the uoutput 
uAB,  voltage AB and zoom uAB . harmonic 
of total 
voltage  Figure 6c
shows the fast Fourier transform (FFT) analysis of uAB , and the output voltage total harmonic distortion
distortion (THD) is 8%. It is evident that the output line‐to‐line voltage contains very few low‐order 
(THD) is 8%.Figure 
harmonics.  It is evident that the 
6d  shows  the output 
output line-to-line
currents,  which voltage contains
are  balanced  very few low-order
sinusoidal  harmonics.
and  symmetrical 
Figure 6d shows the output currents, which are balanced sinusoidal and symmetrical waveforms.
waveforms. From Figure 6b–d, it is confirmed that the fundamental output voltages are sinusoidal 
From Figure 6b–d, it is confirmed that the fundamental output voltages
and symmetrical. Figure 6e shows the output line‐to‐line voltage u ABare sinusoidal and symmetrical.
, output phase voltage u A and 

Figure 6e shows the output

output phase current i line-to-line voltage uAB , output phase voltage uA and output
A, synchronously. There is a displacement angle between u phase
AB and u current
A, which is 

iabout  uAB uand uA , Awhich ◦ . There is

A , synchronously.
54°.  There  is There
also  a issmall 
a displacement
displacement angle between
angle  between  A  and i is about
  because  54resistance–
of  the 
also a small displacement angle between uA and iA because of the resistance–inductance load.
inductance load. 

 
Figure 5. Experimental prototype. 
Figure 5. Experimental prototype.
Energies 2018, 11, 370 10 of 13

Energies 2018, 11, x FOR PEER REVIEW    11 of 14 
Figure 7 shows the experimental results with Uin = 80 Vrms, f out = 20 Hz, and q = 0.6. The waveforms
Energies 2018, 11, x FOR PEER REVIEW    11 of 14 
in Figure 7Figure  7  shows 
are similar the  experimental 
to those results 
in Figure 6, but the with  Uin  =  80 
amplitude of Vrms,  fout  = 
input and 20  Hz, currents
output and  q  = is0.6. 
justThe 
slightly
waveforms  in  Figure  7  are  similar  to  those  in  Figure  6,  but  the  amplitude  of  input  and  output 
larger because
Figure the7 VTR
shows was changed
the  from 0.5 to 0.6.
experimental  It isUclear that the proposed method has the ability to
currents  is  just  slightly  larger  because results  with 
the  VTR  in  =  80 
was  changed  Vrms, 
from fout  = to 
0.5  20  Hz, 
0.6.  It and  q  =  that 
is  clear  0.6.  The 
the 
control the output
waveforms  in voltage magnitude.
Figure  7  are  similar  to  those  in  Figure  6,  but  the  amplitude  of  input  and  output 
proposed method has the ability to control the output voltage magnitude. 
currents  is  just  slightly  larger  because  the  VTR  was  changed  from  0.5  to  0.6.  It  is  clear  that  the 
proposed method has the ability to control the output voltage magnitude. 

 
Figure 6. Experimental waveforms with Uin = 80 Vrms, fout = 20 Hz, and q = 0.5: (a) input voltage ua 
Figure 6. Experimental waveforms with Uin = 80 Vrms, f out = 20 Hz, and q = 0.5: (a) input voltage 
and input  current ia; (b) output line‐to‐line voltage uAB  and  zoom  of  uAB; (c) the FFT analysis of the 
ua and input current ia ; (b) output line-to-line voltage u out = 20 Hz, and q = 0.5: (a) input voltage u
in = 80 Vrms, fAB
and zoom of uAB ; (c) the FFT analysis of
uFigure 6. Experimental waveforms with U
AB; (d) output currents iA, iB, iC, iD; (e) output  line‐to‐line voltage uAB,  output  phase voltage uA,  and 
a 

the uAB ; (d) output

and input  currents
current i iA , iB , iC , iD ; (e) output line-to-line
a; (b) output line‐to‐line voltage u voltage
AB  and  zoom  of  uABu , output phase voltage uA ,
; (c) the FFT analysis of the 
AB
output phase current iA. 
and output phase current iAA. , iB, iC, iD; (e) output  line‐to‐line voltage uAB,  output  phase voltage uA,  and 
uAB; (d) output currents i
output phase current i
For Uin = 100 Vrms and f A. 
out = 100 Hz, experimental results are shown in Figures 8 and 9 with 
For Uin = 100 Vrms and f out = 100 Hz, experimental results are shown in Figures 8 and 9 with
different VTRs of 0.5 and 0.6, respectively. Compared with Figures 6 and 7, the biggest difference is 
different For U
VTRs
in  the  of = 100 Vrms and f
in 0.5 and
waveforms  shown  out = 100 Hz, experimental results are shown in Figures 8 and 9 with 
0.6, respectively.
in  Figures  Compared
8b,d,e  withbecause 
and  9b,d,e,  Figuresthe 
6 and 7, the
output  biggest is 
frequency  difference
changed  is in
different VTRs of 0.5 and 0.6, respectively. Compared with Figures 6 and 7, the biggest difference is 
the waveforms
from  20  Hz shown in Figure
to  100  Hz.  8b,d,e
It  is  clear  that and
the Figure 9b,d,e,
proposed  because
method  the
has  the  output
ability  frequency
to  control  is changed
the  output 
in  the  waveforms  shown  in  Figures  8b,d,e  and  9b,d,e,  because  the  output  frequency  is  changed 
from voltage frequency to coincide with the reference values. 
20 Hz to 100 Hz. It is clear that the proposed method has the ability to control the output voltage
from  20  Hz  to  100  Hz.  It  is  clear  that  the  proposed  method  has  the  ability  to  control  the  output 
frequencyFrom the above experimental results, it is evident that performance of the three‐to‐five phase 
to coincide with the reference values.
voltage frequency to coincide with the reference values. 
DMC with the proposed method in this paper can be achieved. 
FromFrom the above experimental results, it is evident that performance of the three‐to‐five phase 
the above experimental results, it is evident that performance of the three-to-five phase
DMCDMC with the proposed method in this paper can be achieved. 
with the proposed method in this paper can be achieved.

 
Figure 7. Experimental waveforms with Uin = 80 Vrms, fout = 20 Hz, and q = 0.6:  (a) input voltage ua 
 
and input  current ia; (b) output line‐to‐line voltage uAB  and  zoom  of  uAB; (c) the FFT analysis of the 
uFigure 7. Experimental waveforms with U
Figure 7.; (d) output currents i
AB Experimental waveforms
in = 80 Vrms, fout = 20 Hz, and q = 0.6:  (a) input voltage ua 
A, iB, iC, iD; (e) output 
with Uin =line‐to‐line voltage u ,  output 
80 Vrms, f out = 20ABHz, and qphase voltage u
= 0.6: (a) inputA,  and 
voltage
and input  current i
output phase current i a; (b) output line‐to‐line voltage uAB  and  zoom  of  uAB; (c) the FFT analysis of the 
. 
ua and input current ia ; (b) output line-to-line voltage uAB and zoom of uAB ; (c) the FFT analysis of
A
uAB; (d) output currents iA, iB, iC, iD; (e) output  line‐to‐line voltage uAB,  output  phase voltage uA,  and 
the uAB ; (d) output currents iA , iB , iC , iD ; (e) output line-to-line voltage uAB , output phase voltage uA ,
output phase current iA. 
and output phase current iA .
Energies 2018, 11, 370 11 of 13
Energies 2018, 11, x FOR PEER REVIEW    12 of 14 
Energies 2018, 11, x FOR PEER REVIEW    12 of 14 

 
 
Figure 8. Experimental waveforms with U
Figure 8. Experimental waveforms with Uin in = 100 Vrms, fout = 100 Hz, and q = 0.5: (a) input voltage ua 
= 100 Vrms, f out = 100 Hz, and q = 0.5: (a) input voltage
Figure 8. Experimental waveforms with U
and input  current i in = 100 Vrms, f
a; (b) output line‐to‐line voltage u out = 100 Hz, and q = 0.5: (a) input voltage u
AB  and  zoom  of  uAB a 
ua and input current ia ; (b) output line-to-line voltage uAB and zoom of; (c) the FFT analysis of the 
uAB ; (c) the FFT analysis of
and input  current i ; (b) output line‐to‐line voltage u   and  zoom  of  u ; (c) the FFT analysis of the 
theuu
AB; (d) output currents iA, iB, iC, iD; (e) output  line‐to‐line voltage uAB,  output  phase voltage uA,  and 
a AB AB
; (d) output currents iA , iB , iC , iD ; (e) output line-to-line voltage uAB , output phase voltage uA ,
uABAB
; (d) output currents i
output phase current i A.  A, iB, iC, iD; (e) output  line‐to‐line voltage uAB,  output  phase voltage uA,  and 
and output phase current iA .
output phase current iA. 

 
 
Figure 9. Experimental waveforms with Uin = 100 Vrms, fout = 100 Hz, and q = 0.6: (a) input voltage ua 
Figure 9. Experimental waveforms with U
and input 
Figure 9. Experimental waveforms with Uin in = 100 Vrms, f
current ia; (b) output line‐to‐line voltage u = 100 Vrms, out = 100 Hz, and q = 0.6: (a) input voltage u
AB  and 
f outzoom 
= 100of 
Hz,uABand
; (c) the FFT analysis of the  a 
q = 0.6: (a) input voltage
ua uand input 
and current ai; (b) output line‐to‐line voltage u
inputcurrent i
AB; (d) output currents i
a ; (b) A, i B, iC, iDline-to-line
output AB  and  zoom  of 
; (e) output  line‐to‐line voltage u
voltage uAB and zoom AB, uoutput 
AB; (c) the FFT analysis of the 
of uAB ;phase voltage u A,  and of
(c) the FFT analysis
uAB; (d) output currents i
output phase current i .  A, iB, iC, iD; (e) output  line‐to‐line voltage uAB,  output  phase voltage uA,  and 
the uAB ; (d) output currents iA , iB , iC , iD ; (e) output line-to-line voltage uAB , output phase voltage uA ,
A
output phase current iA. 
and output phase current iA .
7. Conclusions 
7. Conclusions 
7. Conclusions
In  this  paper,  a  novel  method  for  the  three‐to‐five  phase  direct  matrix  converter,  named  the 
In  this  paper,  a  novel  method  for  the  three‐to‐five  phase  direct  matrix  converter,  named  the 
DCSV strategy, was proposed. For this method, the general expression of the turn‐on time of each 
In this paper, a novel method for the three-to-five phase direct matrix converter, named the
DCSV strategy, was proposed. For this method, the general expression of the turn‐on time of each 
switch was obtained. This method is of universal significance as it can realize different modulation 
DCSV strategy, was proposed. For this method, the general expression of the turn-on time of each
switch was obtained. This method is of universal significance as it can realize different modulation 
strategies through suitable use of the zero configurations. In addition, an original SVPWM strategy 
switch was obtained. This method is of universal significance as it can realize different modulation
strategies through suitable use of the zero configurations. In addition, an original SVPWM strategy 
based on the proposed DCSV was derived. The DCSV also has the ability to realize a reference load 
strategies through
of  up  to suitable use the 
0.7886  for  of the zerovoltage 
input  configurations. In addition,
in  the  linear  an original
modulation  region.  SVPWM
based on the proposed DCSV was derived. The DCSV also has the ability to realize a reference load 
voltage  strategy
A  symmetrical 
based on
voltage  the
of  proposed
up  to  DCSV
0.7886  was
for  the derived.
input  The
voltage DCSV
in  also
the  has
linear  the ability
modulation  to realize
region. 
switching  sequence  was  obtained  by  using  zero  vectors  and  active  vectors,  and  the  fewest  A a reference
symmetrical load
voltage of up sequence 
switching 
commutations  to 0.7886 for theobtained 
was 
were  realized  input voltage
in  one  in theperiod. 
by  using 
switching  linear
zero  modulation
vectors  and 
Finally,  region.vectors, 
the active  A of 
feasibility  symmetrical
and 
this  switching
the method 
novel  fewest 
commutations 
sequence was were 
obtained realized 
by using in  one 
zero
was validated through experimental results.  switching 
vectors and period. 
active Finally, 
vectors, the 
andfeasibility 
the fewestof  this  novel 
commutations method 
were
was validated through experimental results. 
realized in one switching period. Finally, the feasibility of this novel method was validated through
experimental results.
Energies 2018, 11, 370 12 of 13

Acknowledgments: This research is funded by National Key R&D Program of China under grant
number 2017YFB0903300.
Author Contributions: Rutian Wang and Xue Wang conceived the theory; Chuang Liu performed the experiments
and analyzed the data; Xiwen Gao contributed materials and analysis tools; Rutian Wang and Xue Wang wrote
the paper.
Conflicts of Interest: The authors declare no conflict of interest.

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