Multiplex Ers

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MULTIPLEXERS
EX:NO:2 4:1 MULTIPLEXER
AIM
To design and implement 4:1 multiplexer using Verilog HDL and to view the floor
planning for the same.
APPARATUS REQUIRED
1. PC with Windows XP.
2. Xilinx ISE Design Suite 10.1
PROCEDURE
1. Write and draw the Digital logic System.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code with test bench inputs
(using ISE Simulator) and verify the output waveform as obtained.
5. Implement the above code in FPGA kit.
PROGRAM
module multiplexer(y,s0,s1,d0,d1,d2,d3);
input s0;
input s1;
input d0;
input d1;
input d2;
input d3;
output y;
wire w1,w2,w3,w4,w5,w6;
not n1(w1,s0);
not n2(w2,s1);
and a1(w3,d0,w1,w2);
and a2(w4,d1,w1,s1);
and a3(w5,d2,s0,w2);
and a4(w6,d3,s0,s1);
or a5(y,w3,w4,w5,w6);
endmodule
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TEST BENCH INPUT
#50 s0=0;s1=0;d0=0;d1=1;d2=0;d3=0;
#50 s0=0;s1=0;d0=0;d1=0;d2=0;d3=0;
#50 s0=1;s1=1;d0=0;d1=1;d2=0;d3=1;
#100 $finish;
RTL SCHEMATIC DIAGRAM
TECHNOLOGY SCHEMATIC
LUT SCHEMATIC
TRUTH TABLE
K-MAP
SIMULATION
Simulator is doing circuit initialization process. Finished circuit initialization process.
Initialization
Input selection
Simulation Output
Simulation Output using Test Bench
FLOOR PLANNING
RESULT
The design and implementation of 4:1 multiplexer using Verilog HDL and floor planning
are done using Xilinx and the simulation for the same is done using ISE simulator.
DECODERS
EX:NO:3 3(a) 2X4 DECODER
AIM
To design and implement 2x4 decoder using Verilog HDL and to view the floor planning
for the same.
APPARATUS REQUIRED
PROCEDURE
8. Write and draw the Digital logic system.
PROGRAM
module decoder(y0,y1,y2,y3,s0,s1);
input s0,s1;
output y0,y1,y2,y3;
wire w1,w2;
not n1(w1,s0);
not n2(w2,s1);
and a1(y0,w1,w2);
and a2(y1,w1,w2);
and a3(y2,w1,w2);
and a4(y3,s0,s1);
endmodule
TEST BENCH INPUT
#50 S0=0;S1=0;
#50 S0=1;S1=0;
#50 S0=1;S1=1;
#100 $finish;
RTL SCHEMATIC
LUT SCHEMATIC
TRUTH TABLE
K-MAP
SIMULATION
Initialization
Input Selection
Simulation Output
Simulation Output Using Test Bench
FLOOR PLANNING
RESULT
The design and implementation of 2x4 decoder using Verilog HDL and floor planning
EX:NO:3 3 (b) 3x8 DECODER

AIM:
To design and implement using 3x8 decoder Verilog HDL and to view the floor planning
for the same.
APPARATUS REQUIRED:
PROCEDURE:
PROGRAM
module threedecoder(y0,y1,y2,y3,y4,y5,y6,y7,s0,s1,s2);
input s0,s1,s2;
output y0,y1,y2,y3,y4,y5,y6,y7;
wire w1,w2,w3;
not n1(w1,s0);
not n2(w2,s1);
not n3(w3,s2);
and a1(y0,w1,w2,w3);
and a2(y1,w1,w2,s2);
and a3(y2,w1,s1,w2);
and a4(y3,w1,s1,s2);
and a5(y4,s0,w2,w3);
and a6(y5,s0,w2,s2);
and a7(y6,s0,s1,w3);
and a8(y7,s0,s1,s2);
endmodule
TEST BENCH INPUT
#50 s0=0;s1=0;s2=1;
#50 s0=0;s1=0;s2=0;
#50 s0=0;s1=1;s2=1;
#50 s0=1;s1=0;s2=0;
#50 s0=1;s1=0;s2=1;
#50 s0=1;s1=1;s2=0;
#50 s0=1;s1=1;s2=1;
#100 $finish;
RTL SCHEMATIC
LUT SCHEMATIC
TRUTH TABLE
K-MAP
SIMULATION
Initialization
Input Selection
Simulation Output
Simulation Output using Test Bench
FLOOR PLANNING
RESULT:
The design and implementation of 3x8 decoder using Verilog HDL and floor planning
COMPARATORS
EX:NO:4 4(a) 1-BIT COMPARATOR
AIM:
To design and implement using 1-bit comparator Verilog HDL and to view the floor
APPARATUS REQUIRED:
PROCEDURE:
PROGRAM
module onebitcomp(a,b,x,y,z);
input a,b;
output x,y,z;
assign x=((~a)&(~b))|((a)&(b));
assign y=(a)&(~b);
assign z=(~a)&(b);
endmodule
RTL SCHEMATIC
LUT SCHEMATIC
TRUTH TABLE
K-MAP
SIMULATION
Initialization
Input Selection
Simulation Output
FLOOR PLANNING
RESULT:
The design and implementation of 1-bit comparator using Verilog HDL and floor
planning are done using Xilinx and the simulation for the same is done using ISE simulator.
EX:NO:4 4 (b) 2-BIT COMPARATOR

AIM:
To design and implement using 2-bit comparator Verilog HDL and to view the floor
APPARATUS REQUIRED:
PROCEDURE:
PROGRAM
module twobitcomp(x,w,z,s0,s1,s2,s3);
input s0,s1,s2,s3;
output x,w,z;
assign
z=((~s0)&(~s1)&(~s2)&(~s3))|((~s0)&(s1)&(~s2)&(s3))|((s0)&(s1)&(s2)&(s3))|((s0)&(~
s1)&(s2)&(~s3));
assign w=((s0)&(~s2))|((s1)&(~s2)&(~s3))|((s0)&(s1)&(~s3));
assign x=((~s0)&(s2))|((~s1)&(s3))|((~s1)&(s2)&(s3));
endmodule
RTL SCHEMATIC DIAGRAM
TECHONOLOGY SCHEMATIC
LUT SCHEMATIC
TRUTH TABLE
K-MAP
SIMULATION
Initialization
Input Selection
Simulation Output
FLOOR PLANNING
RESULT:
The design and implementation of 2-bit comparator using Verilog HDL and floor
planning are done using Xilinx and the simulation for the same is done using ISE simulator.
EX:NO:5 STUDY OF XILINX FPGA TRAINER KIT
AIM
To Study the Xilinx FPGA Trainer Kit.
KIT SPECIFICATIONS
1. FPGA Specifications:
1.1 Hardware:
Family: Spartan3E
Device: XC3S250E
Package: PQ208
Speed Grade: -4
1.2 Software:
Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISE Simulator (VHDL/Verilog)
2. Other hardware:
1. Clock Generation:
*The trainer kit has two clock sources

*Fixed clock of 4MHz connected to PIN No: 181
Manual clock by push-to-on switch connected to PIN No: 178. When the key is
pressed once,one positive going pulse will be applied to the clock pin of FPGA.
2. Input Signal Generation:
The input signallevel is generated using DIP switches. The DIP-switch has 8
separate switches. When the switch is ON position the output will be ‘0’ level,
which is fed to FPGA as input. When the switch is OFF position the output of this
will be ‘1’ level. The ‘RC’ is used to limit the current, while connecting to ground
point.
2.3 Output’s:
The FPGA device outputs are connected to bar-graph LEDs which shows the
output level. The output is ‘1’ level the LED will be glowing and when the output
is at ‘0’ level the LED will be in off.
2.4 Bi-directional Lines:

The PIN Nos. 106, 107, 108, 109, 112, 113, 115 & 116 of FPGA can be used as
bi-directional, in which the output can be viewed at DS7 and the input can be set
by switch S1. The circuit diagram of single line
2.5 Edge Triggered Signals:
PIN Nos. 126, 127 and 128 are connected to push-to-on switches, which generate
a positive going pulse.
2.6 Keyboard:
The trainer kit has a 4*4 key matrix connected to the FPGA I/O lines.
2.7 Seven Segment Display:

The trainer kit has 4 digit seven segment displays, which are multiplexed.
2.8 LCD:
The trainer kit has one 16*2 LCD display.
RS - LCD Register Select Signal
R/W - LCD Read / Write Signal
EN - LCD Enable Signal
D7-D0 - LCD Data Lines
2.9 26-pin FRC Lines
FPGA Kit Interfacing Diagram
XILINX SPARTAN 3E TRAINER KIT SPECIFICATIONS

Model No: VSK-SPARTAN 3E
Key components and features:
Family: Xilinx Spartan3E FPGA

Device: XC3S500E
Package: FT256
Speed Grade: -4
16 Nos. of digital input using slide switches:
16 Nos. of digital output using discrete LEDs
FPGA configuration through
*JTAG port
* Slave serial
* Onboard Flash PROM XCFO4S
Onboard programmable oscillator from 3 MHz to 200 MHz

16 Nos. of digital output using discrete LEDs
RESULT
Thus the study of Xilinx Simulation Trainer kit is successfully completed.
EX:NO:6 DESIGN AND IMPLEMENTATION OF FIR FILTER
AIM
To design and implement a FIR Filter using Xilinx software and FPGA Trainer kit.
APPARATUS REQUIRED
Software
Hardware
1. Family: Spartan3E
2. Device: XCS250E
PROCEDURE
3. Write and draw the Digital logic System.
PROGRAM
module filter(clk,a,b,c,x,l,m,n,s,d,t,e);
input [1:0]a,b,c,x;
input clk;
input[3:0]l,m,n,s;
input[4:0]d,t;
output[5:0]e;
mul m1(clk,l,x,c);
mul m2(clk,m,x,b);
mul m3(clk,n,x,a);
flop dflop1(clk,l,s);
add a1(clk,d,m,s);
flop dflop2(clk,d,t);
a a2(clk,e,n,t);
endmodule
module flop(clk,d,q);
input clk;
input [4:0]d;
output reg[4:0]q;
always@(posedge clk)
begin
q<=d;
end
endmodule
module mul(clk,f,g,h);
input clk;
input[1:0]g,h;
output reg[3:0]f;
begin
f<=g*h;
end
endmodule
module add(clk,f,g,h);
input clk;
input[3:0]g,h;
output reg[4:0]f;
begin
f<=g+h;
end
endmodule
module a(clk,f,g,h);
input clk;
input[3:0]g;
input[4:0]h;
output reg[5:0]f;
begin
f<=g+h;
end
endmodule
SIMULATION
Initialization
Input Selection
Simulation Output
SYNTHESIS REPORT
Started: “Synthesize – XST”.

Running xst
Reading design: filter.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=====================================================================
* Synthesis Options Summary *
=====================================================================
---- Source Parameters
Input File Name : "filter.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "filter"
Output Format : NGC
Target Device : xc3s250e-4-ft256
---- Source Options

Top Module Name : filter
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES

Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options

Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options

Optimization Goal : Speed
Optimization Effort :1
Library Search Order : filter.lso
Keep Hierarchy : NO
Netlist Hierarchy : as_optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=====================================================================
=====================================================================
* HDL Compilation *
=====================================================================
Compiling verilog file "filter.v" in library work
Module <filter> compiled
Module <flop> compiled
Module <mul> compiled
Module <add> compiled
Module <a> compiled
No errors in compilation
Analysis of file <"filter.prj"> succeeded.
=====================================================================
* Design Hierarchy Analysis *
=====================================================================
Analyzing hierarchy for module <filter> in library <work>.
Analyzing hierarchy for module <mul> in library <work>.
Analyzing hierarchy for module <flop> in library <work>.
Analyzing hierarchy for module <add> in library <work>.
Analyzing hierarchy for module <a> in library <work>.

=====================================================================
* HDL Analysis *
=====================================================================
Analyzing top module <filter>.
Found 6 error(s). Aborting synthesis.
-->
Total memory usage is 157248 kilobytes
Number of errors : 6 ( 0 filtered)

Number of warnings : 2 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Reading design: FILTERNEW.prj
=====================================================================
* HDL Compilation *
=====================================================================
Compiling verilog file "FILTERNEW.v" in library work
Module <FILTERNEW> compiled
Module <flop> compiled
Module <mul> compiled
Module <add> compiled
Module <a> compiled
No errors in compilation
Analysis of file <"FILTERNEW.prj"> succeeded.
=====================================================================
* Design Hierarchy Analysis *

=====================================================================
Analyzing hierarchy for module <FILTERNEW> in library <work>.
Analyzing hierarchy for module <mul> in library <work>.
Analyzing hierarchy for module <flop> in library <work>.
Analyzing hierarchy for module <add> in library <work>.
Analyzing hierarchy for module <a> in library <work>.

=====================================================================
* HDL Analysis *
=====================================================================
Analyzing top module <filter>.
Module<filter> is correct for synthesis.
Analyzing module<mul>in library<work>

Module<mul>is correct for synthesis.
Analyzing module<flopl>in library<work>

Module<flop>is correct for synthesis.
Analyzing module<add>in library<work>

Module<add>is correct for synthesis.
Analyzing module<a>in library<work>

Module<a>is correct for synthesis.
====================================================================
* HDL Synthesis *
====================================================================
Performing bidirectional port resolution…
Synthesizing Unit<mul>.
Related source file
Found 4-bit register for signal <f>
Found 2x2-bit multiplier for signal <f$mult0000> created at line 52.
Summary:
inferred 1 Multiplier(s).
Unit <mul> synthesized.
Synthesizing Unit <flip>.

Related source file is “filter.v”.
Found 5-bit register for signal <q>.
Unit <flop> synthesized.
Synthesizing Unit <add>.

Found 5-bit register for signal <f>.
Found 4-bit adder carry out for signal <f$addsub0000> created at line 62.
Summary:
inferred 1 Adder/Subtractor(s).
Unit<add>synthesized.
Synthesizing Unit <a>.

Found 6-bit register for signal <f>.
Found 5-bit adder carry out for signal <f$addsub0000> created at line 73.
Summary:
inferred 1 Adder/Subtractor(s).
Unit <a> synthesized.
Synthesizing Unit <filter>
Unit <filter> synthesized.
====================================================================
HDL Synthesis Report
Macro Statistics
#Multipliers :3
2x2-bit multiplier :3
# Adders/Subtractors :2
4-bit adder carry out :1
# Registers :7
4-bit register :3
5-bit register :3
6-bit register :1
====================================================================
* Advanced HDL Synthesis *
====================================================================
Advanced HDL Synthesized Report
Macro Statistics
#Multipliers :3
2x2-bit multiplier :3
# Adders/Subtractors :2
====================================================================
* Low Level Synthesis *
====================================================================
Optimizing unit <filter>…
Optimizing unit <mul>…
Optimizing unit <flop>…
Optimizing unit <add>…
Optimizing unit <a>…
====================================================================
* Partition Report *
====================================================================
Partition Implementation Status
………………………
No Partitions were found in this design.
……………………
Process “Synthesize – XST” completed Successfully.
RESULT
The design and implementation of FIR Filter using Xilinx and the simulation for the
same is done using ISE simulator with FPGA kit.
EX:NO:7 STUDY OF MATLAB
AIM
To Study the MATLAB Tool.
THEORY
MATLAB (short for Matrix Laboratory) is a special-purpose computer program

optimized to perform engineering and scientific calculations. The MATLAB program
implements the MATLAB language and provides a very extensive library of predefined
functions to make technical programming tasks easier and more efficient.
Advantages of Matlab for Technical Programming

1. Ease of Use
2. Platform Independence
3. Pre-Defined Functions
4. Device-Independent Plotting
5. Graphical User Interface
6. MATLAB Compiler
Features of MATLAB
1. Emphasis on Top-Down Design Methodology
2. Emphasis on Functions
3. Emphasis on MATLAB Tools
4. Good Programming Practice
The MATLAB Environment
The fundamental unit of data in any MATLAB program is the array. An array is a
collection of data values organized into rows and columns and known by a single name.
The three most important types of windows are

1. Command Window – Where commands may be entered
2. Figure Window - Which display plots and graphs
3. Edit Window - Which permit a user to create and modify MATLAB
. programs
MATLAB Operators
1. Arithmetic Operators and Arrays
2. Relational Operators and Arrays
3. Element-Wise Operators and Functions
4. Logical Expressions Using the find Function
5. Bit-Wise Functions
6. Overriding Default Precedence
Disadvantages of MATLAB
MATLAB has two principle disadvantages.
1. It is an interpreted language and therefore can execute more slowly than compiled
languages.
2. High cost, a full copy of MATLAB is five to ten times more expensive than a
conventional C or Fortran compiler.
Initializing Variables in MATLAB
MATLAB Variables are automatically created when they are initialized. There are three
common ways to initialize a variable in MATLAB.
1, Assign data to the variable in an assignment statement.
2.Input data into the variable from the keyboard.
3.Read data from a file.
Built-in MATLAB Functions

In mathematics, a function is an expression that accepts one or more input values and
calculates a single result from them.
Common MATLAB Functions
1. Mathematical Functions – abs(x),acos(x),angle(x),asin(x),atan(x),cos(x), exp(x),log(x)
etc.,
2. Rounding Functions – ceil(x),fix(x),floor(x),round(x)
3. String Conversion Functions – char(x),double(x),num2str(x), etc.,
Debugging MATLAB Program
Errors in programs are known as bugs, and the process of locating and eliminating them
is known as debugging.
There are three types of errors are found in MATLAB programs.
1. Syntax Errors
2. Run-Time Errors
3. Logical Errors
Plot using MATLAB

MATLAB’s extensive, device-independent plotting capabilities are one of its most
powerful features. They make it very easy to plot any data at any time. To plot a data set, just
create two vectors containing the x and y values to be plotted, and use the plot function.
Printing a Plot
Once created, a plot may be on a printer with the print command, by clicking on the
“print” icon in the Figure Window, or by selecting the “File/Print” menu option in the figure
Window.
The print command is especially useful because it can be included in a MATLAB
program, allowing the program to automatically print graphical images.
CREATING and RUN a MATLAB FILE

4. Open the MATLAB by Double clicking the icon.
5. Create a New file by File→ new→ blank M-file.
6. Enter the MATLAB coding for the corresponding Experiments.
7. Save the file with .m extension.
8. Debug the coding.
9. Run the coding.
10. By giving the corresponding input values, then the output graph is obtained.
RESULT
Thus the study of MATLAB Tool is successfully completed.
EX:NO:8 ESTIMATION OF R,C,L VALUES OF INTERCONNECTS

AIM:
To Estimate the Resistance, Capacitance and Inductance of Interconnects using
MATLAB.
APPARATUS REQUIRED
Software
11. MATLAB
PROCEDURE
12. Open the MATLAB.
13. Create a new file by File→ new→ blank M-file.
14. Type the MATLAB coding for estimation of R,C,L.
15. Run the coding to obtain the value of R,C and L.
16. Estimated values can be obtained in the Output Window.
DESIGN
Wire dimensions for resistance and capacitance calculations

T– interconnect thickness; H – Vertical interconnect separation; S – Horizontal interconnect separation;
W – interconnect width; ; L – interconnect length
T and H are fixed parameters based on the fabrication process
W, S and L are under the designer’s control
DESIGN EQUATIONS
L = µ0 µr A N2 / l
MATLAB SOURCE CODE

clc;
clear;
% Estimation of R value for interconnection
p=input ('Enter the value of Specific Resistance in ohm/cm = ');
L1=input ('Enter the value of Length in meters = ');
A = input ('Enter the value of Area in meter sqr = ');
x=p*L1;
R=x/A;
display (R);
% Estimation of C value for interconnection
cg=input ('Enter the values of cg in pf = ');
cc= input ('Enter the values of cc in pf = ');
x=2*cg;
y=2*cc;
C = x+y;
display (C);
% Estimation of L value for interconnection
m0=1.257*exp(-6);
mr=1;
a=input('Enter the value of Area in meter sqr = ');
l=input ('Enter the value of Length in meters = ');
N=input ('Enter the value of No.Of.Turns = ');
L = ((m0*mr*a*N^2)/l);
display (L);
% The values of Resister,Capacitor,Inductor for interconnection
display (' The Estimatedvalues of R,C,L of Intrconnections are ');
display (R);
display (C);
display (L);
OUTPUT
Enter the value of Specific Resistance in ohm/cm = 44.64
Enter the value of Length in meters = 0.5
Enter the value of Area in meter sqr = 1.2
R = 18.6000
Enter the values of cg in pf = 15
Enter the values of cc in pf = 10
C = 50
Enter the value of Area in meter sqr = 1.5
Enter the value of Length in meters = 1.2
Enter the value of No.Of.Turns = 20
L = 1.5579
The Estimated values of R,C,L of Interconnections are
R = 18.6000
C = 50
L= 1.5579
RESULT
Thus the Resistance ( R ), Capacitance ( C ), Inductance ( L ) of Interconnections were
designed and values were estimated successfully.
EX:NO:9 MOSFET MODELING USING NEWTON RAPHSON METHOD

AIM
To design and simulate the V-I characteristics of P-Channel and N-channel MOSFET
using Newton Raphson method.
APPARATUS REQUIRED
Software
17. MATLAB
PROCEDURE
20. Type the MATLAB coding for Newton Raphson Method.
21. Run the coding of Newton Raphson method to obtain the value of x and number
of iterations.
22. By the value of x, output graph is obtained.
MATLAB SOURCE CODE
clc;
clear all;
format long;
syms x;
e = 1e-5; % setting the tolerance value
dx = e+1;
f = log(2-x) +x^2; % enter your function here;
x=7; % initially assumed value of x
count=0; % setting counter to know the no of iterations taken
p = zeros(1,1);
while (abs(dx)>e) % initializing the iteration and continue until the error is less
than tolerance
dx = eval(f/(diff(f))); % calculating dx, diff is used for finding the differentiation of
the function
x = x-dx; % updating the value of x
count = count +1; % incrementing the counter
p(count)=x;
drawnow();
plot(abs(p),'r','linewidth',3);
grid;
if(count>300)
fprintf('Error...! Solution not converging !!!\n'); % printing the error message
break;
end
end
if(count<300)
fprintf('The solution ='); % printing the result
x
fprintf('\n Number of iteration taken = %d\n',count);
end
OUTPUT
The solution:
x = 0.268213493174994 - 0.854413795679647i
Number of iteration taken = 13
RESULT
The V-I characteristics of P-Channel and N-Channel MOSFET using Newton Raphson
method is designed and simulated.
EX:NO:10 DEVICE MODELING USING SCHRODINGER EQUATION
AIM:
To simulate of Schrodinger equation based device modeling for MOSFET using
MATLAB.
APPARATUS REQUIRED
Software
23. MATLAB
PROCEDURE
26. Type the MATLAB coding for device modeling using Schrodinger equation.
27. Run the coding.
28. By giving the corresponding input values, then the output graph is obtained.
The Time independent Schrodinger’s Equation.
-h2 / 2m 2 ψ (Z) + V ( Z ) ψ (Z) = E ψ (Z)
MATLAB SOURCE CODE

clc;
clear;
x0=0;
m=1.1;
sum2=1;
n = input ('Enter energy state n: ');
x1 = input('Enter length of the well (in nm):');
while(floor(m)<m)
h=input ('Enter stepsize in nm:');
m=(x1-x0)/h;
if floor (m)<m
warning ('Stepsize is wrong. Enter proper value');
end
end
x=x0:h:x1;
y=zeros(size(x));
y(1)=0;
y(m+1)=0;
y(2) = 1;
for i=3:m
y(i) = -(y(i-2) + ((-2+(n*n*pi*pi*h*h/(x1*x1)))*y(i-1)));
sum2=sum2+y(i)^2;
end
y=y/sqrt(sum2);
y2=y.^2;
figure('color','white');
subplot(2,1,1);
plot(x,y,'r');
xlabel('Distance in nm');
ylabel('wave function');
subplot(2,1,2);
plot(x,y2);
xlabel('Distance in nm');
ylabel('propality density');
OUTPUT
Enter energy state n: 10

Enter length of the well (in nm):10
Enter step size in nm: 0.01
RESULT
The device modeling of a MOSFET using Schrodinger equation is designed and
simulated.
EX:NO:11 STUDY OF SPICE SIMULATION TOOL

AIM:
To study the PSpice simulation tools.
THEORY:
Electronic circuit design requires accurate methods for evaluating circuit performance.
Because of the enormous complexity of modern integrated circuits, computer-aided circuit
analysis is essential and can provide information about circuit performance that is almost
impossible to obtain with laboratory prototype measurements.
SPICE is a general-purpose circuit program that simulates electronic circuits. SPICE can
perform various analyses of electronic circuits: the operating (or the quiescent) points of
transistors, a time-domain response, a small-signal frequency response, and so on. SPICE
contains models for common circuit elements. Active as well as passive, and it is capable of
simulation most electronic circuits. It is a versatile program and is widely used both in industries
and universities. The acronym SPICE stands for Simulation Program with Integrated Circuit
Emphasis.
PSpice, which uses the same algorithms as SPICE2 and is a member of the SPICE family, is
equally useful for simulating all types of circuits in a wide range of applications. A circuit is
described by statements that are stored in a file called the circuit file. The circuit file is read by
the SPICE simulator. Each statement is self-contained and independent; the statements do not
interact with each other. SPICE (or PSPICE) statements are easy to learn and use.
TYPES OF ANALYSIS:
PSpice allows various types of analysis. Each analysis is invoked by including its command
statement. For example, a statement beginning with the .DC command invokes the DC sweep.
The types of analysis and their corresponding. (dot) commands are described below.
DC Analysis is used for circuits with time-invariant sources (e.g., steady-state dc sources). It
calculates all node voltages and branch currents over a range of values, and their quiescent (dc)
values are the outputs.
1. DC sweep of an input voltage/current source, a model parameter, or
temperature over a range of values (.DC)
2. Determination of the linearized model parameters of nonlinear devices
(.OP) dc operating point to obtain all node voltages (.OP)
3. Small-signal transfer function with small-signal gain, input resistance, and output
resistance (Thevinin’s equivalent) (.TF)
4. DC small-signal sensitivities (.SENS)
Transients Analysis is used for circuits with time-invariant sources (e.g., ac sources and
switched de sources). It calculates all node voltages and branch currents over a time interval, and
their instantaneous values are the outputs.
1. Circuits behavior in response to time varying sources (.TRAN)

2. DC and Fourier components of the transient analysis results (.FOUR)
AC Analysis is used for small-signal analysis of circuits with sources of variable
frequencies. It calculates all node voltages and branch currents over a range of frequencies, and
their magnitudes and phase angles are the outputs.
1. Circuits response over a range of source frequencies (.AC)
2. Noise generation at an output node for every frequency (.NOISE)
LIMITATION OF PSpice:
As a circuit simulator, PSpice has the following limitations:
1. The student version of PSpice is restricted to circuits with 10 transistors only.
2. The program is not interactive.
3. PSpice does not support and interactive method of solution.
4. The input impedance cannot be determined directly without running the graphic post-
processor, Probe.
5. The PC version needs 512 kilobytes of memory (RAM) to run.
6. Distortion analysis is not available in PSpice.
7. The output impedance of a circuit cannot be printed or plotted directly.
OrCAD PSpice:
OrCAD PSpice A/D is a simulation program that models the behavior of a circuit
containing any mix of analog and digital devices.
PSpice A/D can perform the following types of analyses:
1. AC, DC and transient analyses, so you can test the response of your circuits to different
inputs.
2. Parametric, monte carlo, and sensitivity/worst-case analysis , so you can see how your
circuit’s behavior varies with changing components values
3. Digital worst-case timing analysis to help you find timing problems that occur with only
certain combination of slow and fast signal transmissions.
PSpice A/D also supports analog and digital behavioral modeling, so you can describe
functional block of circuitry using mathematical expressions and functions.
1. Transmission line models, including delay, reflection, loss, dispersion, and crosstalk.
2. Nonlinear magnetic core models, including saturation and histerisis.
3. Six MOSFET models.
4. Five Gas FET models
5. IGBTs
6. Digital components with analog I/O models
STIMULUS EDITOR:
The stimulus editor is the utility that allows you to quickly setup and verify the input
waveforms for the transient’s analysis. The stimulus editor is graphical waveform editor that
allows you to define the shape of time-based signals used test your circuit design’s response
during simulation.
BASIC ANALYSES:
1. AC sweep and noise.
2. DC sweep & other DC calculation.
3. Transient and Fourier.
NETLIST:
A netlist is the connectivity description of a circuits, showing all of the components, their
interconnection, and their values. When you create a simulation netlist from OrCAD capture, that
netlist describes the current design.
During the netlist process, capture creates several files with different extensions
1. .NET file contains the netlist.
2. .CIR file contains simulation commants.
3. .ALS file contains alias information.
TYPES OF DESCRIPTION:
1. Circuit description
2. Analyses description
3. Output description
STEPS TO CREATING A CIRCUIT FILE:
1. Double click the PSpice AD students icon.
2. Go to file – select new and choose text file.
3. Write the various parameters in forms that are allowed by PSpice.
4. Save the file with extension of .CIR
STEPS TO RUN A CIRUCUIT FILE:
1. Go to file and select open simulation.
2. Choose and input file (.CIR file)
3. Select open.
4. Run and simulate the circuit file.
5. Choose and output file name, default is circuit file with an .OUT extension.
6. Trace the output waveform.
STEPS TO ABORT PSPICE:
7. Click on close box.
8. Select QUIT from the file menu.
RESULT:
Thus the study of PSpice Simulation tool is successfully completed.
EX:NO:12 CMOS INVERTER

AIM
To design a CMOS Inverter and to study the DC & Transient characteristics using PSpice
Simulation Tool.
APPARATUS REQUIRED
10. OrCAD PSpice
PROCEDURE
7. Select open.
CMOS INVERTER
CIRCUIT DIAGRAM:
VDD
4
CMOS INVERTER
M1 PMOS
M1
1 3
Y=a
M4
V1
NMOS
M2
vss
0
0
PSpice NetList
VDDS 2 0 5V
VIN 1 0 DC 5V PULSE(0 5V 0 1NS 10NS 20US 40US)
RL 3 0 100k
M1 3 1 2 2 PMOD L=1U W=20U
.MODEL PMOD PMOS(VTO=2 KP=4.5E-4 CBD=5PF CBS=2PF RD=5
+RS=2 RB=0 RG=0 RDS=1MEG CGSO=1PF CGDO=1PF CGBO=1PF)
M2 3 1 0 0 NMOD L=1U W= 5U
.MODEL NMOD NMOS(VTO=-2 KP=4.5E-5 CBD=5PF CBS=2PF RD=5
+RS=2 RB=0 RG=0 RDS=1MEG CGSO=1PF CGDO=1PF CGBO=1PF)
.TRAN 1US 100US
.TF V(3) VIN
.OP
.PLOT TRAN V(1)
.PROBE
.END
SIMULATION OUTPUT
1.0V
0.5V
SEL>>
0V
V(3)
4.0V
0V
-4.0V
0s 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms
V(1)
Time
DC CHARACTERISTICS
Simulation Output Waveform
TRANSIENT CHARACTERISTICS
Simulation Output Waveform
RESULT
Thus the CMOS Inverter and the study of DC & Transient Characteristics using PSpice
was designed and simulated.
EX:NO:13 CMOS NAND GATE

AIM
To design and simulate a CMOS NAND gate circuit using PSpice Simulation Tool.
APPARATUS REQUIRED
11. OrCAD PSpice
PROCEDURE
7. Select open.
CMOS NAND GATE

CIRCUIT DIAGRAM:
VDD
4
M2
M1
1
3
0V
V1
M3 Y=a.b
0 5
2
M4 V2
0V
vss
0
0
2-Input NAND Gate with CMOS Logic
V1 V2 Y
A Y
Low Low High
B
Low High High
High Low High
High High Low
PSpice NetList
VDD 4 0 DC 5V
VIN1 1 0 DC 5V ; INPUT VOLTAGE CAN BE VARIED AS PER TRUTH TABLE
VIN2 2 0 DC 5V
RL 3 0 100K
M1 4 1 3 0 PMOD L=5U W=20U
M2 4 2 3 0 PMOD L=5U W=20U
.MODEL PMOD PMOS(VTO=-2 KP=4.5E-4 CBD=5PF
+CBS=2PF RD=5 RS=2 RB=0 RG=0
+RDS=1MEG CGSO=1PF CGDO=1PF CGBO=1PF)
M3 3 1 5 0 NMOD L=5U W=20U
M4 5 2 0 0 NMOD L=5U W=20U
.MODEL NMOD NMOS(VTO=-2 KP=4.5E-5 CBD=5PF
.TRAN 1US 80US
.TF V(3) VIN1
.OP
.PLOT TRAN V(2) V(1)
.PROBE
.END
SIMULATION OUTPUT
5.0V
2.5V
0V
0s 10us 20us 30us 40us 50us 60us 70us 80us
V(1) V(3)
Time
RESULT
Thus the CMOS NAND Gate using PSpice is designed and simulated.
EX:NO:14 CMOS NOR GATE

AIM
To design and simulate a CMOS NOR gate circuit using PSpice Simulation Tool.
APPARATUS REQUIRED
11. OrCAD PSpice
PROCEDURE
7. Select open.
CMOS NOR GATE

CIRCUIT DIAGRAM:
VDD
4
M1
3
1
M2
V1
0V
5
Y= a + b
M4
0 M3
2
V2
0V
0 vss
0
2-Input NOR Gate with CMOS Logic
V1 V2 Y
A Y
Low Low High
B
Low High Low
High Low Low
High High Low
PSpice NetList
VDD 4 0 DC 5V
VIN1 1 0 DC 0V
VIN2 2 0 DC 0V
M1 4 1 3 0 PMOD L=5U W=20U
M2 3 2 5 0 PMOD L=5U W=20U
.MODEL PMOD PMOS (VTO=-2 KP=4.5E-4 CBD=5PF
M3 5 2 0 0 NMOD L=5U W=20U
M4 5 1 0 0 NMOD L=5U W=20U
.MODEL NMOD NMOS (VTO=-2 KP=4.5E-5 CBD=5PF
.TRAN 1US 80US
.TF V (5) VIN1
.OP
.PLOT TRAN V (2) V(1)
.PROBE
.END
SIMULATION OUTPUT
RESULT
Thus the CMOS NOR Gate using PSpice is designed and simulated.

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RTL SCHEMATIC DIAGRAM

Simulation Output using Test Bench

TEST BENCH INPUT

Simulation Output Using Test Bench

EX:NO:3 3 (b) 3x8 DECODER

Simulation Output using Test Bench

EX:NO:4 4 (b) 2-BIT COMPARATOR

RTL SCHEMATIC DIAGRAM

EX:NO:5 STUDY OF XILINX FPGA TRAINER KIT

To Study the Xilinx FPGA Trainer Kit.

*The trainer kit has two clock sources

2. Input Signal Generation:

2.4 Bi-directional Lines:

2.7 Seven Segment Display:

XILINX SPARTAN 3E TRAINER KIT SPECIFICATIONS

Key components and features:

Family: Xilinx Spartan3E FPGA

Onboard programmable oscillator from 3 MHz to 200 MHz

Started: “Synthesize – XST”.

---- Source Options

Decoder Extraction : YES

---- Target Options

---- General Options

Analyzing hierarchy for module <mul> in library <work>.

Analyzing hierarchy for module <flop> in library <work>.

Analyzing hierarchy for module <add> in library <work>.

Analyzing hierarchy for module <a> in library <work>.

Number of errors : 6 ( 0 filtered)

* Design Hierarchy Analysis *

Analyzing hierarchy for module <mul> in library <work>.

Analyzing hierarchy for module <flop> in library <work>.

Analyzing hierarchy for module <add> in library <work>.

Analyzing hierarchy for module <a> in library <work>.

Analyzing module<mul>in library<work>

Analyzing module<flopl>in library<work>

Analyzing module<add>in library<work>

Analyzing module<a>in library<work>

Synthesizing Unit <flip>.

Synthesizing Unit <add>.

Synthesizing Unit <a>.

Optimizing unit <filter>…

Optimizing unit <mul>…

Optimizing unit <flop>…

Optimizing unit <add>…

Optimizing unit <a>…

EX:NO:7 STUDY OF MATLAB

To Study the MATLAB Tool.

MATLAB (short for Matrix Laboratory) is a special-purpose computer program

Advantages of Matlab for Technical Programming

The MATLAB Environment

The three most important types of windows are

Built-in MATLAB Functions

Plot using MATLAB

CREATING and RUN a MATLAB FILE

EX:NO:8 ESTIMATION OF R,C,L VALUES OF INTERCONNECTS

Wire dimensions for resistance and capacitance calculations

MATLAB SOURCE CODE

EX:NO:9 MOSFET MODELING USING NEWTON RAPHSON METHOD

Number of iteration taken = 13

EX:NO:10 DEVICE MODELING USING SCHRODINGER EQUATION

The Time independent Schrodinger’s Equation.

-h2 / 2m 2 ψ (Z) + V ( Z ) ψ (Z) = E ψ (Z)

MATLAB SOURCE CODE