Curriculum-Vitae

House No 57, Sector 55

NIT-Faridabad,
Haryana-121004
Tel. No. : 0129-2232120
Mob No. : +919899689747
Email: karun.saraswat@st.com

Karun Saraswat

Employment Profile:

Total Experience : 3 years and 11 months.

Current Employer : STMicroelectronics Pvt. Ltd. Greater Noida, India
Duration : 18th September 2006 - present.
Designation : Sr. System Software engineer
Job Description : I am required to develop Integration and validation platforms for
embedded systems supporting various architectures and host environments. The device under
test may be a SOC or Hardware Chip or any software. I also have good experience of linux device
driver validation (ADC, I2S, SPI, Touch screen, SMP feature of linux), silicon validation, ASIC
Firmware validation (refer GPE project), bare metal initialization codes and code porting.

Academic Profile – Graduation

Bachelor of Technology (Electronics and Instrumentation Control Engineering) from The
YMCA Institute of Engineering, Faridabad affiliated to Maharishi Dayanand University; Rohtak
with an aggregate of 66.4% in may 2006.

Academic Profile – Elementary Schools

• All India Senior Secondary School Examination (2002) - MVN Sr. Sec School, Sector 17,
Faridabad with an aggregate of 85.40 %.
• All India Secondary School Examination (2000) - DAV Public School, Sector 49, Faridabad with
an aggregate of 81.00 %.

Technical Skills:
Programming Languages : C, C++ (with basic knowledge of data structures).
Assembly languages : 8085, 8051 and ARM Instruction set v7.
Scripting Languages : Ruby, TCL, Unix shell scripting.
RTOS : Embedded Linux (ELDK, STLinux), VxWorks-6.4, Fusion RTOS and
Kadak-AMX.
Debugging Tools : Knowledge of various ARM embedded system development tools
like Trace32 ARM debugger, ARM Instruction set simulator (ARMISS).
GNU tools like GDB, DDD. VxWorks Workbench 2.6 which includes its
WDB agent based tools. Logic Analyzer, CRO and Function Generator
etc
Embedded processor : Good knowledge of ARM926eJS, Cortex A9 processor. This core is
part of proprietary SPEAr SOC family of STMicroelectronics.
Compilers : armcc (RVCT 3.0), GNU cross compilers for ARM like ELDK, Code
Sourcery etc. VC++.
Protocol/Specifications :
1) WiMedia MBOA MAC & WiMedia MAC-PHY Interface.
2) Open source Transport Communication Framework specifications
covered under eclipse target management project
(http://www.eclipse.org/dsdp/tm/)

Career Projects

Project 1: Generic Device Driver Automated testing platform

Duration: Nov 2008 – Jan 2009, Feb 2010 – May 2010, June 2010 - present
Team Size: 1
Client: Internal
Platform components: Linux Host PC, SPEAr SOC.

Description and role: This project covered development of regression platform for testing linux
device drivers of various SPEAr IP’s (SSP, ADC, touch-screen etc). Platform provided method for
writing test cases and integrating with the host PC and Target SOC. This regression platform was
based on TCF specifications and used TCF based agents and clients. Various features of this tool
are test selection, test automation; software crash handlings, reboot supports, common launch
environment for host initiated and target initiated test cases. I was responsible for full
development and deployment of this regression tool so that it make testing of drivers exhaustive.
Presently I am doing the feasibility of how this can be upgraded to set up a shared lab for remote
embedded application development. Features planned – IP distribution across boards, Test Case
distribution, filtering, remote debugging etc.

Project 2: I2S Silicon Validation

Duration: May 2010 – June 2010

Team Size: 1
Client: Internal

Description and role: This required post silicon validation of I2S IP of Proprietary SOC of ST. It
included validating various IP features like modes (Master and Slave), frequency, channels etc.

Project 3: GPE device Validation

Duration: May 2009 – Feb 2010

Team Size: 2
Client: Internal
Platform components: Visual Studio, GPE simulators, FPGA kits

Description and role: This project required validation of General Purpose encryption (GPE)
device. This hardware chip works as encryption accelerator and provides encryption Key
management features. Device under test consists of GPE hardware and its driver. It required a
special kind of testing called “Random Testing” as this was a security related project and aim was
to make it unbreakable. For this I developed a random testing tool which tested the devices state
machine for all possible combinations.
Project 4: Fusion RTOS bare metal porting

Duration: March 2009 – May 2009

Team Size: 2
Client: Internal
Platform components: SPEAr SOC and Windows host machine

Description and role: This project required porting of light weight Fusion RTOS on SPEAr SOC.
This included providing start-up code for Fusion RTOS, initializing the MMU, Caches, VIC, stacks,
various ARM exception mode configurations etc.

Project 5: Driver Testing for various IPs

Duration: Jan 2009 – March 2010

Team Size: 4
Client: Internal
Platform component: Target SPEAr SOC, Host Linux machine, VxWorks Workbench v2.6

Description and role: This covered testing of various IPs like SSP, ADC, Touch screen etc.
Kernel mode and User space applications were developed for testing the drivers. Test cases were
designed in such way that it can be integrated to VxWorks Regression platform and TCF based
Linux regression platform. My role was to assist team members in understanding the two Linux
and VxWorks regression platform and develop test cases. I developed test cases for SSP, ADC
and touch screen IP’s.

Project 6: Virtual embedded software platform

Duration: Aug 2008 – Oct 2008

Team Size: 2
Client: Internal
Platform Components: TLM behavioral models, ARMISS, VxWorks Workbench v2.6.

Description and role: This project aimed at developing Virtual embedded platform for SPEAr
SOCs enabling early development of IPs and integration to SOC. I was required to provide Driver
and OS support to demonstrate capabilities of these platforms to potential customers.
Demonstrated capabilities included the functional accuracy of the virtual embedded platform and
speed performance of the system.

Project 7: VxWorks Board support package (BSP) Test platform for SPEAr SOC drivers

Duration: Feb 2008 – May 2008

Team Size: 1
Client: Internal
Platform: VxWorks workbench v2.6

Description and Role: The project required the development of automated testing platform for
SPEAr SOC VxWorks BSP. Platform was required to support easy development and integration of
test cases on target SOC and control it from the Host PC. My role was to gather requirement,
study the existing regression platforms, identify the key features of the platform to be
implemented and do the complete development, testing and deployment of tool.
Project 8: MAC Integration
Duration: September 2006 – Feb. 2008
Group size: 4
Client: Internal
Platform: SystemC based TLM platforms, ARM based SPEAr SOC.

Description: The project required the complete development and integration of MAC software
layer with System C Model of HW platform, then with RTL model of MAC HW and finally porting it
on ARM platform. The project also involves MAC integration with Wireless USB layer & dummy
PHY layers. Porting and Integrating MAC on two Board test platform which was specifically
designed to execute the Test cases required for MAC development. For Two board platform, one
board was used as PHY traffic generator and the other board was used as MAC device.

Role:
1) Development of Two Board platform. This validation platform was to test and validate MAC
(SW+HW). This included development of agent task on two boards and a Environment
controller on host PC.
2) Trace Generation for real time debugging of MAC. This required development of a Ethernet
based trace generation system on target SOC running MAC HW and SW. Traces generated
were viewed and saved for further use. Traces covered the context switching, signal
passing and task states.

Co-curricular Activities
• Member of organizing committee of the Inter-College Technical Fest-CULMYCA 2K6.
• Participated and won several prizes in quiz and extempore in various inter and intra
college fests.
• Vice-captain of Nilgiri house in school and actively involved in organizing various school
functions.

Demographic details

Sex : - Male.
Date of Birth : - 13 March, 1984.
Father’s Name : - Mr. Rakesh Kumar Saraswat
Mother’s Name : - Mrs. Chanderkanta Saraswat
Languages Known : - English, Hindi.