Design Plan NNG Feed Through Creation

Electrostatic Discharge (ESD) Analysis
Using Voltus IC Integrity: Rapid

Adoption Kit (RAK)
Product Version Voltus 17.1 (SSV17.1)

May, 2017
Note:
 RAK Test case database, Scripts and References can be found at the
‘Attachments’ and ‘Related Solutions’ sections just below the PDF section on
https://support.cadence.com
 This pdf can be searched with the RAK ‘Title’ on https://support.cadence.com

Copyright Statement
© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are
registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective
holders.
Learn more at Cadence Online Support - https://support.cadence.com

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Page 2
Voltus ESD: RAK
Contents
Purpose ....................................................................................................................... 4
Audience...................................................................................................................... 4
Software ...................................................................................................................... 4
Overview ...................................................................................................................... 4
Circuit Description........................................................................................................ 5
Lab1 (Creating the ESD PGVs) ................................................................................. 10
ESD PGVs for IOpad and PowerCell macros ........................................................ 10
PGVs for STDCELL ............................................................................................... 11
PGV for techonly cells ............................................................................................ 12
LAB2 (Clamp-to-clamp R) .......................................................................................... 14
LAB3 (Standalone clamp-to-clamp run) ..................................................................... 18
LAB4 (Multistage testing not available)...................................................................... 19
Lab5 (Bump-to-clamp and node run) ......................................................................... 20
Summary ................................................................................................................... 21
Support ...................................................................................................................... 21
Feedback ................................................................................................................... 21

Voltus ESD: RAK
Purpose
This Rapid Adoption Kit (RAK) is a self-training tool to introduce you to Voltus-ESD and
help you understand and implement its flow for Electrostatic Discharge in packaged
chips.
Audience
The RAK is meant for advanced users who have read in detail the “ESD Checks on Full
Chip Using Voltus” Application Note and have the basic understanding of the tool. A
prerequisite is training on Voltus 15.1. Familiarity with Voltus 15.1 RAK may also suffice.
Software
The examples in this kit have been developed using the latest release of VOLTUS 17.1.
It may also work with version 16.2 if all PGVs are redone for this version. Some of the
features in the workshop may not be supported in earlier releases.
Overview
This RAK is meant for those who are familiar with the Voltus flow and understand how
the tool manipulates power and rail parameters to show IR-Drop, resistance profile of
the grid and a horde of other grid analysis landmarks. This is just to understand how the
grid design has been done and how successful it is under normal operation. It will help
you understand how to visualize unique current flows in an ESD event, which are far
from normal operation, and what vulnerabilities are indicated in reports and visuals.
It is better to understand this early on that the normal operation and ESD operation are
distinctly different. The normal operation only functions when the power is connected,
while power connections have no meaning for ESD operation. A voltage zap or a
current surge can happen between any two pins, regardless of whether the pin is power
or signal. Only the contents of the IO cells are important. The R of the grid, substrate
and wells are important if it is an epitaxial process. Every IO contains a clamp and/or
capacitor. The capacitor is either purpose-built or exists inadvertently in large IO
devices.
you need to be familiar with the “ESD Checks on Full Chip Using Voltus” Application
Note released recently. Training on the Voltus 15.1 RAK is also a requirement. Refer to
the Voltus 16.1 Users Guide for details of the tool operation for ESD handling.

Voltus ESD: RAK
Circuit Description
The RAK uses a small chip designed using internal 45nm PDK of Cadence as shown in
Figure 1. It does not have a functioning core because ESD analysis has no need for it.
All the cores represent thin gate devices, which are at risk of ESD leaks, easily
damaging the GOX of the devices or blowing the wells. The design has 16 power cells
(powercells) and 16 IO cells (iocells) with the powercells in pairs on either side of the
four contiguous IO cells. There are four iocells per side, making it a pad-limited square
die.
The core is a synthesized SPI smeared around the die with actual timing placements.
The bottom-right powercells power all the core via an internal padring (see Figure 2),
and the top-left powercells connect the internal rings vddl and vssl (not shown). Figure 3
and 4 are close up of the PNR power connections to the internal ring. Figure 5 shows
the standard cell power routes for vdd and vss.
All powercells and iocells have identical power feedthroughs that get connected via
abutments. This forms an internal padring that is connected to the core padring via M4
as shown in Figure 6. There is an ESD clamp inside each cell, and iocells contain
human body clamp protections on inputs. The clamps are diodes formed from n-
channels and p-channel devices with tied source-drains instead of true p-n junction
formations. For ESD purposes, the entire cell is considered an ESD clamp since the R
to the clamp is trivial.

Voltus ESD: RAK
Figure 1. Schematic of 16 IOs and 16 powerpads plus four corner cells

Voltus ESD: RAK
Figure 2. Full chip layout showing timed core placements and routings to the ios

Voltus ESD: RAK
Figure 3. Pad connections on Figure 4. Close up of vdd

vdd and vss to internal ring connection to internal ring
Figure 5. Stdcell power route

Voltus ESD: RAK
Figure 6. Layout for vss pad showing abutment pins

and bondpad to the internal core vss connect pin

Voltus ESD: RAK
Lab1 (Creating the ESD PGVs)

This lab demonstrates the creation of PGVs for cells. This is the most important part of
the ESD flow. Any error here will make ESD analysis fail. These are special PGVs that
define each of the macros as a detailed macro with a special designation as an ESD
cell. The detailed internal description of the ESD cell with its metal connectivity lets the
tool, estimate the correct R of the padring and report ESD path failures.
It is important to remember that the corner cells in the design are passive fillers with no
ESD clamp embedded. The rest are considered ESD ready. The corners have metals in
place that let the padring form a complete ring around the chip for the dirty supply
(output pad power). The clean supply is broken up at the corners to give four electrically
separated power pair on each side, appropriately named vddl/vssl, vddr/vssr, vddt/vsst
and vddb/vssb. The vddr and vssr are renamed simply vdd and vss for ease in PNR
routing.
ESD PGVs for IOpad and PowerCell macros

Creating PGVs for the clamp macros (all pads and corners) takes roughly 10 minutes.
Script
set_multi_cpu_usage -localCpu 16
#
# Please note that -celltype macro cannot be used. It needs to be stdcell for parser to parse spectre netlist
#
set_multi_cpu_usage -localCpu 16
#-----------------------------------------------------------------------
# Load LEF files
#-----------------------------------------------------------------------
read_lib \
-lef \
../../rak_collaterals/BONDPAD52.lef \
../../rak_collaterals/giolib045_modified.lef
#-----------------------------------------------------------------------
# workaround for reading spectre netlist use 15.22-s043. The full support for spectre in 16.1.
#-----------------------------------------------------------------------
set_advanced_pg_library_mode -libgen_command_file ../rak_collaterals/libgen.cmd -verbosity true
#-----------------------------------------------------------------------
# clamp cells description
#-----------------------------------------------------------------------
set_advanced_pg_library_mode -common_supply_pins PAD -esd_cells {PADVDDIOR PADVSSIOR PADVDD
PADVSS PADDB padIORINGCORNER}
#-----------------------------------------------------------------------
# Macro pll pgv generation
#-----------------------------------------------------------------------
set_pg_library_mode \
-ground_pins {VSS VSS1 VSS2 VSSIOR} \
Voltus ESD: RAK
-power_pins {VDD 0.9 VDD1 0.9 VDD2 0.9 VDDIOR 0.9} \

-celltype macros \
-gds_files {\
../../rak_collaterals/padioringcorner.gds \
../../rak_collaterals/PADVSSIOR.gds \
}\
-filler_cells {padIORINGCORNER} \
-cell_list_file ../../rak_collaterals/macro_list.txt \
-spice_subckts {\
../../rak_collaterals/netlist.hs \
}\
-gds_layermap ../../rak_collaterals/gds.layermap \
-lef_layermap ../../rak_collaterals/lefdef.layermap \
-stop@via CONT \
-spice_models ../../rak_collaterals/spectre_load.sp \
-current_distribution propagation \
-extraction_tech_file ../../rak_collaterals/gpdk045.tch
generate_pg_library \
-output pgv_macro
Run
Change the directory to pgv/macro and the source to run.csh. After the run ends, check
the report file under pgv_macro/*.report for anything that “FAILED”.
PGVs for STDCELL

Creating PGVs for all stdcells takes about 25 minutes.
Script
#-----------------------------------------------------------------------
# Load LEF files
#-----------------------------------------------------------------------
read_lib \
-lef \
../../rak_collaterals/gsclib045_tech.lef \
../../rak_collaterals/gsclib045_macro.lef
#-----------------------------------------------------------------------
# workaround for reading spectre netlist use 15.22-s043. The full support for spectre in 16.1.
#-----------------------------------------------------------------------
set_advanced_pg_library_mode -libgen_command_file ../../rak_collaterals/libgen.cmd
#-----------------------------------------------------------------------
# Standard cells pgv generation
#-----------------------------------------------------------------------
-ground_pins VSS \
-power_pins {VDD 0.9 ExtVDD 0.9} \
-celltype stdcells \
-cell_list_file ../../rak_collaterals/stdcell_list.txt \

Voltus ESD: RAK
-spice_models ../../rak_collaterals/spectre_load.sp \
-spice_subckts { \
../../rak_collaterals/gsclib045.sp \
}\
-current_distribution propagation \
-extraction_tech_file \
../../rak_collaterals/gpdk045.tch
setvar output_directory_name pgv_stdcell
-output pgv_stdcell
Run
Change the directory to pgv/stdcell and the source to run.csh. After the run ends, check
the report file under pgv_stdcell/stdcells.report for anything that “FAILED”.
PGV for techonly cells

This is to create the techonly PGV needed for all ESD runs.
Script
#-----------------------------------------------------------------------
# Load LEF files
#-----------------------------------------------------------------------
read_lib -lef { \
../../rak_collaterals/gsclib045_tech.lef \
../../rak_collaterals/gsclib045_macro.lef \
../../rak_collaterals/ioringdb_modified.lef \
../../rak_collaterals/giolib045_modified.lef \
}
#-----------------------------------------------------------------------
# Techonly pgv generation
#-----------------------------------------------------------------------
-celltype techonly \
-ground_pins {VSS ExtVSS} \
-power_pins {VDD 0.9 Ext_VDD 0.9} \
-decap_cells {DECAP2 DECAP3 DECAP4 DECAP5 DECAP6 DECAP7 DECAP8 DECAP9 DECAP10} \
-filler_cells {FILL1 FILL2 FILL4 FILL8 FILL16 FILL32 FILL64} \
-default_area_cap 0.01 \
-cell_decap_file ../../rak_collaterals/decap_values.txt \
-extraction_tech_file ../../rak_collaterals/gpdk045.tch \
-powergate_parameters { \

Voltus ESD: RAK
{FSWNX1 ExtVSS VSS 750 0.5 4.0e-8} \

{FSWX1 ExtVSS VSS 750 0.5 4.0e-8} \
{HSWDNX1 Ext_VDD VDD 750 0.5 4.0e-8} \
{HSWDX1 Ext_VDD VDD 750 0.5 4.0e-8} \
{HSWNX1 Ext_VDD VDD 750 0.5 4.0e-8} \
{HSWX1 Ext_VDD VDD 750 0.5 4.0e-8} \
}
-output pgv_tech
Run
Change the directory to pgv/techonly and the source to run.csh. After the run ends,
check the report file under techonly/pgv_tech/techonly.report for anything that “FAILED”.

Voltus ESD: RAK
LAB2 (Clamp-to-clamp R)
This lab checks clamp-to-clamp resistance of the ESD design. This does a full static
and dynamic analysis to ensure the design works for the normal operation.
Script
#
# ESD RAK in 45nm Cadence PDK
# LAB2: clamp to clamp R including static and dynamic run to check chip integrity.
#
#
#
#
set_multi_cpu_usage \
-localCpu 8
setExtractRCMode -engine postRoute -specialNet true -coupled true -viaCap true
#-----------------------------------------------------------------------
# load design
#-----------------------------------------------------------------------
set lefs [list]
lappend lefs ../rak_collaterals/gsclib045_tech.lef
lappend lefs ../rak_collaterals/gsclib045_macro.lef
lappend lefs ../rak_collaterals/giolib045_modified.lef
read_lib -lef $lefs
read_view_definition ../rak_collaterals/viewDefinition.tcl
read_verilog ../rak_collaterals/ccc.v
set_top_module chip_top -ignore_undefined_cell
set_dc_sources {VDDT} -power -voltage 1.33

set_dc_sources {VSST} -ground -voltage 0.00
set_dc_sources {VDD} -power -voltage 1.33
set_dc_sources {VSS} -ground -voltage 0.00
set_dc_sources {VDDB} -power -voltage 1.33
set_dc_sources {VSSB} -ground -voltage 0.00
set_dc_sources {VDDL} -power -voltage 1.33
set_dc_sources {VSSL} -ground -voltage 0.00
set_dc_sources {VDDIO} -power -voltage 1.33
set_dc_sources {VSSIO} -ground -voltage 0.00
read_def ../rak_collaterals/esd_routing.def
#-----------------------------------------------------------------------
# Read spef file
#-----------------------------------------------------------------------
read_spef \
-rc_corner rc_worst \
-decoupled \
../rak_collaterals/esd.spef
#-----------------------------------------------------------------------
# Static Power Analysis
#-----------------------------------------------------------------------
Voltus ESD: RAK
set_power_analysis_mode \
-reset
set_power_analysis_mode \
-write_static_currents true \
-binary_db_name staticPower.db \
-create_binary_db true \
-method static
#-----------------------------------------------------------------------
# power nets when you don't use cpf
#-----------------------------------------------------------------------
set_pg_nets -net VDDT -voltage 1.33 -threshold 1.1 -force
set_pg_nets -net VDD -voltage 1.33 -threshold 1.1 -force
set_pg_nets -net VDDB -voltage 1.33 -threshold 1.1 -force
set_pg_nets -net VDDL -voltage 1.33 -threshold 1.1 -force
set_pg_nets -net VSST -voltage 0 -threshold 0.1 -force

set_pg_nets -net VSS -voltage 0 -threshold 0.1 -force
set_pg_nets -net VSSB -voltage 0 -threshold 0.1 -force
set_pg_nets -net VSSL -voltage 0 -threshold 0.1 -force
set_pg_nets -net VDDIO -voltage 1.33 -threshold 1.1 -force

set_pg_nets -net VSSIO -voltage 0.00 -threshold 0.1 -force
set_rail_analysis_domain -name domain_vddr -pwrnets {VDD} -gndnets {VSS}

set_rail_analysis_domain -name domain_vddb -pwrnets {VDDB} -gndnets {VSSB}
set_rail_analysis_domain -name domain_vddl -pwrnets {VDDL} -gndnets {VSSL}
set_rail_analysis_domain -name domain_vddt -pwrnets {VDDT} -gndnets {VSST}
set_rail_analysis_domain -name domain_vddio -pwrnets {VDDIO} -gndnets {VSSIO}
#-----------------------------------------------------------------------
# to define power for instances that are missing .lib
#-----------------------------------------------------------------------
set_power \
-reset
#-----------------------------------------------------------------------
# define switching activity for primary inputs/nets/clocks if they are not
# defined thru user attribute, TCF, VCD or clock constraints. Remember, Voltus
# will use the SDCs but that only controls clocks and registers. SDCs do not
# say how often clock gates toggle.
#-----------------------------------------------------------------------
set_switching_activity \
-reset
set_default_switching_activity \
-input_activity 0.3 \
-period 4.0 \
-clock_gates_output_ratio 0.5
#-----------------------------------------------------------------------
# define output directory
#-----------------------------------------------------------------------
set_power_output_dir pwrOut
#-----------------------------------------------------------------------
# run power analysis
#-----------------------------------------------------------------------
Voltus ESD: RAK
report_power \
-outfile static.rpt
#-----------------------------------------------------------------------
# Static Rail Analysis
#-----------------------------------------------------------------------
set_rail_analysis_mode \
-method static \
-accuracy xd \
-analysis_view av_max1 \
-power_grid_library { \
../pgv/techonly/pgv_tech/techonly.cl \
../pgv/stdcell/pgv_stdcell/stdcells.cl \
../pgv/macro/pgv_macro/macros_PADDB.cl
../pgv/macro/pgv_macro/macros_padIORINGCORNER.cl
../pgv/macro/pgv_macro/macros_PADVDD.cl
../pgv/macro/pgv_macro/macros_PADVDDIOR.cl
../pgv/macro/pgv_macro/macros_PADVSS.cl
../pgv/macro/pgv_macro/macros_PADVSSIOR.cl
}\
-use_em_view_list ../rak_collaterals/em_list.txt \
-enable_rlrp_analysis true \
-verbosity true \
-temperature 125 \
-power_switch_eco false \
-vsrc_search_distance 75 \
-ignore_shorts false \
-enable_manufacturing_effects false \
-report_via_current_direction false \
-force_library_merging true
#-----------------------------------------------------------------------
# define voltage source location
#-----------------------------------------------------------------------
set_power_pads \
-reset
set_power_pads \
-net VDD\
-format xy \
-file ../rak_collaterals/vddr.pp
set_power_pads \
-net VDDB\
-format xy \
-file ../rak_collaterals/vddb.pp
set_power_pads \
-net VDDL\
-format xy \
-file ../rak_collaterals/vddl.pp
set_power_pads \
-net VDDT\
-format xy \
-file ../rak_collaterals/vddt.pp
set_power_pads \
-net VSS\
Voltus ESD: RAK
-format xy \
-file ../rak_collaterals/vssr.pp
set_power_pads \
-net VSSB\
-format xy \
-file ../rak_collaterals/vssb.pp
set_power_pads \
-net VSSL\
-format xy \
-file ../rak_collaterals/vssl.pp
set_power_pads \
-net VSST\
-format xy \
-file ../rak_collaterals/vsst.pp
set_power_pads \
-net VDDIO\
-format xy \
-file ../rak_collaterals/vddio.pp
set_power_pads \
-net VSSIO\
-format xy \
-file ../rak_collaterals/vssio.pp
#-----------------------------------------------------------------------
# define power consumption
#-----------------------------------------------------------------------
set_power_data -reset
set_power_data \
-format current \
{\
pwrOut/static_VDD.ptiavg \
pwrOut/static_VSS.ptiavg \
}
analyze_rail \
-results_directory ./railOut \
-type domain \
domain_vddr
read_power_rail_results -rail_directory railOut/domain_vddr_125C_avg_1 -power_db pwrOut/staticPower.db
analyze_esd -pwr_net VDD -gnd_net VSS -esd_cell_list {PADVDDIOR PADVSSIOR PADVDD PADVSS PADDB} -
output_dir esdOut -use_power_pad true -report_clamp2clamp_resistance true -threshold 0.02 -display
start_gui
#---------------------END----------------------------------------------
Run
Change the directory to Lab2 and the source to run.csh. After the run ends, check the
reports, grid irdrop, and so on. Check the esdcheck.rpt file for clamp-to-clamp R.

Voltus ESD: RAK
LAB3 (Standalone clamp-to-clamp run)

This is a standalone clamp-to-clamp run.
Script
#
# LAB3: clamp to clamp R standalone run
#
#
#
#
Common setup same as Lab2 and the following command.
analyze_esd \
-pwr_net VDD \
-gnd_net VSS \
-esd_cell_list {PADVDDIOR PADVSSIOR PADVDD PADVSS PADDB} \
-output_dir esdOut \
-use_power_pad true \
-report_clamp2clamp_resistance true
start_gui
Run
esdcheck.rpt file for clamp-to-clamp R.

Voltus ESD: RAK
LAB4 (Multistage testing not available)

Multistage R tests are a special feature not available now.
Script
Common setup is same as Lab2 with the following command:
analyze_esd \
-pwr_net VDD \
-gnd_net VSS \
-report_node_location true \
-report_multistage_resistance true
Run
esdcheck.rpt file for multistage R reporting.

Voltus ESD: RAK
Lab5 (Bump-to-clamp and node run)

This is bump-to-clamp and node location report run.
Script
#
# LAB5: bump to clamp and node location run
#
#
#
#
Common setup same as Lab2 with the following command.
analyze_esd \
-pwr_net VDD \
-gnd_net VSS \
-report_node_location true \
-method bump_to_esd_loop_resistance
Run
esdcheck.rpt file for node location and bump-to-clamp R reporting in the
loop_VDD_VSS.rpt file.

Voltus ESD: RAK
Summary
This RAK presented five labs showing how to create ESD-friendly PGVs and run the
various Voltus ESD tests on a 32-pad pad-limited chip. Further enhances to this RAK
will be incorporated as and when required.
Support
Cadence Online Support provides access to support resources, including an extensive
knowledge base, access to software updates for Cadence products, and the ability to
interact with Cadence Customer Support. Visit https://support.cadence.com.
Feedback
Email comments, questions, and suggestions to content_feedback@cadence.com.


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Electrostatic Discharge (ESD) Analysis

Using Voltus IC Integrity: Rapid

Product Version Voltus 17.1 (SSV17.1)

 This pdf can be searched with the RAK ‘Title’ on https://support.cadence.com

Learn more at Cadence Online Support - https://support.cadence.com

Learn more at Cadence Online Support - https://support.cadence.com

Learn more at Cadence Online Support - https://support.cadence.com

Learn more at Cadence Online Support - https://support.cadence.com

Figure 1. Schematic of 16 IOs and 16 powerpads plus four corner cells

Learn more at Cadence Online Support - https://support.cadence.com

Learn more at Cadence Online Support - https://support.cadence.com

Figure 3. Pad connections on Figure 4. Close up of vdd

Figure 5. Stdcell power route

Learn more at Cadence Online Support - https://support.cadence.com

Figure 6. Layout for vss pad showing abutment pins

Learn more at Cadence Online Support - https://support.cadence.com

Lab1 (Creating the ESD PGVs)

ESD PGVs for IOpad and PowerCell macros

-power_pins {VDD 0.9 VDD1 0.9 VDD2 0.9 VDDIOR 0.9} \

PGVs for STDCELL

Learn more at Cadence Online Support - https://support.cadence.com

setvar output_directory_name pgv_stdcell

PGV for techonly cells

Learn more at Cadence Online Support - https://support.cadence.com

{FSWNX1 ExtVSS VSS 750 0.5 4.0e-8} \

Learn more at Cadence Online Support - https://support.cadence.com

setExtractRCMode -engine postRoute -specialNet true -coupled true -viaCap true

set_dc_sources {VDDT} -power -voltage 1.33

set_pg_nets -net VSST -voltage 0 -threshold 0.1 -force

set_pg_nets -net VDDIO -voltage 1.33 -threshold 1.1 -force

set_rail_analysis_domain -name domain_vddr -pwrnets {VDD} -gndnets {VSS}

read_power_rail_results -rail_directory railOut/domain_vddr_125C_avg_1 -power_db pwrOut/staticPower.db

Learn more at Cadence Online Support - https://support.cadence.com

LAB3 (Standalone clamp-to-clamp run)

Common setup same as Lab2 and the following command.

Learn more at Cadence Online Support - https://support.cadence.com

LAB4 (Multistage testing not available)

Common setup is same as Lab2 with the following command:

Learn more at Cadence Online Support - https://support.cadence.com

Lab5 (Bump-to-clamp and node run)

Common setup same as Lab2 with the following command.

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