Combinational Circuit Design

using VHDL

Kalpana G. Bhat
Design entry with HDLs
† Similar to computer program
† Describes underlying hardware
† Advantages:
ƒ Widely supported
ƒ Enables portability
ƒ Text based
ƒ Modular implementation possible
ƒ Concurrency, timing, clocking can all be
modeled

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Verilog Vs VHDL
† Modeling capability
† Compilation
† Data types
† Design reusability
† Learning
† High level constructs
† Gate level timing

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System level languages
† Common system level language for
h/w and s/w.
† Enables h/w- s/w co-design and co-
verification
Example:
System C
System Verilog

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Objective

‰ Implement efficient combinational logic

circuits using VHDL
‰ Introduce language constructs through
examples

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VHDL Program Structure

† Entity declaration
„ defines the interface
† Architecture body
„ defines functionality, allows different
implementations

¾ As a set of concurrent assignment statements-

Dataflow
¾ As a set of interconnected components- structure
¾ As a set of sequential statements- behaviour
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Entity-Generic Structure
Syntax:

Entity entity-name is
Port (signal-names :mode signal-type;
signal-names :mode signal-type;
…………….
signal-names :mode signal-type);
End entity-name;
¾ Mode- signal direction
¾ Identifier, reserve words- not case sensetive
¾ Signal_type- built in or user defined
¾ Signal name-

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 Port Modes

A port’s MODE indicates the direction that data is transferred:

Entity
† IN Data goes into the entity only

† OUT Data goes out of the entity only

(and is not used internally)

† INOUT Data is bi-directional (goes into

and out of the entity)

† BUFFER Data that goes out of the entity

and is also fed-back internally

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Architecture-Generic Structure
Syntax:
Architecture architecture_name of entity_name is
declaration part
Begin
statement part
End architecture_name;

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fulladder.vhd
Dataflow model of Fulladder

entity FullAdder is
port (a, b, cin : in bit;
sum, cout : out bit);
end FullAdder;
architecture FullAdder_eqns of FullAdder is
begin
sum <= a xor b xor cin; -- signal assignment
cout <= (a and b) or (a and cin) or (b and cin);
end FullAdder_eqns;
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Concurrent Signal Assignment
Statement
Syntax:
signal_name <= {expression};

Usage:
int1 <= A and not B; int1 <= A and not B;
int2 <= not A and B; z <= int1 or int2;
z <= int1 or int2; int2 <= not A and B;

-- Output changes value whenever any of the signals on the

right change value
-- Textual order has no effect on order of execution
-- Used in dataflow model

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Concurrent Signal Assignment
Statement…
Syntax:
signal_name <= {expression1 [after delay]};

--a half adder with delays

sum <= a xor b after 5 ns;
carry <= a and b after 10 ns;

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Concurrent Signal Assignment
Statement…
--creating a waveform
pulse <= '1', '0' after 10 ns,
'1' after 30 ns,
'0' after 50 ns;

pulse

30ns 50ns
10ns

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Concurrent Signal Assignment
Statement…
--another option
clock <= not clock after period/2;

† Useful while writing test benches

† Every concurrent signal assignment
statement creates a driver for the target
signal.

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Conditional Signal Assignment
† Concurrent signal assignments with more than
one source expression, where one of the source
expressions is chosen by a control condition
Usage:
sum <= a xor b when (c=‘0’) else a xnor b;
x <= a when (s=“000”) else
b when (s=“101”) else
c when (s=“110”) else
d;

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Conditional signal assignment…
when…else…
Syntax:
signal_name <= expression1 when
boolean_condition1 else
expression2 when
boolean_condition2 else
expression3;

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Conditional Signal Assignment…
† Sensitive to all signals and conditions on RHS
† Conditional signal assignment assigns
decreasing priority to the conditions
corresponding to the order they appear in the
statement
† a has highest priority

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Conditional Signal Assignment
† The Conditional Signal Assignment statement is a
concurrent statement which is somewhat similar to
the if..then..else statement in the sequential part of
the VHDL language.

† The statement executes whenever an event occurs

on any signal appearing on the right hand side
(input) of the statement, i.e, in any of the
expressions or boolean_conditions.

† Unlike the Selected Signal Assignment statement,

each condition is tested in sequence (condition1
then condition2 etc.).

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Conditional Signal Assignment…
--an 8-input priority encoder, in7 is highest
priority input

level <= "111" when in7 = '1' else

"110" when in6 = '1' else
"101" when in5 = '1' else
"100" when in4 = '1' else
"011" when in3 = '1' else
"010" when in2 = '1' else
"001" when in1 = '1' else
"000";

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Example
Implementation of 8 to 1
multiplexer Inbus(0)

.
(Using when…else construct) . Outbit
.
.

entity mux8 is Inbus(7)

Port (inbus: in std_logic_vector(7

downto 0); Sel

sel: in integer range 0 to 7;

outbit: out std_logic);
end mux8;

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8 to 1 multiplexer…

architecture Behavioral of mux8 is

begin
outbit<=inbus(0) when sel=0 else
inbus(1) when sel=1 else
inbus(2) when sel=2 else
inbus(3) when sel=3 else
inbus(4) when sel=4 else
inbus(5) when sel=5 else
inbus(6) when sel=6 else
inbus(7) when sel=7 else
‘-';
end Behavioral;
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Selected signal assignment
Usage:
with sel select
x <= a when “111”,
b when “010”,
c when “101”,
d when “100”,
‘-’ when others ;
† allows one of a number of source expressions to be
selected based on a condition
† no input has higher priority than others
† less selection logic than conditional assignment

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Selected signal assignment…
with…select..
Syntax:
with select_expression select
signal_name <= expression1 when choice1,
expression2 when choice2,
expression3 when choice3|choice4,
--multiple alternative choices
expression4 when choice5 to choice7,
--discrete range of choices
expression5 when others;
--covers all possible choices not
mentioned above

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Selected Signal Assignment
† The Selected Signal Assignment statement is a
concurrent statement which is somewhat similar to a
Case statement in the sequential part of the VHDL
language.
† There is no priority associated with any particular
'when' alternative which means that choices must not
overlap and all possible choices for the
select_expression must be included. Otherwise a final
'when others' limb must be included to cover those
choices not elaborated.
† The selected signal assignment statement is useful for
describing multiplexers and arbitrary combinational
logic based on a truth table description.

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Example
--Full adder
entity fulladd is
Port (a,b,cin : in bit;
s,cout : out bit);
end fulladd;
architecture behave of fulladd is
begin
with a&b&cin select
s <= '1' when "010"|"100"|"001"|"111",
'0' when others;
with a&b&cin select
cout <= '1' when "011"|"101"|"110"|"111",
'0' when others;
end behave;
‰ Truth table implementation
‰ Boolean function realization
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Example
Implementation of 8 to 1 multiplexer
(Using with…select construct)
architecture Behavioral of mux8 is
begin
with sel select
outbit<=inbus(0) when 0,
inbus(1) when 1,
inbus(2) when 2,
………..
inbus(7) when 7,
‘-' when others;
end Behavioral;
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 VHDL Statements
‰ Two types of statements
Concurrent
Sequential
‰ Concurrent Statements (means in parallel)
‰ Executed concurrently
‰ Order is not important
‰ concurrent constructs:
‰ Concurrent Signal Assignment
‰ when-else
‰ with-select

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Sequential signal assignment
† Algorithmic description - pure sequential
† Sequential descriptions in the form of
processes
† A process is a series of sequential statements
that must be executed in order
† Processes are concurrent with one another
and with concurrent statements

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Process-Example
-4 bit adder
entity vadd is
port (A, B: in unsigned (3 downto 0);
S: out unsigned (4 downto 0);
end vadd;
architecture behav of vadd is
begin
add: process (A,B)
S <= (‘0’ & A) + (‘0’ & B);
end process add;
end behav;
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Process..
Two forms of VHDL process
• With Sensitivity list
Syntax:
label: process (sensitivity list)
declaration part
begin
statement part
end process label;

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Process…
• Wait statement:
Syntax:
label: process
declaration part
begin
statement part
wait on sensitivity list
end process label;
† It cannot have both sensitivity list and wait statement
† A process never terminates. It is either active or
suspended.

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Variables
† Used for local storage in processes.
† Variable declaration form
variable Variable_names : type_name[:=initial_value];
‰ Variables are updated using a variable assignment
statement of the form
variable_name := expression;
‰ Variables are instantaneously updated with no delay

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Variable assignment
--Full adder using Half adder
and or gate
architecture behav of full_add is
begin
process
variable sum1, sum2,
c1, c2 : bit;
begin
sum1 := a xor b; a sum1 sum2=sum
c1 := a and b;
sum2 := sum1 xor c; b
c2 := sum1 and c c
sum <= sum2; c2 cout
cout <= c1 or c2;
wait on a, b, c;
end process; c1
end behav;
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Using Variables vs. Signals
Process using variables:
Architecture var of pro is
signal trigger, sum: integer:=0;
Begin
Process
Variable var1:integer:=1;
Variable var2:integer:=2;
Variable var3:integer:=3;
Begin
Wait on trigger;
Var1:=var2+var3;
Var2:=var1;
Var3:=var2;
Sum<=var1+var2+var3;
End process;
End var;
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Using Variables vs. Signals
Process using signals:
Architecture sig of pro is
signal trigger, sum: integer:=0;
signal sig1:integer:=1;
signal sig2:integer:=2;
signal sig3:integer:=3;
Begin
Process
begin
Wait on trigger;
Sig1<=sig2+ sig3;
Sig2<=sig1;
Sig3<=sig2;
Sum<=sig1+sig2+sig3;
End process;
End sig;
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Variables and signals
† Variables
• used inside the process
• assignment takes immediate effect
• no driver

‰ Signals
• used to interconnect components and
processes
• new value is assigned to signal when process
suspends
• driver present

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Example-If..elsif..
process(c1, c2, c3, a, b) process (c0, c1, c2, a, b, c, d)
variable v: bit; begin
if c0=‘1’ then
begin
f <= a;
if c1=‘0’ then elsif c1=‘1’ then
v := a; f <= b;
else else
v:= b; f <= d;
end if; end if;
if c2 = ‘1’ and end process;
c3=‘1’ then
v := not v; • Tests each condition in strict
end if; order of priority
f <= v; end process; • Similar to when…else construct
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If…elsif - statement
Syntax:
if condition then
sequential statements
elsif condition then
sequential statements
…
else
sequential statements
end if;

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Example
-8 to 1 multiplexer (If…elsif..)
architecture Behavioral of mux8 is
begin
Process (sel)
begin
if sel=0 then outbit<=inbus(0);
elsif sel=1 then outbit<=inbus(1);
elsif sel=2 then outbit<=inbus(2);
….
elsif sel=6 then outbit<=inbus(6);
elsif sel=7 then outbit<=inbus(7);
else outbit<=‘-';
end if;
end process;
end Behavioral;

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Case statements
Usage:
Process (sel)
begin
case sel is
when “00”| “11” => y <=‘1’;
when “01” => y <= ‘0’;
when others => y <= ‘-’;
end case;
end process;
† no priority
† Simillar to with..select construct

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Case statements
Syntax:
case expression is
when choices=>sequential-statements
when choices=>sequential-statements
when others=>sequential-statements
end case;

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Example
Implementation of 8 to 1 multiplexer
(Using case construct)

architecture Behavioral of mux8 is

begin
Process (sel)
begin
case sel is
when 0 => outbit<=inbus(0);
when 1 => outbit<=inbus(1);
when 2 => outbit<=inbus(2);
when 3 => outbit<=inbus(3);
when 4 => outbit<=inbus(4);

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Example..
when 5 => outbit<=inbus(5);
when 6 => outbit<=inbus(6);
when 7 => outbit<=inbus(7);
when others=>null;
end case;
end process;
end Behavioral;

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Example- for…loop
process (a,b)
variable v: std_logic;
begin
v:=‘0’;
for j in 0 to 3 loop
f(j) <= a(j) and b(3-j); -- repetitive logic
v := v xor a(j) -- iterative logic
end loop;
g <= v;
end process;
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for…loop
Syntax:

[loop_label1:]iteration-scheme loop
sequential-statements
end loop [loop label];

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Example
-8 to 1 mux
entity mux is
Port ( d : in std_logic_vector(7 downto 0);
sel:in integer range 0 to 7;
y : out std_logic);
end mux;
architecture Behavioral of mux is
begin
process(sel)
begin
for i in 0 to 7 loop
if sel=i then
y<=d(i);
end if; end loop; end process; end Behavioral;
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Example
m to 1 mux
entity mux is
Generic (m:natural:=8);
Port ( d : in std_logic_vector(m-1 downto 0);
sel:in integer range 0 to m-1;
y : out std_logic);
end mux;
architecture Behavioral of mux is
begin
process(sel)
begin
for i in 0 to m-1 loop
if sel=i then
y<=d(i);
end if; end loop; end process; end Behavioral;
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while loop
Syntax:
while condition loop
statements;
end loop;

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Assertion statements
--used to check if expected conditions are met within a
model
architecture check of srff is
begin
Process (s,r)
begin
assert s=‘1’ nand r=‘1’; -- asserts if condition is false
report “incorrect usage”
severity failure; -- can be note, warning, error or failure
if s=‘1’ then q<=‘1’; end if;
if r=‘1’ then q<=‘0’; end if;
end process;
end check;
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Assertion Statement …
Syntax:
assert Boolean_condition [ report String_literal ]
[ severity Level ] ;

‰ The statement is typically used to check for timing

violations occurring on inputs to the entity such as a set-
up time, hold time or minimum pulse width requirement.

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Component Instantiation Statement
entity dec2to4 is
port(s0,s1,en : in bit;
y0,y1,y2,y3 : out bit);
end dec2to4;
architecture structural of
dec2to4 is
component inv
port(a : in bit;
b : out bit);
end component;
component and3
port(a1,a2,a3 : in bit;
o1 : out bit);
end component;
signal ns0,ns1 : bit;
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Component Instantiation
Statement…
begin
i1 : inv port map (s0,ns0);
i2 : inv port map (s1,ns1); --
positional association, actuals are
connected by position
a1 : and3 port map(en,ns0,ns1,y0);
a2 : and3 port map(en,s0,ns1,y1);
a3 : and3 port map(en,ns0,s1,y2);
--named association formal =>
actual
a4 : and3 port map(a1 => en, a2 =>
s0, a3 => s1, o1 => y3);
end structural;

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Generate Statement
† The Generate Statement is used to replicate concurrent
statements over a specified range. If the concurrent
statements are component instantiations, then this
creates an array of components.
† This is very useful for creating regular structures like
shift registers, memory circuits and ripple carry adders.
† The label is compulsory with a generate statement.
† The statement may be nested to create two dimensional
arrays of components.
† The if.. generate statement is often used within a
generate structure to account for irregularities

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for.. and if…generate
Syntax:
label : for parameter in range generate
concurrent_statements
label : if condition generate
concurrent_statements
end generate label;
end generate label;

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Implementation of 8 to 1 mux
(using generate ..construct)

4 to 1

Inbus(3:0)
2 to 1

Sel(1:0) x(1) Outbit

Inbus(4:7)
x(0) Sel(2)

4 to 1

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(Code for 4 to 1 multiplexer which is used as a component
for 8 to 1 multiplexer.)

entity mux4 is
port(inbus:in std_logic_vector(3 downto 0);
sel:in std_logic_vector(1 downto 0);
outbit:out std_logic);
end mux4;
architecture Behavioral of mux4 is
begin
outbit<=inbus(0) when sel="00" else
inbus(1) when sel="01" else
inbus(2) when sel="10" else
inbus(3) when sel="11" else
‘-';
end Behavioral;

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(Code for 2 to 1 multiplexer which is used as a component
for 8 to 1 multiplexer.)

entity mux2 is
port(a:in std_logic_vector(1 downto 0);
sel:in std_logic;
y:out std_logic);
end mux2;
architecture Behavioral of mux2 is
begin
with sel select
y<=a(0) when '0',
a(1) when '1',
‘-' when others;
end Behavioral;
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(Code for 8:1 multiplexer using 4 to 1 and 2 to 1
multiplexers as component.)

entity mux8 is
port(inbus:in std_logic_vector(7 downto 0);
sel:in std_logic_vector(2 downto 0);
outbit:out std_logic);
end mux8;
architecture Behavioral of mux8 is
component mux4 is …….
end component;
component mux2 is……
end component;
signal x:std_logic_vector(1 downto 0);

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(Code for 8:1 multiplexer using 4 to 1 and 2 to 1
multiplexers as component.)….

begin
4 to 1
g1:for i in 0 to 1 generate
m1:mux4 port map
Inbus(3:0)
(inbus((4*i+3) downto
2 to 1
(4*i)),sel(1 downto 0),x(i));
end generate;
m2:mux2to1 port map Sel(1:0) x(1) Outbit
(x(1 downto 0),sel(2),outbit);
end Behavioral;
Inbus(4:7)
x(0) Sel(2)

4 to 1

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Summary
† VHDL gives the designer many different ways
to describe hardware
† Behavioral descriptions in VHDL may be
expressed in sequential or concurrent form
† Sequential behavior is modeled using a single
VHDL process
† VHDL processes are composed of the same sort
of statements and control constructs found in
HLLs
† Concurrent behavior is modeled using multiple
VHDL processes and/or multiple concurrent
signal assignment statements

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References
† Bhaskar,J. VHDL Primer,Prentice Hall.
† Jhon.F.Wakerly, Digital Design,Prentice Hall.
† Peter.J.Ashenden, The designer’s guide to VHDL.,Morgan
Kaufmann
† Charles H Roth, Jr. Digital systems design using VHDL

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