Beruflich Dokumente
Kultur Dokumente
Sequental Circuits
1
Digital Circuits
CC W
Y
Storage
elements
R
Q
Q
S
NOR SR Latch (Set-Reset Latch)
R
0 Q
1 Q
S
NOR SR Latch (Set-Reset Latch)
R 1
0 0 Q
1 Q
S 0
NOR SR Latch (Set-Reset Latch)
R 1
0 0 Q
Q 1; Q 0 Set State
1
Q 0; Q 1 Re set State
Q
S 0
NOR SR Latch (Set-Reset Latch)
R 1
0 0 Q
Q 1; Q 0 Set State
1
Q 0; Q 1 Re set State
Q
S 0
S R Q Q State
1 0 1 0 SET
NOR SR Latch
Reset
R 0 Q
1 Q 1; Q 0 Set State
1
Q 0; Q 1 Re set State
0 Q
S 0
Set
S R Q Q State
1 0 1 0 SET
0 1 0 1 RESET
HOLD State
S R Q Q State
R 1 1
Q 1 0 1 0 SET
0
0 0 1 0 HOLD
0 1 0 1 RESET
Q
S 0 0 0 0 0 0 1 HOLD
HOLD State
S R Q Q State
R 1 1
Q 1 0 1 0 SET
0
0 0 1 0 HOLD
0 1 0 1 RESET
Q
S 0 0 0 0 0 0 1 HOLD
S R Q Q State
1 0 1 0 SET
0 1 0 1 RESET
0 0 Q Q HOLD 1 bit memory?
HOLD State
S R Q Q State
R 1 1
Q 1 0 1 0 SET
0
0 0 1 0 HOLD
0 1 0 1 RESET
Q
S 0 0 0 0 0 0 1 HOLD
S R Q Q State
1 0 1 0 SET
0 1 0 1 RESET
0 0 Q Q HOLD 1 bit memory?
1 1 0 0 INVALID
R 0 Q
1
A more serious problem occurs when we switch the latch to the hold state by
changing RS from 11 00 . Suppose the inputs do not change
simultaneously and we get the situation 11 01* 00
1 0 1 0
R 0 Q
R
Q
R 1 Q
Q 0 Q 0 Q
S 1 S 1 S 0
0
Q=1
1 0 1 0
R 0 Q
R R 1 Q
Q
0 0 Q
1 Q 1 Q S 0
S 0 S
Q=1
1 0 1 0
R 0 Q
R R 1 Q
Q
0 0 Q
1 Q 1 Q S 0
S 0 S
Q=1
0 0 Q
1 Q 1 Q S 0
S 0 S
Q=1
1 1 0 0
R 0 Q
R
Q
R 0 Q
Q 1 Q 1 Q
S 1 S 0 S 0
0
Q=0
1 0 1 0
R 0 Q
R R 1 Q
Q
0 0 Q
1 Q 1 Q S 0
S 0 S
Q=1
1 1 0 0
R 0 Q
R
Q
R 0 Q
Q 1 Q 1 Q
S 1 S 0 S 0
0
Q=0
So although output is well defined when we apply RS = 11, it becomes
unpredictable once we switch the latch to hold state by applying RS = 00. That
is why RS = 11 is not used as an input combination.
NAND Latch
S
Q
Q
R
S R Q Q State
0 1 1 0 SET
1 0 0 1 RESET
1 1 Q Q HOLD
0 0 1 1 INVALID
RS NAND Latch with Enable
S
1
Q
EN Hold State
0
1 Q
R
Enable S R Q Q State
S S
0 x x Q Q Hold
Q
1 1 0 1 0 Set
EN 0 1 0 1 Reset
1
1 Q 1 0 0 Q Q Hold
R 1 1 0 0 Invalid
R 1
D latch
S Q D 1 1 S Q 1
EN 1 EN
R Q R Q 0
0
D latch
S Q D 1 1 S Q 1
EN 1 EN
R Q R Q 0
0
Enable S R Q Q State
0 x x Q Q Hold D Q
1 1 0 1 0 Set
1 0 1 0 1 Reset EN Q
1 0 0 Q Q Hold
1 1 1 0 0 Invalid
D latch
S Q D 1 1 S Q 1
EN 1 EN
R Q R Q 0
0
Enable S R Q Q State
0 x x Q Q Hold D Q
1 1 0 1 0 Set
1 0 1 0 1 Reset EN Q
1 0 0 Q Q Hold
1 1 1 0 0 Invalid
D Q
clk
Clock
D Q
clk
Clock
D
Master-Slave D Flip-flop
D D D Q
master slave
EN EN Q
clk
Clock
Master
Slave
Major Quiz 3 Solution Discussion