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// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
input [12:0] gpio_bd_i,

output [ 7:0] gpio_bd_o,
inout iic_scl,
inout iic_sda,
input ref_clk0_p,
input ref_clk0_n,
input ref_clk1_p,
input ref_clk1_n,
input [ 3:0] rx_data_p,
input [ 3:0] rx_data_n,
output [ 3:0] tx_data_p,
output [ 3:0] tx_data_n,
output rx_sync_p,
output rx_sync_n,
output rx_os_sync_p,
output rx_os_sync_n,
input tx_sync_p,
input tx_sync_n,
input sysref_p,
input sysref_n,
output spi_csn_ad9528,
output spi_csn_ad9371,
output spi_clk,
output spi_mosi,
input spi_miso,
inout ad9528_reset_b,
inout ad9528_sysref_req,
inout ad9371_tx1_enable,
inout ad9371_tx2_enable,
inout ad9371_rx1_enable,
inout ad9371_rx2_enable,
inout ad9371_test,
inout ad9371_reset_b,
inout ad9371_gpint,
// internal signals
wire [94:0] gpio_i;

wire [94:0] gpio_o;
wire [94:0] gpio_t;
wire [20:0] gpio_bd;
wire [ 2:0] spi_csn;
wire ref_clk0;
wire ref_clk1;
wire rx_sync;
wire rx_os_sync;
wire tx_sync;
wire sysref;
wire rx_sync_vio;
wire rx_os_sync_vio;
wire tx_sync_vio;
wire ad9528_reset_b_vio;
wire [15:0] rx_I0;

wire [15:0] rx_I1;
wire [15:0] rx_Q0;
wire [15:0] rx_Q1;
wire [31:0] tx_I0;
wire [31:0] tx_I1;
wire [31:0] tx_Q0;
wire [31:0] tx_Q1;
wire [31:0] rx_FB_I0;
wire [31:0] rx_FB_Q0;
wire rx_clk;
wire tx_clk;
wire rx_FB_clk;
// instantiations
IBUFDS_GTE4 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (ref_clk0_p),
.IB (ref_clk0_n),
.O (ref_clk0),
.ODIV2 ());
IBUFDS_GTE4 i_ibufds_ref_clk1 (
.CEB (1'd0),
.I (ref_clk1_p),
.IB (ref_clk1_n),
.O (ref_clk1),
.ODIV2 ());
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
OBUFDS i_obufds_rx_os_sync (
.I (rx_os_sync),
.O (rx_os_sync_p),
.OB (rx_os_sync_n));
IBUFDS i_ibufds_tx_sync (
.I (tx_sync_p),
.IB (tx_sync_n),
.O (tx_sync));
assign gpio_bd_o = gpio_bd[ 7:0];

assign spi_csn_ad9528 = spi_csn[1];
assign spi_csn_ad9371 = spi_csn[0];
system_wrapper i_system_wrapper (
.dac_fifo_bypass (gpio_o[60]),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.ps_intr_00 (1'd0),
.ps_intr_01 (1'd0),
.ps_intr_02 (1'd0),
.ps_intr_03 (1'd0),
.ps_intr_04 (1'd0),
.ps_intr_05 (1'd0),
.ps_intr_06 (1'd0),
.ps_intr_07 (1'd0),
.ps_intr_14 (1'd0),
.ps_intr_15 (1'd0),
.rx_FB_I0(rx_FB_I0),
.rx_FB_Q0(rx_FB_Q0),
.rx_FB_clk(rx_FB_clk),
.rx_I0(rx_I0),
.rx_I1(rx_I1),
.rx_Q0(rx_Q0),
.rx_Q1(rx_Q1),
.rx_clk(rx_clk),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_ref_clk_0 (ref_clk1),
.rx_ref_clk_2 (ref_clk1),
.rx_sync_0 (rx_sync),
.rx_sync_2 (rx_os_sync),
.rx_sysref_0 (sysref),
.rx_sysref_2 (sysref),
.spi0_sclk (spi_clk),
.spi0_csn (spi_csn),
.spi0_miso (spi_miso),
.spi0_mosi (spi_mosi),
.spi1_sclk (),
.spi1_csn (),
.spi1_miso (1'b0),
.spi1_mosi (),
.tx_I0(tx_I0),
.tx_I1(tx_I1),
.tx_Q0(tx_Q0),
.tx_Q1(tx_Q1),
.tx_clk(tx_clk),
.tx_data_0_n (tx_data_n[0]),
.tx_data_0_p (tx_data_p[0]),
.tx_ref_clk_0 (ref_clk1),
.tx_sync_0 (tx_sync),
.tx_sysref_0 (sysref));
ila_0_rx_data RX_DATA (
.clk(rx_clk), // input wire clk
.probe0(rx_I0), // input wire [15:0] probe0
.probe1(rx_Q0), // input wire [15:0] probe1
.probe2(rx_I1), // input wire [15:0] probe2
.probe3(rx_Q1) // input wire [15:0] probe3
);
ila_0_tx_data TX_DATA (
.clk(tx_clk), // input wire clk
.probe0(tx_I0), // input wire [15:0] probe0
.probe1(tx_Q0), // input wire [15:0] probe1
.probe2(tx_I1), // input wire [15:0] probe2
.probe3(tx_Q1) // input wire [15:0] probe33
);
ila_0_FB_data your_instance_name (
.clk(rx_FB_clk),
.probe0(rx_FB_I0), // input wire [31:0] probe0
.probe1(rx_FB_Q0) // input wire [31:0] probe1
);
assign ad9528_reset_b_vio=ad9528_reset_b;
assign tx_sync_vio=tx_sync;
assign rx_sync_vio=rx_sync;
assign rx_os_sync_vio=rx_os_sync;
vio_0_status status (
.clk(rx_clk), // input wire clk
.probe_in0(ad9528_reset_b_vio), // input wire [0 : 0] probe_in0
.probe_in1(ad9528_sysref_req), // input wire [0 : 0] probe_in1
.probe_in2(ad9371_tx1_enable), // input wire [0 : 0] probe_in2
.probe_in3(ad9371_tx2_enable), // input wire [0 : 0] probe_in3
.probe_in4(ad9371_rx1_enable), // input wire [0 : 0] probe_in4
.probe_in5(ad9371_rx2_enable), // input wire [0 : 0] probe_in5
.probe_in6(ad9371_test), // input wire [0 : 0] probe_in6
.probe_in7(ad9371_reset_b), // input wire [0 : 0] probe_in7
.probe_in8(ad9371_gpint), // input wire [0 : 0] probe_in8
.probe_in9(ad9371_gpio_00), // input wire [0 : 0] probe_in9
.probe_in28(tx_sync_vio), // input wire [0 : 0] probe_in28
.probe_in29(rx_sync_vio), // input wire [0 : 0] probe_in29
.probe_in30(rx_os_sync_vio) // output wire [0 : 0] probe_out0
);
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************

input [12:0] gpio_bd_i,

wire [94:0] gpio_i;

wire [15:0] rx_I0;

assign gpio_bd_o = gpio_bd[ 7:0];

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