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AI is 0.7, what is the minimum thickness of the deposited dielectric ? (10 pts)
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IC Technology II – Mid-term Examination
Part-II Close Book
2011.04.26 16:40 – 17:30
A. True or False (20 pts)
1. The ratio of the number of atoms that actually stay or “stick” on the surface relative to the number of
incident atoms. (PVD-5)
2. One of the drawbacks of the evaporation method is difficult to deposit alloys, compounds, and low
vapor pressure materials. (PVD-19)
3. For ionized sputtering process, lower substarte bias results in better step coverage. (PVD-50)
4. Overpotential is the potential required to overcome hindrance of the overall electrode reaction. (ECD-
25)
5. In Cu ECD process, the Leveler is larger than the brightener and is more easier to be adsorbed at upper
parts of the structure to inhibit deposition. The Cu growth rate on protruded surface is thus suppressed.
(ECD-45)
6. If the doping concentration is lower than the intrinsic carrier concentration at the diffusion temperature,
electric fields set up near the front of the diffusion profile. In this case, dopant diffusion would be
enhanced by the electric field. (Diffusion-12)
7. Channeling occurs when incident ions align with a major crystallographic direction and are guided
between rows of atoms in a crystal. An amouphous capping can suppress the channeling effect.
(Implant-15)
8. Reverse annealing, i.e. activation level decreases with the increase of annealing temperature, may occur
on the Boron implanted sample. This phenomenon does not observed on the Phosphorus implanted
sample. (Implant-23)
9. Polishing at a pH value close to the IEP of the abrasive, no ionic double layer forms at the particle
surface, results in a maximum hardness of the particle surface and a high polishing rate. (CMP-33)
10. SiO2 erosion is defined as the difference in the SiO 2 thickness before and after the polish step, resulting
because the polish rate of SiO2 is non-zero during the over polish step. (CMP-51)