Beruflich Dokumente
Kultur Dokumente
14Aug’01
Presented by K. W. Chew
1. Introduction
2. Deep Nwell Process Overview
3. Substrate Coupling Test Structures
4. S21 Isolation
5. Effect on RF Transistor Performance
6. Conclusions
Introduction
Source : IEEE Journal of Solid-State Circuits, Vol. 33, No. 3, pp. 314-323, Mar. 1998
Deep N-well Process Overview
STI formation
N-well formation
P-well formation
Channel implants
Co salicidation
BEOL
Deep N-well Process Overview
Deep n-Well
p-substrate
N+
with P+ P+ P+ P+
DNW
DNW
N+
N+ P+ P+ P+ P+
GR
GR
* The authors would like to acknowledge Institute of Microelectronics (Singapore) VLSI department for the test structure layouts
Diode-Type Substrate Coupling Structure in
Deep N-well
GR N P G P N GR S
Deep n-Well
p-substrate
Effect of Different Body Biasing Techniques on RF
Isolation for P+ Noise Generators
-30
G to S spacing : 280µ m
-35 DNW Implant : P1E13/900KeV
-40
-45
-50
S21 Isolation (dB)
-55
-60
-65
-70
-75
-30
-40
-45
S21 Isolation (dB)
-50
-55
-60
-65
-80
0.1 1 10
Frequency (GHz)
Effect of Different Body Biasing Techniques on RF
Isolation for N+ Noise Generators
-10
G to S spacing : 50µ m
DNW Implant : P2E13/900KeV
-20
-30
S21 Isolation (dB)
-40
-50
-60
-30
G to S spacing : 280µ m
-35
-40
S21 Isolation (dB)
-45
-50
-55
-70
0.1 1 10
Frequency (GHz)
Thin-Gate Oxide MOSFETs in Deep N-well
DC Characteristics
1.00E-07 4.0E-04
Ids (A/um)
Ids (A/um)
3.0E-04
1.00E-09
2.0E-04
P-std P-DW
1.00E-11
N-std N-DW 1.0E-04
1.00E-13 0.0E+00
-1.8 -1.2 -0.6 0 0.6 1.2 1.8 -1.8 -1.3 -0.8 -0.3 0.2 0.7 1.2 1.7
Vds (V)
Vg (V)
Thick-Gate Oxide MOSFETs in Deep N-well
DC Characteristics
Ids (A/um)
3.0E-04
1.00E-10
2.0E-04
P-std P-DW
1.00E-12
N-std N-DW 1.0E-04
1.00E-14
0.0E+00
-3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5
0.14
0.12
C gg
Capacitances (pF)
0.10
NMOSFET
Lgate = 0.25 µ m
0.08
W finger = 9.58 µ m
Nfinger = 8
0.06
Vds = 2.5V
Vgs = 1.0V C gb
0.04
C gd
Frequency (GHz)
Effect of Deep Nwell on the RF Transistor AC
Characteristics Extracted from CV Measurements
70
NMOSFET
Lgate = 0.25 µ m f max
60
Wfinger = 9.58 µ m
Nfinger = 8
50
Vds = 2.5V ft
Frequency (GHz)
40 w/o DNW
w DNW
30
20
10
0
1.0E-02 1.0E-01 1.0E+00
2.5 2.5
Triode Saturation
2.0 2.0
NFmin (dB)
NFmin (dB)
1.5 NMOS Transistor 1.5
NMOS Transistor
Lf=0.18µm Lf=0.18µm
Wf=5µm Wf=5µm
1.0 Nf=16
1.0 Nf=16
Vgs=1.2V Vgs=1.8V
Vds=0.6V Vds=1.8V
0.0 0.0
1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0
Frequency (GHz) Frequency (GHz)
Comparison of RF Transistor 1/f Noise
Characteristics with and without Deep N-well
1.00E-12
1E-12
with DNW
1.00E-14
SId (A2/Hz)
1E-14
SId (A2/Hz)
1.00E-15
NMOS Transistors 1E-15
NMOS Transistors
Lgate = 0.18µm
Lgate = 0.18µm
Nfinger = 16
1.00E-16 Nfinger = 16
Lfinger = 5µm 1E-16
Lfinger = 5µm
Vds = 0.7V
Vds = 1.8V
Vgs = 1.8V
Vgs = 0.9V
1.00E-17
1E-17
1 10 100 1000 10000
1 10 100 1000 10000
Frequency (Hz) Frequency (Hz)
Triode Saturation
Vertical NPN Bipolar from the 0.18 µm Deep N-well
Technology
1.0E+00
6 1.0E-01 (2)
Ib=50uA Ib=100uA 1.0E-02
5 Ib=150uA Ib=200uA 1.0E-03
Ib=250uA Ib=300uA (1)
1.0E-04
• VA = 22V
3 • BVCEO = 6V 1.0E-06
1.0E-07
• BVCBO = 17V 1.0E-08
2
1.0E-09
1 1.0E-10
1.0E-11
0
1.0E-12
0 1 2 3 4 5
1.0E-13
Vc (V)
0.0 -0.5 -1.0 -1.5 -2.0
20
Veb (V)
18
16
14
12
10
N+
β
4
P+
2
N+
0
1.0E-12 1.0E-10 1.0E-08 1.0E-06 1.0E-04 1.0E-02 1.0E+00
AE : 5X5 µm2
Ic (A)
Conclusions