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Session 302


Introduction Digital Design with SM Charts

Design of Networks for Arithmetic Operations
This paper describes how we use VHDL in teaching Programmable Gate Arrays
a senior course in digital systems design. The Floating Point Arithmetic
acronym VHDL stands for VHSIC Hardware Additional VHDL Topics
Description Language, and VHSIC in turn stands for Interfacing Memory to Busses
Very High Speed Integrated Circuit. VHDL is a Testing Digital Systems and Design for Testability
general-purpose language which can be used to
describe and simulate the operation of a wide variety Since VHDL is a very complex language, it could
of digital systems ranging in complexity from a few easily get in the way of learning digital system
gates to an interconnection of many complex design principles if care is not taken. Our objective
integrated circuits. VHDL was originally developed is not to make students VHDL experts, but rather to
for the military to allow a uniform method for teach them how VHDL can facilitate the digital
specifying digital systems. VHDL has since become design process. We introduce VHDL early in the
an IEEE standard [l] and it is becoming widely- course and then teach additional parts of VHDL on
used in industry in the United States as well as in an as needed basis.
Although there are several textbooks available on
VHDL allows students to describe a digital system at VHDL [2,3,4,5], these texts emphasize learning
a behavioral level, a logic equation level, and as an VHDL rather than learning digital system design.
interconnection of components. For example, a We are developing our own text which teaches
binary adder could be described at the behavioral VHDL as a part of the digital system design process.
level in terms of its function of adding two binary Each time we introduce a new concept, we also show
numbers, without giving any implementation details. how to implement it in VHDL. For example, after
The same adder could be described at the data flow introducing SM (sequential machine) charts, we
level by giving the logic equations for the adder. show how to go from an SM chart to a VHDL
Finally, the adder could be described at the description.
structural level by specifying the interconnections of
the gates which comprise the adder. We use a VHDL simulator throughout the course.
Because we use PCs in our lab rather than
VHDL is ideal for teaching top-down design workstations, our choice of VHDL simulators was
methodology. The system can first be specified at a somewhat limited. We chose the V-System VHDL
high level and then tested using a simulator. After compiler/simulator from Model Technology [6]
the system is debugged at this level, the design can because it fully implements IEEE standard VHDL
gradually be refined, eventually leading to a and it has a very friendly user interface. We pay
structural description which is closely related to the careful attention to timing analysis in the course,
actual hardware implementation. and we relate the waveforms generated by the
VHDL simulator to the actual circuit timing.
Course Description We also use other CAD software in the course to
We first introduce VHDL in a senior digital design implement designs using XILINX field program-
course. This course requires a basic course in logic mable gate arrays (FPGAs) 171. In particular, we use
design as a prerequisite. The senior course includes Viewlogic software for schematic capture and
the following topics: simulation, and then we use the XILlNX XACT
Review of Logic Design Fundamentals software to partition, place and route the design for
Introduction to VHDL implementation using an FPGA.
Programmable Logic Devices
1 1994 Frontiers in Education Conference E
Introductory VHDL Example
-- T h i s is a b e h a v i o r a l model of a Mealy
In this section, we will show three different VHDL -- s t a t e m a c h i n e based on i t s Table 1.
models for the Mealy sequential machine specified -- The o u t p u t (2) a n d n e x t
by Table 1. The behavioral description (Figure 2) -- s t a t e a r e c o m p u t e d b e f o r e t h e active e d g e
directly implements the state table. Just as the
-- of t h e c l o c k . The s t a t e c h a n g e o c c u r s on
-- t h e r i s i n g e d g e of t h e c l o c k .
general model of a Mealy sequential network
e n t i t y SM1-2 i s
consists of a combinational network and a state p o r t ( ) ( , CLK: i n b i t ;
register (see Figure l), our VHDL model has two 2: o u t b i t ) ;
processes, one to model the combinational network e n d SM1-2;
and one to model the state register. The first
process computes the next state and the network a r c h i t e c t u r e T a b l e of SM1-2 i s
s i g n a l S t a t e , N e x t s t a t e : i n t e g e r := 0;
output (2)and the second process updates the state begin
register on the rising edge of the clock. By using p r o c e s s ( S t a t e , X ) - - C o m b i n a t i o n a l Network
this modeling technique, the simuliator can generate begin
meaningful timing diagrams (see Figure 5 ) from the case S t a t e is
behavioral model. when 0 =>
i f X='O' t h e n
After making a state assignment and deriving the Z<='1'; N e x t s t a t e < = l ; e n d i f ;
next state equations, we can derive the VHDL i f X='l' then
description shown in Figure 3. This description uses Z<='O'; N e x t s t a t e < = 2 ; e n d i f ;
the same entity declaration as before, but the when 1 =>
i f X='O' then
architecture is different. After completing the logic Z<='1'; N e x t s t a t e < = 3 ; e n d i f ;
design using NAND gates and D flip-flops, we can i f X='l' t h e n
write a VHDL description which shows the Z<=='O'; N e x t s t a t e < - 4 ; e n d i f ;
interconnections between the gates and flip-flops when 2 a>
(Figure 4). Models for the gates and flip-flops are i f X='O' t h e n
contained in a library named BITLIB. Figure 6 Z<='O'; N e x t s t a t e < = 4 ; e n d i f ;
shows the timing diagram generated from this i f X='l' then
description. Z<='1': N e x t s t a t e < = 4 ; e n d i f ;
when 3 =>
Table 1 i f X='O' t h e n
Z<='O'; N e x t s t a t e < = 5 ; e n d i f ;
if X='l' t h e n
NS z Z<='l'; N e x t s t a t e < = 5 ; e n d i f ;

x=o X = l
s1 s2
when 4 =>
i f X-'O' t h e n
Z<='l' : N e x t s t a t e < = S ; e n d i f ;
s1 s3 s4 1 0 if X = ' l ' t h e n
s2 s4 s4 0 1 Z<='O'; N e x t s t a t e < = 6 ; e n d i f ;
when 5 =>
s3 s5 s5 0 1
i f X='O' t h e n
s4 S5 S6 1 0
S5 so so 0 1 Z<='O'; N e x t s t a t e < = O ; e n d i f ;
S6 so - 1 - i f x='l' t h e n
Z<=' 1 : N e x t s t a t e < = O : e n d i f :
when 6 =>
i f X='O' t h e n
Z<='l'; N e x t s t a t e < = O ; e n d i f ;
n when o t h e r s => n u l l : --should n o t o c c u r
e n d case;
end p r o c e s s ;
p r o c e s s (CLK) --State Register
i f CLK='l' t h e n - - r i s i n g e d g e of c l o c k
S t a t e <= N e x t s t a t e ;
end i f ;
end process;

Figure 1 . Mealy sequential network Figure 2. Behavioral model for Table 1

': 1994 Frontiers in Education Conference
-- The f o l l o w i n g i s a d e s c r i p t i o n of t h e Final Design Pro~ect
-- s e q u e n t i a l m a c h i n e of Table1 i n terms
-- of i t s n e x t s t a t e e q u a t i o n s . The s t a t e Students do a final design project which integrates
-- assignment follows:
-- SO-->O; S1-->4; S2-->5; S3-->7; many of the concepts taught in the course. They
-- S4-->6; S5-->3; S6-->2 carry out the following steps in their final design
e n t i t y SM1-2 i s
port(X,CLK: i n b i t ;
(1) Develop a high level design consisting of a
2: out bit);
block diagram and an SM chart.
e n d SM1-2; (2) Write a behavioral level VHDL description,
simulate, test and debug it.
a r c h i t e c t u r e E q u a t i o n s of SM1-2 is
s i g n a l Ql,Q2,Q3: b i t ;
(3) Complete the logic design using appropriate
process (CLK) (4) Enter the logic schematic diagram using
begin Viewdraw; simulate, test and debug it using
i f CLK-'l' then Viewsim.
Ql<=not 42 after 10 ns; (5) Partition, place and route the design for FPGA
Q2<=Q1 a f t e r 1 0 n s ; imDlementation using- the XACT software from
Q3<=(Q1 a n d Q2 a n d Q3) o r ( ( n o t X ) a n d Q1 XILINX.
and (not 43)) o r (6) Download the final design to a FPGA and test it.
( X and ( n o t Q1) a n d ( n o t 43))
a f t e r 1 0 ns; Final design projects were chosen so that they will fit
end i f ;
e n d process;
into a single X3020 FPGA, which has 64 logic cells.
Z<=( ( n o t X ) and ( n o t Q 3 ) ) or ( X and Q3)
Examples of final projects are a bowling score
a f t e r 2 0 ns; computer, a 4-bit floating point adder or subtracter,
and an arithmetic-logic unit. Since the design has
been tested at steps (2) and (4), it is very likely that
Figure 3. Sequential machine model the design will work the first time it is downloaded.
using equations
Advantages and Disadvantages of
-- The f o l l o w i n g i s a STRUCTURAL VHDL Using VHDL
-- model of a s e q u e n t i a l n e t w o r k .
We previously used a hardware description language
l i b r a r y BITLIB; called DSDL (Digital System Design Language) [SI
use BITLIB.bitgack.al1; in the course. Use of VHDL offers several
e n t i t y SM1-2 i s advantages over DSDL. First, students learn an
port(X,CLK: i n b i t : industry-standard hardware description language.
2: o u t b i t ) ; Second, CAD tools which use VHDL are readily
e n d SM1-2; available for both PCs and workstations. Third,
a r c h i t e c t u r e S t r u c t u r e of SM1-2 i s VHDL is a very flexible language which is
s i g n a l A l , A2, A3, A 5 , A6, D3 : b i t : = I O * ; technology independent and which can be used to
s i g n a l Ql,Q2,Q3: b i t : = . O ' ; model a wide variety of digital systems.
s i g n a l QlN,QZN,QJN, XN: b i t : = ' l ' ;
11: I n v e r t e r p o r t map (X,XN) ;
The main disadvantage of VHDL is its complexity.
GI: Nand3 p o r t map ( Q l , Q 2 , Q 3 , A l ) ; This can be overcome by teaching only part of the
G2: Nand3 p o r t map ( Q l , Q 3 N , X N , A Z ) ; language and gradually introducing new concepts as
G3: Nand3 p o r t m a p (X,QlN,Q2N,A3) ; needed. Proper use of VHDL requires a good
G4: Nand3 p o r t map (Al,A2,A3,D3); understanding of timing analysis of digital systems.
FF1: DFF p o r t m a p (Q2N, CLK, Q l , Q1N) ; In order to get correct results from a VHDL
FF2: DFF p o r t map (Ql,CLK,Q2,Q2N); simulation, it is necessary to understand the VHDL
FF3 : DFF p o r t map ( D 3 , CLK, Q3,Q 3 N ) ; simulation process. The cost of good VHDL CAD
G5: Nand2 p o r t map ( X , Q 3 , A 5 ) ; tools is rather high, but most vendors will give
G6: Nand2 p o r t map (XN,Q3N,A6);
G7: Nand2 port map (A5,A6,Z);
substantial educational discounts.
end S t r u c t u e :

Figure 4. Structural model of sequential


: 1994 Frontiers in Education Conference E
' l I ! I I ! ! l l l l l l l l l : l l , i l , l l , , , l l l l . , l l l l ~ l ~ i l i l
0 loo0 2000
Figiure 5. Timing waveform for Figure 2

~ i l l , l l l i , l l l l l , l , l i l ~ i l l l , l l l l l l i , l l l l l l l ~ i l l
0 1OOO 2000

Figure 6. Timing waveform for Figure 4

Conclusion 6. Model Technology Inc., V-SystemlWindows

User's Manual, Version 4, Beaverton, Oregon,
VHDL has proven to be a valuable tool in teaching 1994.
digital systems design. Its use facilitates teaching a 7. Xilinx, Inc., The Programmable Logic Data
top-down design methodology. By introducing Book, 1994.
VHDL early in the course, we are able to relate 8. Roth, Charles H., "Teaching Digital System
VHDL to new concepts as they are encountered in Design with a Multilevel Digital Systems
the course. Use of VHDL is consistent with modern Simulator", 1987 Frontiers in Education
industrial practice, and knowledge of VHDL has Conference Proceedings, pp. 362-367.
given some of our students an edge in the job *****
marketplace. VHDL together with other CAD
software enables students to complete meaningful
design projects and implement them in FPGA Charles H. Roth
hardware in a relatively short time. Charles H. Roth joined the University of Texas at
Austin faculty in 1961, where he is currently serving
as Professor of Electrical and Computer
References Engineering. He received his BSEE from the
University of Minnesota, his MS from M.I.T., and
1. IEEE Standard VHDL Reference Manual his PhD from Stanford. Starting in 1971, he
(ANSIDEEE Std 1076-1993). IEEE, 1994. designed and implemented a self-paced course in
2. Bhasker, Jayaram, A VHDL Primer, Prentice-Hall, logic design, which he still continues to update and
1992. supervise. He is author of the widely-used textbook,
3. Armstrong, James and Gray, Gail, Structured Fundamentals of Logic Design, and several other
Logic Design with VHDL, Prentice-Hall, 1993. texts. In 1974, he received the General Dynamics
4. Perry, Douglas L., VHDL, 2d ed., McGraw-Hill, Award for outstanding engineering teaching. His
1994. teaching and research interests include micro-
5 . Navabi, Z., VHDL: Analysis &md Modeling of computer systems, the theory and design of digital
Digital Systems, McGraw-Hill, 1993. systems, and educational software.

1' 19!94 Frontiers in Education Conference E