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1. Neil Weste and K. Eshragian, “Principles of CMOS VLSI Design:
Subject Code : 08EC021 IA Marks : 50
A System Perspective,” 2nd edition, Pearson Education (Asia) Pte.
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100 Ltd., 2000.
2. Wayne, Wolf, “Modern VLSI design: System on Silicon”
MOS Transistor Theory: n MOS / p MOS transistor, threshold voltage Pearson Education”, Second Edition
equation, body effect, MOS device design equation, sub threshold region,
Channel length modulation. mobility variation, Tunneling, punch through, 3. Douglas A Pucknell & Kamran Eshragian , “Basic VLSI Design”
hot electron effect MOS models, small signal AC Characteristics, CMOS PHI 3rd Edition (original Edition – 1994)
inverter, βn / βp ratio, noise margin, static load MOS inverters, differential
inverter, transmission gate, tristate inverter, BiCMOS inverter. 4. Sung Mo Kang & Yosuf Lederabic Law, “CMOS Digital
Integrated Circuits: Analysis and Design”, McGraw-Hill (Third
CMOS Process Technology: Lambda Based Design rules, scaling factor, Edition)
semiconductor Technology overview, basic CMOS technology, p well / n
well / twin well process. Current CMOS enhancement (oxide isolation, LDD.
refractory gate, multilayer inter connect) , Circuit elements, resistor ,
capacitor, interconnects, sheet resistance & standard unit capacitance
concepts delay unit time, inverter delays , driving capacitive loads, propagate
delays, MOS mask layer, stick diagram, design rules and layout, symbolic VLSI SYSTEM AND ARCHITECTURE
diagram, mask feints, scaling of MOS circuits.
Subject Code : 08EC082 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Basics of Digital CMOS Design: Combinational MOS Logic circuits-
Total no. of Lecture Hours : 52 Exam Marks : 100
Introduction, CMOS logic circuits with a MOS load, CMOS logic circuits,
complex logic circuits, Transmission Gate. Sequential MOS logic Circuits -
Introduction, Behavior of hi stable elements, SR latch Circuit, clocked latch Behavior and Architecture: Dedicated and Programmable VLSI
and Flip Flop Circuits, CMOS D latch and triggered Flip Flop. Dynamic architectures, Instruction sets and through enhancement techniques
Logic Circuits - Introduction, principles of pass transistor circuits, Voltage (Parallelism. pipelining. cache, etc.)
boot strapping synchronous dynamic circuits techniques, Dynamic CMOS
circuit techniques
CISC Architecture Concepts: Typical CISC instruction set and its VLSI
implementation, RT-level optimization through hardware flow charting,
CMOS Analog Design: Introduction, Single Amplifier. Differential Design of the execution unit, Design of the control part (micro programmed
Amplifier, Current mirrors, Band gap references, basis of cross operational and hardwired), handling exceptions: Instruction boundary interrupts,
amplifier. immediate interrupts and traps.

Dynamic CMOS and clocking: Introduction, advantages of CMOS over RISC Architecture Concepts: Typical RISC instruction set and its VLSI
NMOS, CMOS\SOS technology, CMOS\bulk technology, latch up in bulk implementation, Execution pipeline, Benefits and problems of pipelined
CMOS., static CMOS design, Domino CMOS structure and design, Charge execution, Hazards of various types of pipeline stalling, concepts of
sharing, Clocking- clock generation, clock distribution, clocked storage scheduling (Static and dynamic) and forwarding to reduce / minimize
elements. pipeline stalls Exceptions in pipelined processors

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DSP Architecture Concepts: Typical DSP instruction set and its VLSI Processor and Memory Organization: Structural unit in as processor,
implementation processor selection for an embedded systems. Memory devices, memory
selection for an embedded system, allocation of memory to program
Dedicated Hardware Architecture Concepts: Example and Case studies. statements and blocks and memory map of a system. Direct memory
Dedicated DSP architecture Concepts: Synthesis, Scheduling and Resource accesses.
allocation, Conventional Residue number, distributed arithmetic architecture
Devices And Buses for Device Networks: I/O devices, serial
communication using FC, CAN devices, device drivers, parallel port device
REFERENCE BOOKS: driver in a system, serial port device driver in a system, device driver for
internal programmable timing devices, interrupt servicing mechanism, V
1. D A Patterson and I L Hennessy, “Computer Architecture: A context and periods for switching networked I/O devices using ISA, PCI
deadline and interrupt latency and advanced buses.
Quantitative approach”, Second edition, Margon Kaufmann, 1996
2. Lars Wanhammar, “DSP Integrated Circuits”, Academic Programming Concepts and Embedded Programming in C: Microchip
PlC microcontroller/Motorola MC68HC1I: Introduction, CPU architecture
Press 1999.
registers instruction sets, addressing modes, timers. Interrupts, ITC bus
3. D A Patterson and J L Hennessy, “Computer organization and operation, serial EEPROM, ADC, UART, serial programming /parallel slave
Design: Hardware/Software interface” Second Edition, Margan
Kaufmann, 1998 Program Modeling Concepts In Single and Multiprocessor Systems:
software development process, modeling process for software analysis before
4. Avtar Sing and Srinivas S, “DSP: Architecture,
software implementation, programming model for the event controlled or
Programming and Applications”, Thomson Learning, 2004. response time constrained real time programs, modeling of multiprocessor
5. B. Venkataramani and M. Baskar, “DSP: Architecture,
Programming and Applications”, TMH, 2002. Intel-Process Communication and Synchronization of Processors Tasks:
and threads; multiple process in an application, problems of sharing data by
multiple tasks and routines, inter process communications. RTOS task
scheduling models interrupt literacy and response times, performance metric
in scheduling models, standardization of RTOS, list of basic functions,
fifteen point strategy for synchronization.

1. Raj Kamal, “Embedded systems Architecture, Programming and
Subject Code : 08EC037 IA Marks : 50
Design”, TMH.
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100 2. J. W. Valvano, “Embedded Microcomputer system – Real time
Interfacing”, Thomson Learning Publishing
Introduction to Embedded System: An embedded system, processor, 3. Jane W. S., Liu, “Real Time Systems”, Pearson Education Asia Pub
hardware unit, soft ware embedded into a system, Example of an embedded
system, OS services, I/O, N/W, O/S, Real time and embedded OS.

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Subject Code : 08EC046 IA Marks : 50 VLSI TECHNOLOGY
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100 Subject Code : 08EC083 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Linear Equations: Fields; system of linear equations, and its solution sets;
elementary row operations and echelon forms; matrix operations; invertible Environment for VLSI Technology: Clean room and safety requirements.
matrices, LU-factorization. Wafer cleaning processes and wet chemical etching techniques.
Vector Spaces: Vector spaces; subspaces; bases and dimension; coordinates; Impurity Incorporation: Solid State diffusion modeling and technology;
summary of row-equivalence; computations concerning subspaces. Ion Implantation modeling, technology and damage annealing;
characterization of Impurity profiles.
Linear Transformations: Linear transformations; algebra of linear
transformations; isomorphism; representation of transformations by matrices; Oxidation: Kinetics of Silicon dioxide growth both for thick, thin and ultra
linear functionals; transpose of a linear transformation. thin films. Oxidation technologies in VLSI and ULSI; Characterization of
oxide films; High k and low k dielectrics for ULSI.
Canonical Forms: Characteristic values; annihilating polynomials; invariant Lithography: Photolithography, E-beam lithography and newer lithography
subspaces; direct-sum decompositions; invariant direct sums; primary techniques for VLSI/ULSI; Mask generation.
decomposition theorem; cyclic bases; Jordan canonical form. Iterative
estimates of characteristic values. Chemical Vapour Deposition Techniques: CVD techniques for deposition
of polysilicon, silicon dioxide, silicon nitride and metal films; Epitaxial
Inner Product Spaces: Inner products; inner product spaces; orthogonal sets growth of silicon; modeling and technology.
and projections; Gram-Schmidt process; QR-factorization; least-squares
problems; unitary operators. Metal Film Deposition: Evaporation and sputtering techniques. Failure
mechanisms in metal interconnects; Multi-level metallization schemes.
Symmetric Matrices and Quadratic Forms: Digitalization; quadratic
forms; constrained optimization; singular value decomposition. Plasma and Rapid Thermal Processing: PECVD, Plasma etching and RIE
techniques; RTP techniques for annealing, growth and deposition of various
REFERENCE BOOKS: films for use in ULSI.
Process integration for NMOS, CMOS and Bipolar circuits; Advanced MOS
1. David. C. Lay, “Linear Algebra and its Applications,” 3rd edition, technologies

Pearson Education (Asia) Pte. Ltd, 2005. REFERENCE BOOKS:

2. Kenneth Hoffman and Ray Kunze, "Linear Algebra," 2nd edition,
1. C.Y. Chang and S.M.Sze (Ed), “ULSI Technology”, McGraw Hill
Pearson Education (Asia) Pte. Ltd/ Prentice Hall of India, 2004. .
Companies Inc, 1996.
3. Bernard Kolman and David R. Hill, "Introductory Linear Algebra
2. Stephena, Campbell, “The Science and Engineering of
with Applications," Pearson Education (Asia) Pte. Ltd, 7th edition,
Microelectronic Fabrication”, Second Edition, Oxford University
Press, 2005.
4. Gilbert Strang, "Linear Algebra and its Applications," 3rd edition,
3. Yuan Taur, Tak. H. Ning, “Fundamentals of Modern VLSI
Thomson Learning Asia, 2003.
Devices”, Cambridge University Press, 2003
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4. S.K. Gandhi, “VLSI Fabrication Principles”, John Wiley Inc., REFERENCE BOOKS:
New York, 1983.
1. M.J.S .Smith, - “Application - Specific Integrated Circuits” –
Pearson Education, 2003.
ASIC DESIGN 2. Jose E.France, Yannis Tsividis, “Design of Analog-Digital VLSI

Subject Code : 08EC012 IA Marks : 50 Circuits for Telecommunication and signal processing”, Prentice
No. of Lecture Hours /week : 04 Exam Hours : 03 Hall, 1994.
Total no. of Lecture Hours : 52 Exam Marks : 100
3. Malcolm R.Haskard; Lan. C. May, “Analog VLSI Design - NMOS

Note All Designs Will Be Based On VHDL and CMOS”, Prentice Hall, 1998.

4. Mohammed Ismail and Terri Fiez, “Analog VLSI Signal and

Introduction: Full Custom with ASIC, Semi custom ASICS, Standard Cell
based ASIC, Gate array based ASIC, Channeled gate array, Channel less gate Information Processing”, McGraw Hill, 1994.
array, structured get array, Programmable logic device, FPGA design flow,
ASIC cell libraries
Data Logic Cells: Data Path Elements, Adders, Multiplier, Arithmetic
Operator, I/O cell, Cell Compilers DIGITAL SYSTEM DESIGN USING VHDL

ASIC Library Design: Logical effort: practicing delay, logical area and Subject Code : 08EC032 IA Marks : 50
logical efficiency logical paths, multi stage cells, optimum delay, optimum No. of Lecture Hours /week : 04 Exam Hours : 03
no. of stages, library cell design. Total no. of Lecture Hours : 52 Exam Marks : 100

Low-Level Design Entry: Schematic Entry: Hierarchical design. The cell

Specification of combinational systems using VHDL, Introduction to VHDL,
library, Names, Schematic, Icons & Symbols, Nets, schematic entry for
Basic language element of VHDL, Behavioral Modeling, Data flow
ASIC’S, connections, vectored instances and buses, Edit in place attributes,
modeling, Structural modeling, Subprograms and overloading, VHDL
Netlist, screener, Back annotation
description of gates.
Programmable ASIC: programmable ASIC logic cell, ASIC I/O cell
Description and design of sequential circuits using VHDL, Standard
A Brief Introduction to Low Level Design Language: an introduction to combinational modules, Design of a Serial Adder with Accumulator, State
EDIF, PLA Tools, an introduction to CFI designs representation. Half gate Graph for Control Network, design of a Binary Multiplier, Multiplication of a
ASIC. Introduction to Synthesis and Simulation; Signed Binary Number, Design of a Binary Divider.

ASIC Construction Floor Planning and Placement And Routing: Register- transfer level systems, Execution Graph, Organization of System,
Physical Design, CAD Tools, System Partitioning, Estimating ASIC size, Implementation of RTL Systems, Analysis of RTL Systems, and Design of
partitioning methods. Floor planning tools, I/O and power planning, clock RTL Systems.
planning, placement algorithms, iterative placement improvement, Time
driven placement methods. Physical Design flow global Routing, Local Data Subsystems, Storage Modules, Functional Modules, Data paths, Control
Routing, Detail Routing, Special Routing, Circuit Extraction and DRC. Subsystems, Micro programmed Controller, Structure of a micro
programmed controller, Micro instruction Format, Micro instruction
sequencing, Micro instruction Timing, Basic component of a micro system,
memory subsystem.
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I/O Subsystem, Processors, Operation of the computer and cycle time, Binary Sense Amplifier, Sample and Hold, Sampled data circuits, Switched
Decoder, Binary Encoder, Multiplexers and Demultiplexers, Floating Point capacitor filters, DAC, ADC, RF amplifier, Oscillator, PLL, Mixer.
Arithmetic-Representation of Floating Point Number, Floating Point
Multiplication REFERENCE BOOKS:
1. Razavi B., “Design of Analog CMOS Integrated Circuits”,
McGraw Hill, 2001
1. C. H. Roth, “Digital System Design using VHDL”, Thomson 2. R. Jacob Baker,”CMOS: Mixed-Signal Circuit Dedsign”,
Learning”, 2001 John Wiley, 2008
2. M. Ercegovac, T. Lang and L.J. Moreno, “Introduction to Digital 3. Baker, Li, Boyce, “CMOS: Circuit Design, Layout and
Systems”, Wiley,2000. Simulation”, Prentice Hall of India, 2000
3. J. Bhaskar, “A VHDL Primer”, Addison Wesley, 1999. 4. E. Allen, Douglas R. Holberg, “CMOS Analog circuit
4. John.F.Wakerly, “Digital Design-Principles and Practices”, PHI, Design”
3 Edition updated, 2005
5. Navabi, “VHDL-Analysis and Modeling of Digital Systems”,

Subject Code : 08EC070 IA Marks : 50

No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Introduction: Real Time System, Types, Real Time Computing, Design
Subject Code : 08EC025 IA Marks : 50 Issue, Sample Systems, Hardware Requirements- Processor in a system,
No. of Lecture Hours /week : 04 Exam Hours : 03 System Memories, System I/O.
Total no. of Lecture Hours : 52 Exam Marks : 100 Hardware Requirements for Real-Time Applications: Processors,
Interfaces, (A/D, D/A, USART, Watchdog Timers, Interrupt Controllers).
Introduction to CMOS Analog Circuits : MOS transistor DC and AC small Embedded Systems: Introduction, Various System Architecture for
signal parameters from large signal model, Embedded System, High Performance Processors - Strong ARM processors,
Programming, Interrupt Structure, I/O architecture.
Common Source Amplifier : with resistive load, diode load and current
source load, Source follower, Common gate amplifier, Cascode amplifier,
Real Time Operating System: Fundamental Requirements of RTOS, Real
Folded Cascode, Frequency response of amplifiers, Current
Time Kernel Types, Schedulers, Various Scheduling modules with examples,
source/sink/mirror, Matching, Wilson current source and Regulated Cascode
Latency (Interrupt Latency, Scheduling Latency and Context Switching
current source, Band gap reference,
Latency), Tasks Management, State Transition Diagram, Task Control Block.
Differential Amplifier, Gilbert cell, Op-Amp, Design of 2 stage Op-Amp, Mutual Exclusion, Inter-task communication and synchronization of tasks.
DC and AC response, Frequency compensation, slew rate, Offset effects,
PSRR, Noise, Comparator, Memory and File management: Pipelining and Cache Memories, Paging
and Segmentation, Fragmentation, Address Translation.

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Case Study: Introduction to VX Works/Mucos/pSOS; Example systems. Probabilistic power analysis: Random logic signals, probability &
frequency, probabilistic power analysis techniques, signal entropy.
Design of Real Time Systems: Introduction, Development Methodologies,
Real Time applications; Considerations such as double buffing, Design Low Power Design Circuit level: Power consumption in circuits. Flip Flops
Analysis. & Latches design, high capacitance nodes, low power digital cells library
Logic level: Gate reorganization, signal gating, logic encoding, state machine
encoding, pre-computation logic
Low power Architecture & Systems: Power & performance management,
1. Stuart Bennett, “Real-Time Computer Control: An Introduction”, switching activity reduction, parallel architecture with voltage reduction,
2nd Edn. Pearson Education, 2005 flow graph transformation, low power arithmetic components, low power
memory design.
2. Philip. A. Laplante, “Real-Time Systems Design and Analysis- an
Low power Clock Distribution: Power dissipation in clock distribution,
Engineer’s Handbook”- Second Edition, PHI Publications. single driver Vs distributed buffers, Zero skew Vs tolerable skew, chip &
3. Jane W.S. Liu, “Real-Time Systems”, Pearson Education Inc., package co design of clock network
2000. Algorithm & Architectural Level Methodologies: Introduction, design
flow, Algorithmic level analysis & optimization, Architectural level
4. Dr. K.V.K K Prasad, “Embedded Real Time Systems: Concepts estimation & synthesis.
Design and Programming”, Dreamtech Press New Delhi, 2003.
5. David A. Evesham, “Developing Real Time Systems – A Practical REFERENCE BOOKS:

Introduction”, Galgotia Publications, 1990. 1. Kaushik Roy, Sharat Prasad, “Low-Power CMOS VLSI Circuit
Design” Wiley, 2000
2. Gary K. Yeap, “Practical Low Power Digital VLSI Design”, KAP,
3. Rabaey, Pedram, “Low Power Design Methodologies” Kluwer
Subject Code : 08EC047 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03 Academic, 1997
Total no. of Lecture Hours : 52 Exam Marks : 100

Introduction : Need for low power VLSI chips, Sources of power dissipation TESTING AND VERIFICATION OF VLSI CIRCUITS
on Digital Integrated circuits. Emerging Low power approaches, Physics of
power dissipation in CMOS devices. Subject Code : 08EC078 IA Marks : 50
Device & Technology Impact on Low Power: Dynamic dissipation in No. of Lecture Hours /week : 04 Exam Hours : 03
CMOS, Transistor sizing & gate oxide thickness, Impact of technology Total no. of Lecture Hours : 52 Exam Marks : 100
Scaling, Technology & Device innovation
Power estimation, Simulation Power analysis: SPICE circuit simulators, Introduction: Scope of testing and verification in VLSI design process;
gate level logic simulation, capacitive power estimation, static state power, Issues in test and verification of complex chips; embedded cores and SOCs
gate level capacitance estimation, architecture level analysis, data correlation
analysis in DSP systems, Monte Carlo simulation. Fundamentals of VLSI testing, Fault models. Automatic test pattern
generation, Design for testability, Scan design,
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Test interface and boundary scan. programmable gate arrays, Sea of gate and gate array design, standard cell
design, full custom mask design.
System Testing and test for SOCs, Iddq testing, Delay fault testing, BIST for
testing of logic and memories, Test automation. Chip Design Methods: Behavioral synthesis, RTL synthesis, Logic
optimization and structural tools layout synthesis, layout synthesis, EDA
Design Verification Techniques based on simulation, analytical and formal Tools for System
approaches, Functional verification, Timing verification, Formal verification,
Basics of equivalence checking and model checking, Design Capture Tools: HDL Design, Schematic Design, Layout Design,
Floor planning and Chip Composition. Design Verification Tools: Simulation
REFERENCE BOOKS : Timing Verifiers, Net List Comparison Layout Extraction, Design Rule
1. M. Abramovici, M. A. Breuer, A. D. Friedman, “Digital Systems
Data Path Sub System Design: Introduction, Addition, Subtraction,
Testing and Testable Design” Piscataway, New Jersey: IEEE
Comparators, Counters, Boolean logical operations, coding, shifters,
Press, 1994 Multiplication, Parallel Prefix computations
2. M. Bushnell and V. D. Agarwal, "Essentials of Electronic Testing
Array Subsystem Design: SRAM, Special purpose RAMs, DRAM, Read
for Digital, Memory and Mixed-Signal VLSI Circuits", Kluwer only memory, Content Addressable memory, Programmable logic arrays.
Academic Publishers, 2000
Control Unit Design: Finite State Machine (FSM) Design, Control Logic
3. T.Kropf, "Introduction to Formal Hardware Verification", Implementation: PLA control implementation, ROM control implementation.
Springer Verlag, 2000.
Special Purpose Subsystems: Packaging, power distribution, I/O, Clock,
4. P. Rashinkar, Paterson and L. Singh, "System-on-a-Chip Transconductance amplifier, follower integrated circuits, etc
Verification-Methodology and Techniques", Kluwer Academic
Design Economics: Nonrecurring and recurring engineering Costs, Fixed
Publishers, 2001. Costs, Schedule, Person power, example
5. Samiha Mourad and Yervant Zorian, “Principles of Testing
VLSI System Testing & Verification: Introduction, A walk through the
Electronic Systems”, Wiley (2000). Test Process, Reliability, Logic Verification Principles, Silicon Debug
Principles, Manufacturing Test Principles, Design for Testability, Boundary

VLSI Applications: Case Study: RISC microcontroller, ATM Switch,

Subject Code : 08EC027 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03 1. Neil H.E. Weste, Davir Harris, “CMOS VLSI Design: A Circuits
Total no. of Lecture Hours : 52 Exam Marks : 100
and System Perspectives” Addison Wesley - Pearson Education,
VLSI System Design Methodology: Structure Design, Strategy, Hierarchy, 3rd Edition, 2004.
Regularity, Modularity, and Locality. System on Chip Design options: 2. Wayne, Wolf, “Modern VLSI Design: System on Silicon”
Programmable logic and structures, Programmable interconnect,
Prentice Hall PTR/Pearson Education, Second Edition, 1998
17 18
3. Douglas A Pucknell & Kamran Eshragian , “Basic VLSI Design” 2. Christophn Meinel & Thorsten Theobold, “Algorithm and Data
PHI 3 Edition (original Edition – 1994) Structures for VLSI Design”, KAP, 2002.
3. Rolf Drechsheler : “Evolutionary Algorithm for VLSI”, Second
ALGORITHMS FOR VLSI DESIGN AUTOMATION 4. Trimburger, “Introduction to CAD for VLSI”, Kluwer Academic
publisher, 2002
Subject Code : 08EC010 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
Logic Synthesis & Verification: Introduction to combinational logic
synthesis, Binary Decision Diagram, Hardware models for High-level Subject Code : 08EC007 IA Marks : 50
synthesis. No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100
VLSI Automation Algorithms:
Partitioning: problem formulation, classification of partitioning algorithms, Introduction - The concept of embedded systems design, embedded
Group migration algorithms, simulated annealing & evolution, other microcontroller cores, embedded memories, Examples of embedded systems.
partitioning algorithms
Technological Aspects of Embedded Systems: interfacing between analog
Placement, Floor Planning & Pin Assignment: problem formulation, and digital blocks, signal conditioning, Digital signal processing.
simulation base placement algorithms, other placement algorithms, constraint
based floor planning, floor planning algorithms for mixed block & cell Sub-System Interfacing: interfacing with external systems, user interfacing.
design. General & channel pin assignment Design trade offs due to process compatibility, thermal considerations, etc.
Software aspects of embedded systems: real time programming languages
Global Routing: Problem formulation, classification of global routing and operating systems for embedded systems.
algorithms, Maze routing algorithm, line probe algorithm, Steiner Tree based
algorithms, ILP based approaches REFERENCE BOOKS:

Detailed Routing: problem formulation, classification of routing algorithms, 1. J.W. Valvano, "Embedded Microcomputer System: Real Time
single layer routing algorithms, two layer channel routing algorithms, three
layer channel routing algorithms, and switchbox routing algorithms Interfacing", Brooks/Cole, 2000.
2. Jack Ganssle, "The Art of Designing Embedded Systems",
Over The Cell Routing & Via Minimization: two layers over the cell
routers, constrained & unconstrained via minimization Newnes, 1999.
3. David Simon, "An Embedded Software Primer", Addison Wesley,
Compaction: problem formulation, one-dimensional compaction, two
dimension based compaction, hierarchical compaction 2000


1. Naveed Shervani, “Algorithms for VLSI physical design

Automation”, Kluwer Academic Publisher, Second edition.
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III – SEMESTER 3. Thomas H. Lee “Design of CMOS RF Integrated Circuits”
Cambridge University press 1998.
Subject Code : 08EC020 IA Marks : 50 4. Y.P. Tsividis, “Mixed Analog and Digital Devices and
No. of Lecture Hours /week : 04 Exam Hours : 03 Technology”, TMH 1996
Total no. of Lecture Hours : 52 Exam Marks : 100

Introduction to RF Design and Wireless Technology: Design and

Applications, Complexity and Choice of Technology. Basic concepts in RF
design: Nonlinearly and Time Variance, Intersymbol interference, random HARDWARE - SOFTWARE CO-DESIGN
processes and noise. Sensitivity and dynamic range, conversion of gains and
distortion Subject Code : 08EC041 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
RF Modulation: Analog and digital modulation of RF circuits, Comparison Total no. of Lecture Hours : 52 Exam Marks : 100
of various techniques for power efficiency, Coherent and non-coherent
detection, Mobile RF communication and basics of Multiple Access Introduction: Motivation hardware & software co-design, system design
techniques. Receiver and Transmitter architectures, Direct conversion and consideration, research scope & overviews
two-step transmitters
Hardware Software back ground: Embedded systems, models of design
RF Testing: RF testing for heterodyne, Homodyne, Image reject, Direct IF representation, the virtual machine hierarchy, the performance3 modeling,
and sub sampled receivers. Hardware Software development,
BJT and MOSFET Behavior at RF Frequencies: BJT and MOSFET
Hardware Software Co-Design Research: An informal view of co-design,
behavior at RF frequencies, modeling of the transistors and SPICE model,
Hardware Software tradeoffs, crosses fertilization, typical co-design process,
Noise performance and limitations of devices, integrated parasitic elements at
co-design environments, limitation of existing approaches, ADEPT modeling
high frequencies and their monolithic implementation
RF Circuits Design: Overview of RF Filter design, Active RF components
Co-design Concepts: Functions, functional decomposition, virtual machines,
& modeling, Matching and Biasing Networks. Basic blocks in RF systems
Hardware Software partitioning, Hardware Software partitions, Hardware
and their VLSI implementation, Low noise Amplifier design in various
Software alterations, Hardware Software trade offs, co-design.
technologies, Design of Mixers at GHz frequency range, Various mixers-
working and implementation. Oscillators- Basic topologies VCO and
Methodology for Co-Design: Amount of unification, general consideration
definition of phase noise, Noise power and trade off. Resonator VCO
& basic philosophies, a framework for co-design
designs, Quadrature and single sideband generators. Radio frequency
Synthesizers- PLLS, Various RF synthesizer architectures and frequency
Unified Representation for Hardware & Software: Benefits of unified
dividers, Power Amplifier design, Liberalization techniques, Design issues in
representation, modeling concepts
integrated RF filters.
An Abstract Hardware & Software Model: Requirement & applications of
REFERENCE BOOKS: the models, models of Hardware Software system, an abstract Hardware
1. B. Razavi, “RF Microelectronics” PHI 1998 Software models, generality of the model

2. R. Jacob Baker, H.W. Li, D.E. Boyce “CMOS Circuit Design, Performance Evaluation: Application of t he abstract Hardware & Software
layout and Simulation”, PHI 1998. model, examples of performance evaluation

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Object Oriented Techniques in Hardware Design: Motivation for object Hardware Modeling: Hardware Modeling Languages, distinctive features,
oriented technique, data types, modeling hardware components as classes, structural hardware language, Behavioral hardware language, HDLs used in
designing specialized components, data decomposition, Processor example. synthesis, abstract models, structures logic networks, state diagrams, data
flow and sequencing graphs, compilation and optimization techniques.
Two Level Combinational Logic Optimization: Logic optimization,
1. Sanjaya Kumar, James H. Ayler “The Co-design of Embedded principles, operation on two level logic covers, algorithms for logic
minimization, symbolic minimization and encoding property, minimization
Systems: A Unified Hardware Software Representation”,
of Boolean relations.
Kluwer Academic Publisher, 2002 .
Multiple Level Combinational Optimizations: Models and transformations
2. H. Kopetz, “Real-Time Systems”, Kluwer, 1997. for combinational networks, algebraic model, Synthesis of testable network,
algorithm for delay evaluation and optimization, rule based system for logic
3. R. Gupta, “Co-synthesis of Hardware and Software for optimization.
Embedded Systems”, Kluwer 1995.
Sequential Circuit Optimization: Sequential circuit optimization using state
based models, sequential circuit optimization using network models.
4. S. Allworth, “Introduction to Real-time Software Design”,
Springer-Verlag, 1984. Schedule Algorithms: A model for scheduling problems, Scheduling with
resource and without resource constraints, Scheduling algorithms for
5. C. M. Krishna, K. Shin, “Real-time Systems”, Mc-Graw Hill, 1997 extended sequencing models, Scheduling Pipe lined circuits.

6. Peter Marwedel, G. Goosens, “Code Generation for Embedded Cell Library Binding: Problem formulation and analysis, algorithms for
library binding, specific problems and algorithms for library binding (lookup
Processors”, Kluwer Academic Publishers, 1995. table F.P.G.As and Antifuse based F.P.G.As), rule based library binding.

Testing: Simulation, Types of simulators, basic components of a simulator,

fault simulation Techniques, Automatic test pattern generation methods
(ATPG), design for Testability (DFT) Techniques.

Subject Code : 08EC077 IA Marks : 50 1. Giovanni De Micheli, “Synthesis and Optimization of Digital
No. of Lecture Hours /week : 04 Exam Hours : 03
Circuits”, Tata McGraw-Hill, 2003.
Total no. of Lecture Hours : 52 Exam Marks : 100
2. Srinivas Devadas, Abhijit Ghosh, and Kurt Keutzer, “Logic
Introduction: Microelectronics, semiconductor technologies and circuit Synthesis”, McGraw-Hill, USA, 1994.
taxonomy, Microelectronic design styles, computer aided synthesis and
optimization. 3. Neil Weste and K. Eshragian, “Principles of CMOS VLSI Design:
A System Perspective,” 2nd edition, Pearson Education (Asia)
Graphs: Notation, undirected graphs, directed graphs, combinatorial
optimization, Algorithms, tractable and intractable problems, algorithms for Pte. Ltd., 2000.
linear and integer programs, graph optimization problems and algorithms, 4. Kevin Skahill, “VHDL for Programmable Logic,” Pearson
Boolean algebra and Applications.
Education (Asia) Pte. Ltd., 2000.
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CAD TOOLS FOR VLSI DESIGN MIS Structures and MOSFETS: MIS systems in equilibrium, under bias,
small signal operation of MESFETS and MOSFETS.
Subject Code : 08EC019 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03 Short Channel Effects and Challenges to CMOS: Short channel effects,
Total no. of Lecture Hours : 52 Exam Marks : 100 scaling theory, processing challenges to further CMOS miniaturization

Beyond CMOS: Evolutionary advances beyond CMOS, carbon Nano tubes,

Introduction to VLSI Methodologies - VLSI Physical Design Automation -
conventional vs. tactile computing, computing, molecular and biological
Design and Fabrication of VLSI Devices - Fabrication process and its impact
computing Mole electronics-molecular Diode and diode- diode logic .Defect
on Physical Design.
tolerant computing,

A Quick Tour of VLSI Design Automation Tools: Data structures and Super Buffers, Bi-CMOS and Steering Logic: Introduction, RC delay
Basic Algorithms, Algorithmic Graph theory and computational complexity, lines, super buffers- An NMOS super buffer, tri state super buffer and pad
Tractable and Intractable problems. drivers, CMOS super buffers, Dynamic ratio less inverters, large capacitive
loads, pass logic, designing of transistor logic, General functional blocks -
General Purpose Methods for Combinational Optimization: partitioning, NMOS and CMOS functional blocks.
floor planning and pin assignment, placement, routing.
Special Circuit Layouts and Technology Mapping: Introduction, Talley
circuits, NAND-NAND, NOR- NOR, and AOI Logic, NMOS, CMOS
Simulation-Logic Synthesis: Verification-High level synthesis - Multiplexers, Barrel shifter, Wire routing and module lay out.
Compaction. Physical Design Automation of FPGAs, MCMS-VHDL-
Verilog-Implementation of Simple circuits using VHDL and Verilog. System Design: CMOS design methods, structured design methods,
Strategies encompassing hierarchy, regularity, modularity & locality, CMOS
REFERENCE BOOKS: Chip design Options, programmable logic, Programmable inter connect,
programmable structure, Gate arrays standard cell approach, Full custom
1. N.A. Shervani, “Algorithms for VLSI Physical Design Design.
Automation”, 1999.
2. S.H.Gerez, “Algorithms for VLSI Design Automation”, 1998.
1. Kevin F Brrnnan “Introduction to Semi Conductor Device”,
Cambridge publications
ELECTIVE-IV 2. Eugene D Fabricius “Introduction to VLSI Design”, McGraw-Hill
International publications
Subject Code : 08EC009 IA Marks : 50 3. D.A Pucknell “Basic VLSI Design”, PHI Publication
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100 4. Wayne Wolf, “Modern VLSI Design” Pearson Education, Second
Edition , 2002
Review of MOS Circuits: MOS and CMOS static plots, switches,
comparison between CMOS and BI - CMOS.

MESFETS: MESFET and MODFET operations, quantitative description of


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RF AND MICROWAVE CIRCUIT DESIGN Design of Data Processing Elements: Adder Architectures, Multiplier
Architectures, Counter Architectures, ALU Architectures,
Subject Code : 08EC071 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03 Design of Storage Elements: Latches, Flip-Flops, Registers, Register Files;
Total no. of Lecture Hours : 52 Exam Marks : 100
Design of Control Part: Moore & Mealy Machines, PLA Based
Implementation, Random Logic Implementation, Micro-programmed
Wave Propagation in Networks: Introduction to RF/Microwave Concepts
and applications; RF Electronics Concepts; Fundamental Concepts in Wave
Propagation; Circuit Representations of two port RF/MW networks
Structuring of Logic Design: PLA Design, PLA Architectures, Gates Array
Cell Design, Concept of Standard Cell Based Design, Cell Library Design;
Passive Circuit Design: The Smith Chart, Application of the Smith Chart in
Distributed and lumped element circuit applications, Design of Matching
Memory Design: SRAM cell, Various DRAM cells, RAM Architectures,
Address Decoding, Read/Write Circuitry, Sense Amplifier and their Design,
ROM Design;
Basic Considerations in Active Networks: Stability Consideration in Active
networks, Gain Considerations in Amplifiers, Noise Considerations in Active
Clocking Strategies, Clock Skew, Clock Distribution and Routing, Clock
Buffering, Clock Domains, Gated Clock, Clock Tree; Synchronization
Failure and Meta-stability.
Active Networks: Linear and Nonlinear Design: RF/MW Amplifiers Small
Signal Design, Large Signal Design, RF/MW Oscillator Design, RF/MW
Frequency Conversion Rectifier and Detector Design, Mixer Design, RF/MW REFERENCE BOOKS:
Control Circuit Design, RF/MW Integrated circuit design.
1. Neil H. E. Weste and Kamran Eshraghian, “Principles of CMOS
1. Matthew M. Radmanesh, “Radio Frequency and Microwave VLSI Design – A Systems Perspective”, Addison Wesley.
Electronics Illustrated," Pearson Education (Asia) Pte. Ltd., 2004.
2. Wayne Wolf, “Modern VLSI Design”, Prentice Hall.
2. Reinhold Ludwig and Pavel Bretchko, “RF Circuit Design: Theory
3. C. Mead and L. Conway, “Introduction to VLSI Systems”,
and Applications,” Pearson Education (Asia) Pte. Ltd., 2004.
Addison Wesley.

VLSI SUB-SYSTEM DESIGN 4. J. P. Uyemura, “Circuit Design for CMOS VLSI”, Kluwer
Subject Code : 08EC081 IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 52 Exam Marks : 100

Review of Transistor, Inverter Analysis, CMOS Process and Masking

Sequence, Layer Properties and Parasitic Estimation;

VLSI Design Flow, Design Methodologies, Abstraction Levels;

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