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R R R R
A A
RE RE
RT RT
B B
DE DE
D D D D
A B A B
R R
D D
R RE DE D R RE DE D
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN65HVD72, SN65HVD75, SN65HVD78
SLLSE11D – MARCH 2012 – REVISED JULY 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 9.1 Overview ................................................................. 15
2 Applications ........................................................... 1 9.2 Functional Block Diagram ....................................... 15
3 Description ............................................................. 1 9.3 Feature Description................................................. 15
9.4 Device Functional Modes........................................ 15
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 4 10 Application and Implementation........................ 17
10.1 Application Information.......................................... 17
6 Pin Configuration and Functions ......................... 4
10.2 Typical Application ................................................ 18
7 Specifications......................................................... 5
11 Power Supply Recommendations ..................... 24
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5 12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 25
7.3 Recommended Operating Conditions....................... 5
12.2 Layout Example .................................................... 25
7.4 Thermal Information .................................................. 6
7.5 Electrical Characteristics........................................... 6 13 Device and Documentation Support ................. 26
7.6 Power Dissipation ..................................................... 7 13.1 Device Support...................................................... 26
7.7 Switching Characteristics: 250 kbps Device 13.2 Documentation Support ........................................ 26
(SN65HVD72) Bit Time ≥4 µs.................................... 7 13.3 Related Links ........................................................ 26
7.8 Switching Characteristics: 20 Mbps Device 13.4 Community Resources.......................................... 26
(SN65HVD75) Bit Time ≥50 ns .................................. 8 13.5 Trademarks ........................................................... 26
7.9 Switching Characteristics: 50 Mbps Device 13.6 Electrostatic Discharge Caution ............................ 26
(SN65HVD78) Bit Time ≥20 ns .................................. 8 13.7 Glossary ................................................................ 26
7.10 Typical Characteristics ............................................ 9
14 Mechanical, Packaging, and Orderable
8 Parameter Measurement Information ................ 11 Information ........................................................... 27
9 Detailed Description ............................................ 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Added the SON-8 package and Nodes column to Device Comparison Table,...................................................................... 4
• Changed the Voltage range at A or B Inputs MIN value From: –8 V To: –13 V .................................................................... 5
• Added footnote for free-air temperature to the Recommended Operating Conditions table.................................................. 5
2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
• Changed the Bus input current (disabled driver) TYP values for HVD78 VI = 12 V From: 150 To: 240 and VI = –7 V
From: –120 To: –180 .............................................................................................................................................................. 7
• Changed, Thermal Information............................................................................................................................................... 7
• Changed, Thermal Characteristics ......................................................................................................................................... 7
• Added TYP values to the Switching Characteristics table...................................................................................................... 8
• Added TYP values to the Switching Characteristics table...................................................................................................... 8
• Changed the SN65HVD72, 75, 78 Logic Diagram ............................................................................................................... 15
• Added section: LOW-POWER STANDBY MODE ................................................................................................................ 19
• Added VALUEs to the Thermal Characteristics table in the DEVICE INFORMATION section. ........................................... 7
• Changed the Switching Characteristics condition statement From: 15 kbps devices (SN65HVD73, 74, 75) bit time >
65 ns To: 20 Mbps devices (SN65HVD73, 74, 75) bit time > 50 ns ...................................................................................... 8
• Changed the Switching Characteristics condition statement From: 50 kbps devices (SN65HVD76, 77, 78) bit time >
20 ns To: 50 Mbps devices (SN65HVD76, 77, 78) bit time > 20 ns ...................................................................................... 8
• Added Figure 4 to Typical Characteristics. ............................................................................................................................ 9
• Added Figure 5 to Typical Characteristics. ............................................................................................................................ 9
• Added Figure 6 to Typical Characteristics. ............................................................................................................................ 9
• Added Figure 7 to Typical Characteristics. ............................................................................................................................ 9
• Added Figure 8 to Typical Characteristics. ............................................................................................................................ 9
• Added Figure 9 to Typical Characteristics. ............................................................................................................................ 9
• Added Application Information section to data sheet. .......................................................................................................... 17
D Package
8-Pin SOIC DGK Package
Top View 8-Pin VSSOP
Top View
R 1 8 VCC
R 1 8 VCC
RE 2 7 B
RE 2 7 B
DE 3 6 A DE 3 6 A
D 4 5 GND D 4 5 GND
DRB Package
8-Pin VSON
Top View
R 1 8 VCC
RE 2 7 B
DE 3 6 A
D 4 5 GND
Pin Functions
PIN
TYPE DESCRIPTION
NAME NUMBER
A 6 Bus I/O Driver output or receiver input (complementary to B)
B 7 Bus I/O Driver output or receiver input (complementary to A)
D 4 Digital input Driver data input
DE 3 Digital input Active-high driver enable
GND 5 Reference potential Local device ground
R 1 Digital output Receive data output
RE 2 Digital input Active-low receiver enable
VCC 8 Supply 3-V to 3.6-V supply
7 Specifications
7.1 Absolute Maximum Ratings
(1)
over recommended operating range (unless otherwise specified)
MIN MAX UNIT
Supply voltage, VCC –0.5 5.5
Voltage at A or B inputs –13 16.5
V
Input voltage at any logic pin –0.3 5.7
Voltage input, transient pulse, A and B, through 100 Ω –100 100
Receiver output current –24 24 mA
Junction temperature, TJ 170 °C
Continuous total power dissipation See Power Dissipation
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) By inference from contact discharge results, see Application and Implementation.
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
(2) Operation is specified for internal (junction) temperatures up to 150°C. Self-heating due to internal power dissipation should be
considered for each application. Maximum junction temperature is internally limited by the thermal shutdown (TSD) circuit which disables
the driver outputs when the junction temperature reaches 170°C.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(1) Under any specific conditions, VIT+ is assured to be at least VHYS higher than VIT–.
6 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
3.5 3.5
VCC = 3.3 V,
DE = VCC, VCC = 3.3 V,
100 W 60 W
D=0V
D=0V
2.5 2.5
2 2
1.5 1.5
VOL
1 1
0.5 0.5
0 0
0 20 40 60 80 100 0 20 40 60 80 100
IO - Driver Output Current - mA IO - Driver Output Current - mA
Figure 1. Driver Output Voltage vs Driver Output Current Figure 2. Driver Differential Output Voltage vs Driver Output
Current
40 4
TA = 25°C
35 RL = 54 W 3.5
D = VCC
DE = VCC
IO - Driver Output Current - mA
25 2.5
20 2
15 1.5
10 1
5 0.5
0 0
0 0.5 1 1.5 2 2.5 3 3.5 -40 -20 0 20 40 60 80 100 120
o
VCC Supply Voltage - V Temperature - C
Figure 3. Driver Output Current vs Supply Voltage Figure 4. SN65HVD78 Driver Rise or Fall Time vs
Temperature
12 70
RL = 54 W
60
10
Driver Propagation Delay - ns
50
ICC - Supply Current - mA
40
6
30
4
20
2 10
0 0
-40 -20 0 20 40 60 80 100 120 50 70 90 110 130 150 170 190 210 230 250
o
Temperature - C Signaling Rate - kbps
Figure 5. SN65HVD78 Driver Propagation Delay vs Figure 6. SN65HVD72 Supply Current vs Signal Rate
Temperature
RL = 54 W RL = 54 W
60 60
50 50
ICC - Supply Current - mA
30 30
20 20
10 10
0 0
0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 35 40 45 50
2.5
Receiver Output (R) V
VIT- (-7V)
2
VIT-(0V)
VIT-(12V)
1.5
VIT+(-7V)
VIT+(0V)
1
VIT+(12V)
0.5
0
-150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50
Differential Input Voltage (VID) mV
Figure 9. Receiver Output vs Input
DE
A
D
0 V or 3 V VOD 60 W ±1%
+ –7 V < V(test) < 12 V
B _
375 W ±1%
S0301-01
Figure 10. Measurement of Driver Differential Output Voltage With Common-Mode Load
A VA
RL/2
A
D B VB
0 V or 3 V VOD
VOC(PP) DVOC(SS)
B
RL/2
VOC
CL
VOC
S0302-01
Figure 11. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
50% 50%
A
»
B W
W
»
Figure 12. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
3V
A S1
D VO VI
3V 50% 50%
B 0V
DE RL = 110 W 0.5 V
CL = 50 pF ±20% tPZH
Input ± 1% VOH
VI 50 W CL Includes Fixture 90%
Generator
and Instrumentation VO
Capacitance 50%
»0V
tPHZ
S0304-01
Figure 13. Measurement of Driver Enable and Disable Times With Active High Output and Pulldown Load
RL = 110 W »3V
A ±1%
S1 VI 50% 50%
D VO
3V
0V
B tPZL tPLZ
DE
CL = 50 pF ±20% »3V
Input
Generator VI 50 W CL Includes Fixture VO
and Instrumentation 50%
10%
Capacitance VOL
S0305-01
Figure 14. Measurement of Driver Enable and Disable Times With Active Low Output and Pullup Load
3V
A
VO VI 50% 50%
R
Input
VI 50 W 0V
Generator B tPLH tPHL
1.5 V CL = 15 pF ±20% VOH
RE 90% 90%
0V VO 50% 50%
10% 10% VOL
CL Includes Fixture
tr tf
and Instrumentation
Capacitance
S0306-01
Figure 15. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
DE A
R VO 1 kW ± 1%
0 V or 3 V D S1
B
CL = 15 pF ±20%
RE
CL Includes Fixture
and Instrumentation
Input Capacitance
Generator VI 50 W
3V
VI 50% 50%
0V
tPZH(1) tPHZ
VOH
D at 3 V
90% S1 to GND
VO 50%
»0V
tPZL(1) tPLZ
VCC
D at 0 V
VO 50% S1 to VCC
10%
VOL
S0307-01
Figure 16. Measurement of Receiver Enable and Disable Times With Driver Enabled
A
0 V or 1.5 V R VO 1 kW ± 1%
S1
B
1.5 V or 0 V CL = 15 pF ±20%
RE
CL Includes Fixture
and Instrumentation
Input Capacitance
Generator VI 50 W
3V
VI 50%
0V
tPZH(2)
VOH
A at 1.5 V
VO 50% B at 0 V
S1 to GND
GND
tPZL(2)
VCC
A at 0 V
VO 50% B at 1.5 V
S1 to VCC
VOL
S0308-01
9 Detailed Description
9.1 Overview
The SN65HVD72, SN65HVD75, and SN65HVD78 are low-power, half-duplex RS-485 transceivers available in 3
speed grades suitable for data transmission up to 250 kbps, 20 Mbps, and 50 Mbps.
These devices have active-high driver enables and active-low receiver enables. A standby current of less than
2 µA can be achieved by disabling both driver and receiver.
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and lower than the negative input threshold, VIT–, the receiver output turns low.
If VID is between VIT+ and VIT–, the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
3M
1.5 k 1.5 k
D, RE DE R
9V 9V 1M 9V
R2 R2
R1
A
A
R1 R
B
B
16 V R3 R3
16 V
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
R R R
R R R
RE A RE A RE A
DE B DE B DE B
D D D
D D D
Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to be
turned on and off individually. While this configuration requires two control lines, it allows for selective listening
into the bus traffic, whether the driver is transmitting data or not.
Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal.
In this configuration, the transceiver operates as a driver when the direction-control line is high, and as a receiver
when the direction-control line is low.
Additionally, only one line is required when connecting the receiver-enable input to ground and controlling only
the driver-enable input. In this configuration, a node not only receives the data from the bus, but also the data it
sends and can verify that the correct data have been transmitted.
R R R R
A A
RE RE
RT RT
B B
DE DE
D D D D
A B A B
R R
D D
R RE DE D R RE DE D
Common cables used are unshielded twisted pair (UTP), such as low-cost CAT-5 cable with Z0 = 100 Ω, and
RS-485 cable with Z0 = 120 Ω. Typical cable sizes are AWG 22 and AWG 24.
The maximum bus length is typically given as 4000 ft or 1200 m, and represents the length of an AWG 24 cable
whose cable resistance approaches the value of the termination resistance, thus reducing the bus signal by half
or 6 dB. Actual maximum usable cable length depends on the signaling rate, cable characteristics, and
environmental conditions.
1000
Conservative
Characteristics
100
10
100 1k 10k 100k 1M 10M 100M
Data Rate (bps)
VHYS-min
50mV
VID - mV
-70 -20 0 70
Vnoise-max = 140mVpp
(1M) (1.5k)
25
High-Voltage 150pF Device
Pulse CS Under 20
Generator (100pF) Test 15
10
5 10kV HBM
0
0 50 100 150 200 250 300
Time - ns
Figure 23. HBM and IEC-ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur due to human contact with connectors and cables. Designers may choose to implement
protection against longer duration transients, typically referred to as surge transients.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often
result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the
switching of power systems, including load changes and short circuit switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
Figure 24 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left-hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automation.
The right-hand diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
3.0
2.8
2.6 6-kV Surge
2.4
22 2.2
14 1.4
12 1.2
4-kV EFT
10 1.0
8 0.8
6 0.6
4 0.4
2 10-kV ESD 0.2 0.5-kV Surge
0 0
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
Time (µs) Time (µs)
In the case of surge transients, high-energy content is characterized by long pulse duration and slow decaying
pulse power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver
is converted into thermal energy which heats and destroys the protection cells, thus destroying the transceiver.
Figure 25 shows the large differences in transient energies for single ESD, EFT, and surge transients, as well as
for an EFT pulse train, commonly applied during compliance testing.
1000
100
Surge
10
1
EFT Pulse Train
Pulse Energy (J)
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5 1 2 4 6 8 10 15
Peak Pulse Voltage (kV)
Vcc Vcc
Vcc Vcc
10k 10k
0.1μF R1 0.1μF R1 TBU1
1 8 1 8
RxD R Vcc RxD R Vcc
TVS TVS MOV1
2 7 2 7
MCU RE A MCU RE A
XCVR XCVR
3 6 3 6
DIR DE B DIR DE B
4 5 4 5 MOV2
TxD D GND TxD D GND
R2 R2 TBU2
10k 10k
Figure 26. Transient Protections against ESD, EFT, and Surge Transients
The left-hand circuit provides surge protection of ≥500-V surge transients, while the right-hand circuit can
withstand surge transients of up to 5 kV.
0.1μF
2 1:1.33 MBR0520L 3.3VISO
Vcc D2 3 4
IN OUT
1
TLV70733
SN6501 10μF 0.1μF 3 2 10μF
1 EN GND
GND D1
10μF MBR0520L
4,5
L1 ISO-BARRIER
3.3V
N PSU 0.1μF 0.1μF
PE
0.1μF
1 16 0.1μF
4.7k 4.7k
PE Vcc1 Vcc2
2 7 10
EN1 ISO7241 EN2 8
DVcc 16 6 11 1 Vcc
UCA0RXD OUTD IND R R1
5 7
XOUT 11 3 14 2 B
MSP430 P3.0 INA OUTA RE SN65
6 F2132 12 4 13 3 R2
XIN P3.1 INB OUTB DE HVD72 6
15 5 12 4 A
DVss UCA0TXD INC OUTC D GND2
4 GND1 GND2 5 TVS
2,8 9,15
R HV C HV
Power isolation is accomplished using the push-pull transformer driver SN6501 and a low-cost LDO, TLV70733.
Signal isolation uses the quadruple digital isolator ISO7241. Notice that both enable inputs, EN1 and EN2, are
pulled up via 4.7 kΩ resistors to limit their input currents during transient events.
While the transient protection is similar to the one in Figure 26 (left circuit), an additional high-voltage capacitor is
used to divert transient energy from the floating RS-485 common further towards Protective Earth (PE) ground.
This is necessary as noise transients on the bus are usually referred to Earth potential.
RHV refers to a high voltage resistor, and in some applications even a varistor. This resistance is applied to
prevent charging of the floating ground to dangerous potentials during normal operation.
Occasionally varistors are used instead of resistors to rapidly discharge CHV, if it is expected that fast transients
might charge CHV to high-potentials.
Note that the PE island represents a copper island on the PCB for the provision of a short, thick Earth wire
connecting this island to PE ground at the entrance of the power supply unit (PSU).
In equipment designs using a chassis, the PE connection is usually provided through the chassis itself. Typically
the PE conductor is tied to the chassis at one end while the high-voltage components, CHV and RHV, are
connecting to the chassis at the other end.
RL = 60 Ω RL = 60 Ω
RL = 60 Ω
12 Layout
5
Via to ground
C 4 Via to VCC
R
6 R
R 1
JMP
MCU 7 R
R 5
TVS
6 R
SN65HVD7x 5
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 14-Aug-2014
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
SN65HVD72D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 HVD72
& no Sb/Br)
SN65HVD72DGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 HVD72
& no Sb/Br)
SN65HVD72DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 HVD72
& no Sb/Br)
SN65HVD72DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 HVD72
& no Sb/Br)
SN65HVD72DRBR ACTIVE SON DRB 8 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 HVD72
& no Sb/Br)
SN65HVD72DRBT ACTIVE SON DRB 8 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 HVD72
& no Sb/Br)
SN65HVD75D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 HVD75
& no Sb/Br)
SN65HVD75DGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 HVD75
& no Sb/Br)
SN65HVD75DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 HVD75
& no Sb/Br)
SN65HVD75DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 HVD75
& no Sb/Br)
SN65HVD75DRBR ACTIVE SON DRB 8 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 HVD75
& no Sb/Br)
SN65HVD75DRBT ACTIVE SON DRB 8 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 HVD75
& no Sb/Br)
SN65HVD78D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 HVD78
& no Sb/Br)
SN65HVD78DGK ACTIVE VSSOP DGK 8 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 HVD78
& no Sb/Br)
SN65HVD78DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 HVD78
& no Sb/Br)
SN65HVD78DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 HVD78
& no Sb/Br)
SN65HVD78DRBR ACTIVE SON DRB 8 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 HVD78
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 14-Aug-2014
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
SN65HVD78DRBT ACTIVE SON DRB 8 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 HVD78
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION
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PACKAGE MATERIALS INFORMATION
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