RAY MARSTON

THE l'l l /\Sl·> L OC' K E I> LOO P (!'LL) CIH-

CUit "locks·· the frequency and
phase of a variable-frequency
oscillator to that of an input ref-
erence . An electronic servo loop.
it provides frequency-selective
tuning and filtering without the
need for coils or inductors. a de-
sirable feature in miniature.
solid-state circuits.
This article examines the the-
ory and basic operating princi-
ples of phase-locked loop cir-
cuits. It then shows many
practical a pp! icalions for the
voltage-con trolled oscillator in-
tegrated within a monolithic
PLL circuit. Subsequent arti -
cles in this series will examine
communications and control
circuits that make use of com-
plete PLL ICs.
Figure I is the block diagram
of a basic PLL circuit. It consists
of blocks representing the
phase comparator (sometimes
called the phase-detector). low-
pass tilter (LPFJ. and a linear.
voltag e -cont rolled os c illator
(VCOJ. Prominent applications
for PLL ICs include FM demod-
ulators . frequency synthesis.
and tone decoding.
Learn about
PLL principles
The phase comparator re-
phase-locked loops (PLLJ,
ceives and compares the phase
and frequency of the circuit's
and design
output frequency (f0 ) with an communications and control
external input reference fre-
quency ([HJ. and generates a cor- circuits with them.
responding variable output er-
ror voltage.
After the error voltage is fil- verse response takes place. The Frequency multiplication
tered by the LPF. it is fed to the phase comparator's output de- In the basic PLL block di-
control input of the VCO so that creases. again directing the agram in Fig. 1. the output sig-
a ny frequency or phase dif- vco·s frequency to lock to the nal frequency locks to the mean
fe rences between)~) and_f1< are same frequency as the inpu t ref- value of the input frequency so
prngressively reduced to zero. erence. that the input and output fre-
When that occurs. the loop is The low-pass tiller is the es- quencies are identical. Figure 2
said to be locked . sential part of the PLL circuit shows a variation of that circuit
If the VCO's frequency is ini- that converts the output of the in which the output frequency
tially below that of the input ref- phase detector in to a smooth is precisely ten lim es greater
erence. the phase comparator's DC control voltage. Becau se it than the input frequency. As a
outp u t swi ngs pos it ive. Its fil- has a finite lime constan t. PLL result. the circuit a cts like a fre-
tered voltage output then com- locking is not instantan eous. quency multiplier.
m ands the VCO's frequency to and the output frequency locks In the block diagram of Fig. 2.
in crease until both its frequen - to the mean value offw rather a divide-by-ten counter is inser-
cy and phase precisely match than to its instantaneous value . ted in the feedback loop be-
those of the input reference . This characteristic is valued for tween the VCO output and the
Similarly, if the VCO's fre - producing clean outpu t fre - input of the phase comparator.
q uency increases above that of quencies from a noisy input ref- Consequently. the phase com-
the internal reference. the re- erence freq'u encies. parator locks to the output fre- 47

FIG. 1-PHASE-LOCKED LOOP (PLL) circuit.
FIG. 2-FREQUENCY MULTIPLIER circuit based on the PLL.
quency of the divide-by-ten
counter instead of the output
frequency of the VCO.
Therefore. at the lock con-
dition, the VCO's frequency !f0 )
is ten times greater than the in-
put reference signal !JI<). and
the circuit acts as a 10 x fre-
quency multiplier. This circuit
can multiply by any number
other than ten if it has a counter
with an appropriate division
ratio in its feedback loop.
Frequency synthesis.
The PLL circuit can also func-
tion as a precise programmable
frequency synthesizer (see Fig.
3). The reference input frequen-
cy of the phase comparator is a
fixed precision I-kHz signal de-
rived from a I-MHz crystal os-
ci I lator through a divide-
by-1000 counter.
As in the frequency multiplier
circuit, there is a counter in the
feedback loop between the
VCO 's output and the phase
comparator's input. However,
this circuit is externally pro-
grammable, so it can provide
any whole-number division
ratio between IOO x and
IOOO x .
This feature permits the cir-
cuit to generate or synthesize
accurate, stable frequencies be-
tween 100 kHz and I MHz in I-
kHz steps. The VCO circuit in
Fig. 3 must have a frequency
span range of at least 10 to I to
cover the required range. More-
over, the frequency step value
corresponds to the I-kHz exter-
48 nal input frequency.
High-frequency synthesis
The programmable counter is
an essential function of all fre-
quency synthesizers . Practical
counters typically respond to
maximum input frequencies of
only a few megahertz. As a re-
sult, the Fig. 3 circuit cannot
directly synthesize frequencies
higher than a few megahertz.
Figures 4 to 6 show three alter-
native versions of high-frequen-
cy PLL synthesizer circuits.
The circuit in Fig. 4 depends
on a prescaling technique. An
additional divide-by-X , fixed-
value, high-frequency counter
stage (the prescaler) is located
between the VCO output and
the input of the programmable
counter.
This configuration permits
the VCO to operate at a frequen-
FIG. 3-FREQUENCY SYNTHESIZER based on the PLL.
FIG. 4-FREQUENCY SYNTHESIZER with prescaler based on the PLL.
cy X-times higher than the pro-
grammable counter stage. In
the example shown. the pre-
scaler has a divide-by value of
20 x . giving the synthesizer the
ability to cover 2 to 20 MHz in
900 discrete steps. A disadvan-
tage is that it causes the step
value of the synthesizer to in-
crease by a ratio equal to the
prescaler value (i.e . , to
20 xjH)-20 kHz in this circuit.
In the Fig. 5 circuit, a mixer
technique synthesizes frequen-
cies between 100 and lOI MHz
in 1000 discrete steps of I kHz.
The VCO's output is mixed with
a crystal-derived 99 . 9-MHz fre-
quency before being sent
through a low-pass filter to pro-
duce a 100-KHz to I. I-MHz dif-
jerence frequency. That dif-
ference frequency then enters
the PLL and passes through the
programmable counter stages.
This scheme permits the VCO
frequency to be varied in steps
equal to thefH value, but it lim-
its the VCO"s useful span to a
few megahertz.
Figure 6 shows how the mixer
and prescaler circuits in Fig. 5
can be combined to make a
wide-range. high-frequency
synthesizer that can generate
frequencies between 100 and
I20 MHz in 1000 discrete 20-Hz
steps. The VCO's output fre-
quency is mixed with a crystal-
derived 98-MHz frequency and
put through a low-pass filter to
produce an output from 2 to 22
MHz.
2)~~
100lcHz TO 1MHz
(1kHz STEPS)
 the PLL through the program-
VOLT.11,GE"- mable counter. This synthesizer
CONTR.OLLED circuit gives excellent results .
OSCIU.ATOR

V CO operation.
The voltage-con trolled os-
iMl.ll'MHz
CRYSTAL cillator in high-frequency PLL
OSCtl.1.ATOlil synthesizers typically must
cover a very limited span range.
This function is typically per-
formed by a variable capacitor-
controlled transistor oscillator
with a buffer circuit. By con-
trast, th e VCO in low-frequency
FIG. 5-HIGH·FREOUENCY, MIXER·TYPE synthesizer based on the PLL.
synthesiz e rs typically must
cover a very wide span range.
REF
That circuit is typically a special
FREQ (rl'I - VOLTAGE· Y.::<.OUTPUT monolithic CMOS or bipolar IC
1kHz i.St. CONTROllID · ~! FREQ oscillator.
fR OSC1UATO~ 100 TO 120MHZ
(20kHZ STEPS)
Some monolithic PLL inte-
'o grated circuits contain excel-
98.0MHi
lent wide-range VCOs that can
CRYSTAL be used by themselves in prac-
OSClt LAi'ElR tical circuits. An example is the
popular Harris CMOS
CD4046B. widely alternate-
sourced by many other man-
ufacturers including Motorola.
National Semiconductor. Phi-
FIG. 6-WIDE·RANGE, HIGH-FREQUENCY synthesizer based on the PLL. lips. and SGS-Thomson. It is
also made with HC and HCT
SIGNAL CMOS technologies.
IN vDD

16 The CD4046B PLL IC .

Figure 7 is the block diagram
for the CD4046B that includes
PHASE external components . It con-
COMPARATOR I
2 PHASE COMP I OUT sists of a low-power. linear. volt -
age-controlled oscillator (VCO).
a source-follower. a Zener diode.
13 and two phase comparators .
PHASE COMP II OUT The two phase comparators
1
have a common signal input
PHASE PULSES and a common comparator in-
R3 put. The signal input can be di-
rectly coupled for a large voltage
signal. or capacitively coupled
to the self-biasing amplifier for
g VCOIN LOW
.....- - - - - -1---0------ - -.. PASS a small voltage signal
FILTER Phase comparator I. an ex-
C2
clusive OR gate. provides a dig-
,10 DEMODULATOR ital e rror sig nal (PHAS E COMP 1
-, OUT
ouT) and maintains 90° phase

~Rs
I
Vss shifts at the VCO center fre-
quency. Between signal input
and comparator input (both at
t 50% duty cycle). it can lock onto
Vss the signal input frequencies
8 15 that are close to harmonics of
Vss ZENER the VCO's ce nter frequen cy. It
offers good noise-rejection per-
FIG. 7-BLOCK DIAGRAM for the CD4046B PLL IC showing its external components formance. but must be driven
and connections.
by square waves on both pins 3
That output is then reduced by a divide-by-20 pres c al er and 14. It has only a narrow cap-
to the 100-kH z to 1. 1-MHz range stage before it is fed back in to t u rc-f requency range . 49

1 16 Voo
PHASE PULSES
2 15 ZENER
PHASE COMP I OUT
3
1' SIGNAL IN
COMPARATOR IN
4 13 PHASE COMP II OUT
VCOOUT
INHIBIT S .12 R2
CIA 6 11
Rt
Cle 7 'l O DEMODULATOR
Vss e g VCO IN
FIG. 8-PINPOUT DIAGRAM for the
CD40468 PLL IC in a 16-pin dual-in-line
package.
+9V C1
0.1
vco
OUTPUT
FIG. 9-SQUAREWAVE GENERATOR for
200 Hz to 2 kHz.
Phase comparator II. an edge-
t riggered digital memory net-
work, provides a digital error
signal (PHAS F: COMP II OUT) and
lock-in signal (phase pulses) to
indicate a locked condition. It
maintains a 0° phase shift be-
tween the signal and com -
parator inputs. It can be driven
by crude , non-symmetrical
waveforms on pins 3 and 14. Al-
though it has a very wide cap-
ture-frequency range, it has
poor noise rejection .
The VCO produces an output
signal (vco ouT) whose frequen-
cy is determined by the voltage
at pin 9 (vco IN) and the input
and the capacitor between pins
6 and 7 (CIA and Cl 8 , respec-
tively) and resistors Rl and R2
at pins 11 and 12 (m and R2,
respectively). Resistor R2 per-
mits the minimum operating
frequency to be preset. The VCO
generates a symmetrical
squarewave output that ap -
pears on pin 4 (vco ouT).
The source-follower output of
the VCO IN (DEMODULATOR ouT)
is used with an external resistor
50 whose value is 10 kilohms or
more. When high, the INHIBIT
input disables the VCO and
source-follower to minimize
standby power consumption.
The Zener diode between pin 8
(V 55 ) and 15 (ZENER) has a nomi-
nal operating value of 5.6 volts:
it can provide supply regula-
tion, if required.
OU~ Pin 9 has a nearly infinite in-
put impedance. It c·an be driven
from a high-impedance source.
The internal source-follower
stage permits the voltage at pin
9 to be externally monitored
without loading the source. Pin
5 (1N111rnT) is normally connected
to pin 8 to enable both the VCO
and the source-follower.
+9V C1
0.1
R1
100K VCO
i SET OUTPUT
FREQ)
FIG. 10-WIDE-RANGE VCO, variable
from near-zero to 1.4 kHz by adjusting
the voltage on pin 9.
01
1N4148
R1
100K
,, FREQ)
...I..
..,..
FIG. 11-WIDE-RANGE VCO fully varia-
ble down to zero frequency
Figure 8 is the pinout di-
agram for the CD4046B in a 16-
pin dual-in-line package. It will
operate over a supply voltage
range (V 00 ) of 3 to 18 volts. Typ-
ical power consumption is 70
microwatts. and its VCO fre-
quency is typically 1.3 MHz. The
CD4046B has a maximum oper-
ating frequency of about 1. 6
MHz.
VCO applications
Figures 9 to 17 show various
ways to make practical use of
the voltage-controlled oscillator
section of the CD4046B. In Fig.
9, pin 9 is permanently con-
nected to tl1c supply so that the
circuit acts as a basic square-
wave oscillator. Its frequency is
variable over a 10 to 1 range by
adjusting trimmer potentiome-
ter Rl. ·
Pin 4 is tied directly to pin 3
(COMPARATOR IN). If pin 3 is al-
lowed to float, the comparators
self-oscillate at about 20 MHz,
and superimpose a high-fre -
quency on the VCO output
waveform.
Figure 10 shows how to con-
nect the CD4046B as a wide-
range VCO. Resistor R2 and ca-
pacitor Cl set the maximum fre-
quency that can be obtained,
and trimmer potentiometer Rl
controls the frequency through
the pin 9 voltage. The frequency
falls nearly to zero (at a rate of a
few cycles per minute) when pin
9 is set at zero volts.
The effective control range of
pin 9 varies from about 1 volt
above zero to 1 volt below the
positive supply value (e.g., po-
R1
100K vco
OUTPUT
(FREQ)
R2 R3
4.7MEG 100K
FIG. 12-RESTRICTED-RANGE VCO,
variable from 60 Hz to 1.4 kHz with trim-
mer potentiometer R1.
+9V
R1 vco
100K OUTPUT
(FREQ)
FIG. 13-ALTERNATIVE RESTRICTED-
range VCO.
tentiometer Rl has a "dead"
control region of several hun-
dred millivolts at either end of
its span.)
Figure 11 shows how the
R1
100K
(FREQ)
FIG. 14-A TWO-PHASE, WIDE-RANGE VCO.
"dead" regions of Rl ::: an be ating frequency can be reduced
eliminated by placing a silicon to zero by connecting 10-
diode in series with each end of megohm resistor R2 from pin 12
Rl (Dl and 02). The circ·.iit also to pin 16 (V00 ). When the fre -
shows how the minimum oper- quency is reduced to zero, the
VCO output randomly settles to
either the Iogic-0 or Iogic-1
+9V C1 state.
0.01 Figure 12 shows how the re-
sistor at pin 12 can also be con-
OUTPUT2 nected to pin 8 to set the
6 7
r""""......._.....__~=-----o i_n_r u ... minimum operating frequency
I ' I t I •
1 I I I I '
of a restricted-range VCO. The
L...--.-__.l-'--*---0 Art.ft
OUTPUT1
minimum frequen cy is deter-
mined by the combi nation of R2
R2 and Cl. and the maximum fre-
100K quency is determined by Cl and
the parallel value of R2 and R3 .
Potentiometer RI can vary the
frequency range from 60 Hz to
1.4 kHz.
C1
Figure 13 shows an alter-
+9V native version of the restricted-
0.01 PRESS S1

R2
J~ L range VCO. Its maximum fre-
quency is controlled by R2 and
16 6 7 3
100K C l. and the minimum frequen-
R1
1OOK
(FREQ)
9
>-1;--- +- - 1 C04046B
4
vco
n_ cy is controlled by Cl and R2
and R3. With a suitable choice
OUTPUT of values for R2 and R3. the re-
stricted-range VCO can span
a.ny range from 1 to I to near
infinity.
The VCO can be set up to gen-
erate a pair of squarewave out-
FIG.15-MANUALLY GATED wide-range VCO. puts 180° out-of-phase by con-
necting the '{CO ou tput to the
+9V C1 phase comparator input. mak-
O.Q1 ing pin 14 (SIGNAL IN) high. and

6
r 7
taking the 180° out -of-phase
output from pin 2. as shown in
Figure 14. This circuit takes ad-
C04046B
vantage of the integrated cir-
5 8 11 cuit's built-in exclusive OR gate
at pin 2.
As shown in Fig. 15. the VCO
R3
100K
section of the CD4046B can be
disabled by connecting pin 5
high to logic 1. This feature per-
FIG. 16-ELECTRONICALLY GATED, wide-range VCO with an external gate inverter. mits the VCO to be gated on and
off by external signals. The VCO
C1 GATE can be manually gated with
+9V INPUT pushbutton switch SI that is
0.01

SL connected between pin 5 and

---
16
ground.
14
Figure 16 shows how the VCO
CD4046B can be gated electronically by an
4
vco
external inverter stage. one-
2 5 8 11
OUTPUT fourth of a CD4011B. a CMOS
GATE NANO gate. Alternatively. if you
INPUT do not need two-phase ouput
R3
100K capability. Fig. 17 shows how
the internal exclusive OR phase
detector can control the gate. In
FIG. 17-ELECTRONICALLY GATED, wide-range VCO with an Internal exclusuve OR this circuit. pin 4 is not con-
phase detector to permit gate inversion. nected to pin 3. !l 51
 RAY MARSTON

THIS ARTIC LE PICKS UP WHERE LAST

month's article on phase-locked
loops left off. Last month the
basic principles of the phase-
locked-loop were explained and
the functional sections of a pop-
u I a r CMOS PLL IC, the
CD4046B were described. The
circuits presented in that arti-
cle showed various ways to con-
figure the voltage-controlled os-
cillator (VCO) section of the
CD4046B for practical frequen-
cy-dependent applications.
Sound-effects generators
The versatility of the VCO sec-
tion of the CD4046B IC was ex-
plained last month. Its operat-
ing frequency can be swept over
a very wide range under the con-
trol of voltages applied to pin 9.
Moreover, its output can be
gated on or off with a voltage
applied to pin 5 . These charac-
teristics make the CD4046B
suitable as the principle compo-
nent in many different circuits
for sound-effects generation.
Figures I to 6 are schematics for
sound-effects generators.
The circuit in Fig. I can emit a
conventional siren sound. It Experiment with these
produces a tone that rises slow-
ly to a maximum value when Sl phase-locked loop circuits, and put
is closed, and falls slowly from
that maximum to silence when them to work in your designs.
SI is opened.
This response is caused by
the voltage on Cl that is applied through C4 and transistor QI. charges through RS. The cycle
to voltage-control pin 9. It rises Figure 2 shows how the Fig. I is repeated again on the arrival
exponentially through RI when circuit can be modified to give a of the next pulse .
SI is closed, and falls exponen- quick response in which the fre- Figure 4 shows a different
tially through R2 when SI is quency rapidly switches to its kind of sound-generator circuit
opened. Resistor R3 ensures maximum value when SI is that can generate either a
that the operating frequency closed (as Cl discharges expo- pulsed or warble tone, depend-
falls to zero when the voltage at nentially through R3). Figure 3 ing on the setting of S2. Push-
pin 9 is zero. The VCO output is shows another circuit modifica- button switch Sl simulta-
AC coupled to the speaker tion that generates a "phasor" neously enables pin 5 of the
sound (similar to that heard CD4046B to gate on the
aboard the starship Enterprise CD4001B astable multivibrator
in the Star Trek TV series) when which, in tum, applies a rec-
pushbutton switch Sl is dosed. tangular (alternately fully-high
In this circuit, the CD4011B IC and fully-low) waveform to the
is configured as an astable IC's pin 9.
multivibrator that is gated In the pulsed mode. the VCO
through SL It produces a chain generates zero frequency when
of 4 millisecond pulses at inter- pin 9 is low, but in the warble
vals of 70 milliseconds. mode it generates a tone that is
Each pulse rapidly charges 20% lower than the high tone
capacitor C2 through R3 and generated when pin 9 is low.
FIG. 1-ELECTRONIC SIREN CIRCUIT 02 to produce a high tone Figure 5 is a circuit that pro-
based on a CMOS CD4046B PLL IC. which decays slowly as C2 dis- duces a special-effects run - 69

FIG. 2-0UICK-START SIREN CIRCUIT
based on a CD404668 PLL IC.
down clicking sound like that of
the big "wheels of fortune" seen
in television game shows. The
time between clicks is constant
after pushbutton switch Sl is
pressed. However, whenSl is re-
leased, the time between clicks
increases as the "wheel" appar-
ently slows to a standstill. The
circuit operates as follows:
When PBl is pressed, Cl
9VTO 12V
rapidly charges to a high voltage
through 02. Simultaneously.
Q 1 is biased on through the
combination of 03 and R4.
which connects R6 between pin
11 and ground. This makes the
VCO operate at tens of kilohertz.
effectively generating a random
number of clock pulses.
When Sl is released, Ql is
turned off and the timing of the
VCO is governed by R7. At the
same time, Cl discharges
rapidly to half the value of the
supply voltage through RI. R2
and 01. This discharge causes

' }~
R6 the VCO to operate at about 100
10MEGc3 Hz. Capacitor Cl then slowly
0.1
T TOTAL.
discharges through R3. and the
16 7 VCO frequency slowly decays to
zero in about 15 seconds.
CD4046B
The output of the circuit in
5 t1 cs
Fig. 5 can directly clock most
4ml PULSES AT 0.1 counters. It can be directly cou-
70ms INTERVALS pled through R9 to an external
crystal or ceramic transducer to
RS R7 R8 produce low-level run-down
1MEG 12K 12K sounds.
The circuit's output can settle
in either the logic-zero or logic-
FIG. 3-PHASOR-SOUND GENERATOR circuit based on a CD404668 IC.
one state when the run-down is
9V TO 12V complete. Therefore. the output
should not be DC coupled to cir-
C1 R1 cuits such as power amplifier
O.l 3.3MEG stages.
Figure 6 is a schematic show-
ing how the circuit in Fig. 5 can
be modified to ensure that its
output always settles in the log-
ic-zero when run-down is com-
plete. This modification make
S1 .J the circuit safe for direct-coup-
(OPERATE) r') ling the output to power ampli-
fier stages.
In this circuit, the CA3140
operational amplifier is config-
ured as a voltage comparator. It
FIG. 4--COMBINED PULSED /WARBLE TONE alarm generator based on the CD40468. is set up to turn the VCO off
automatically and drive its. out-
+9V " put low through pin 5 when the
voltage at pin 9 falls below a ref-
~o s1
SPIN erence value of about 2 volts. (It
RS
10MEG
C2 is set on pin 3 of the op-amp).
0.01
D2 D3
1N4148 1N4148 12 ,16 Special VCO circuits
The VCO section of the
01 OUTPUT
CD4046B is so versatile that it
R4 lends itself to a wide variety of
1N4148
47K R9
+ 820!.) special-purpose waveform gen-
R6 erator applications. Figures 7 to
C1 10K
10µF SOUND OUTPUT TO 9 are examples of these circuits.
R3
1MEG
R7 CRYSTAL OR CERAMIC The circuit in Fig. 7 is a sim-
1MEG TRANSDUCER
plejrequency shift keyed (FSK)
square-wave generator. With
70 FIG. 5-RUN-DOWN CLOCK/SOUND generator circuit. the component values shown in
 to a wide-range, universal.
squarewave "clock" generator
that covers the nominal range
0.5 Hz to 500 kHz in three
switch-selected bands. This cir-
cuit can be a useful" test instru-
ment that provides a two-phase
OUTPUT output . It can operate in either
the free-funning or the gated
R7
modes.
10K
R4 R6 RB Phase-locked circuits
1MEG 471( 1MEG The basic operating princi-
__. ples of the CMOS phase-locked
loop (PLL) IC were explained last
FIG. &-MODIFIED RUN-DOWN generator circuit. month. You should review that
C1 10V TO 15V
+9V 0.01 C3
100pF
R2 1~4
471< 1MEG

R1 FM
1MEG OUTPUT
C2 R3
0.22 47K

FIG. 7-FREQUENCY SHIFT KEYED

(FSK) generator. Logic O = 1.2 kHz and FIG. 8-FREQUENCY MODULATOR CIRCUIT generates 220 kHz.
logic 1 = 2.4 kHz.

this figure, the circuit will gen-

erate a tone frequency of 2.4 C2
kHz when a logic-one signal is 1µF
ajpplied to pin 9. It will also gen- POLYESTER SWITCH St RANGES
+9V
erate a 1.2-kHz tone when a log- 1. 5 T050Hz
2. SOHz TO SlcHz
ic-zero signal is applied to the 3. 5 TO SOOllHz
same point. 01
...--~

The high-frequency tone is 1N4148

OUTPUT ~
set by the values of Cl and R2, A6 2 ; l : : : :
and the low-frequency tone is 22K Loo >--~~-"'! CD4046B t l I I I I

(I)
set by the values of Cl. R2, and OUTPUT_H_H__H_
R3. Other frequencies can be GATE 5 1
INPUT
obtained by altering those com- RS
10MEG
ponent values.
The circuit in Fig.8 is a 220-
kHz frequency modulation (FM) R1 R3 R4
02 22K
waveform generator. The inter- 100K 1N4148 47K
nal Zener diode at pin 15 of the
CD4046B provides a stable FREE-RUN
0
power supply for the CD3140
op-amp, which is configured as GAT
a multiply-by-20 inverting AC FIG. 9--UNIVERSAL CLOCK/SQUAREWAVE generator.
amplifier. It has a quiescent bias
of about 2.6 volts applied to its age-control input terminal pin 9 article unless you have a clear
non-inverting A input at pin 3 of the CD4046B"s VCO . The understanding of those princi-
through R2 and R3. component values of C3 and R6 ples before you work with the
As a result, output pin 6 of the were selected so that it gener- circuits presented in the re-
op-amp produces an approxi - ates a mean output '"carrier'"fre- mainder of this article. They
mate 2.6-volt potential that is quency of220 kHz. This output will make use of all of the PLL's
amplitude modulated with an frequency is modulated by the circuitry.
amplified ( x 20) version of the original AF input signal. Figure 10 shows the
audio frequency input signal. Figure 9 shows how the CD4046B organized as a wide-
This output is applied to volt- CD4046B VCO can be converted range signal tracker. It will com- 71
 +9V i i 11 voo
'IN J LJ L OV
, , I ,
t I I I
13 16 I I I I v

'ourn _ r roo
PHASE I ov' I I

u--+-<~ COMPARATOR VCO

14
I ' I I
2 I I ' I
II
PIN1 ~Voo
OUTPUT -- - -- -- ~ - OV
3 11
four
PIN2 J [ ----w-t2DD
R1 C1 OUTPUT I OV
100K 180pF

......- . - -.:IM!lli.
FIG. 1G-WIDE·RANGE PLL SIGNAL TRACKER showing waveforms obtained when
the loop is locked.

+9V FIG. 14-FREQUENCY SYNTHESIZER

PIN1 covers a 1 to 9 kHz range.

f ROM to that obtained with pin 9 at

CD40468
{ the supply voltage (V00 ).
PIN2 LOCK
OUTPUT
*TIE ALL UNUSED INPUT PINS
18.9.12. &13) TO GROU,NO
FIG. 11-PHASE·LOCKED LOOP "lock" dectector/indicator.
+9V fREGUlATED)
C2
0.1
6 7
C1
0.01
FIG. 12-PRECISION NARROW-BAND TONE SWITCH has a range of 1.8 kHz to 2.2 kHz.
.ov 1A£Gul.Ar!D) This circuit (and the others
shown here) takes advantage of
the internal wide-range phase
comparator II. This circuit per-
mits it to lock to any signal
within the "span" range of the
VCO. The filter formed by R2,
•IV (REGULATE>)"" R3, and C2 is organized as a
sample-and-hold amplifier in
this operating mode. lts compo-
nent values determine the set-
tling and tracking times of
s ignal capture.
FIG . 13-A LOW FREQUENCY x 100
The VCO's operating frequen-
multiplier/pre-scaler circuit.
cy is determined by the values of
RI and Cl and the voltage on
pute and track any input signal pin 9. The VCO "span" (and
from 100 Hz to 100 kHz, pro· thus the capture and tracking
vided that the input signal to range of the circuit) ranges
pin 14 switches fully between from the VCO frequency value
72 the zero and one logic levels . obtained with pin 9 at zero volts
Figure 11 is a simple lock de-
tector/indicator circuit that can
be used in conjunction with the
PLL circuit of Fig . 10. ln the
PLL, the output of each phase
comparator is a series of pulses
whose ·w idths are proportional
to the difference between its two
input signals.
The output of phase com-
parator I is normally low, and
that of phase comparator II is
normally high, except for these
pulses. When the PLL circuit is
locked (see Fig. 10), the two out-
puts are almost perfect mirror
images of each other.
In the lock detector/indicator
circuit of Fig. 11, those features
are implemented through two-
input NOR gate ICI-a. which is
driven from the outputs of the
two comparators . If the loop is
locked, the ICI -a output re-
mains permanently low, thus
driving ICI-b output high and
turning on LEDL
If the loop is not locked. how-
ever, the ICI-a output is formed
as a series of positive-going
pulses that rapidly charge Cl
through DI and RI. This forces
IC l -b low and holds LEDI off.
Figure 12 shows how a PLL
circuit can be combined with a
lock indicator to form a preci-
sion narrow-band tone switch.
The VCO's maximum frequency
is determined by RI and C 1, and
the minimum frequency is de-
termined by RI, R2. and Cl.
The frequency is variable
from about 1.8 kHz to 2.2 kHz
with the component values
shown in Fig. 12. The circuit
can only lock to input signals
within this frequency range.
Figures 13 and 14 are sche-
matics for several practicalfre-
quency multiplier circuits. The
circuit in Fig. 13 serves as a
multiply by 100 frequency mul-
tiplier/pres cal er that can
change 1 Hz to 150 Hz input sig-
nals into 150 Hz to 15 kHz out-
put signals.
The circuit in Fig. 14 is a sim-
ple frequency synthesizer: It is
fed with a precise (crystal-de-
rived) 1-kHz input signal. and
its output is a whole-number
multiple (in the range x 1 to
x 9) of this signal. The
CD401 7B is organized as a pro-
grammable divide-by-N counter
in this application . A single
CD40 l 7B can be replaced by a
series of programmable decade
counters to form a wide-range
(10 Hz to 1 MHz) synthesizer. n
NIGHT VISION SCOPES
continuedfrom page 62
chase a suitable IR filter at most
retail camera stores. or you can
stack four or five layers of com-
pletely exposed, developed film
negatives between the incan-
descent lamp and flashlight
lens. This film can be obtained
as scrap from local photo de-
veloping shops. Cut four or five
disks from this exposed film to
fi. t inside the plastic or glass
lens cap of your flashlight.
A complete kit of parts to
build both of the scopes de-
scribed in this article can be ob-
tained from the source given in
the parts list. If you elect to buy
a surplus image tube to make a
night-vision scope from
scratch, purchase or obtain a
"fast" camera lens and a magni-
fying glass for use as an eye-
piece. You can then assemble all
of these parts in a suitable met-
al or plastic tube. The power
supply described here will
power most imaging tubes, re-
gardless of their size or country
of origin . n 8
FUNCTION GENERATORS Note: A copy of B&K Precision's
continuedfrom page 50 Guidebook to Funcclon Gener-
ators will be sent to any reader free
of charge by addressing a request
In writing to Guldeboc k. B + K Pre-
cision. 64 70 West Cortland Street.
Chicago. IL 60635.
I
," nature represents the forward
, ," voltage drop. The vertical part of
the signature represents the for-
ward current, and the horizon-
, tal part represents the reverse
voltage drop.
In the waveform for the Zener
diode in Fig. 9-d, the forward
a current is a function of the for-
ward voltage. But when the re-
,.. ~ ......
verse voltage equals the PN
junction breakdown voltage. re-
'~ "' , ~~
verse current increases rapidly.
producing a vertical line in the
lower left quadrant of the
" ............... _
I~
J
screen. This line is the break-
over point or Zener voltage, and
it is established by the knee in
the signature.
The signature techn ique can
b be applied to test and explain
the operation of all electronic
components. It is simple to use.
it can speed troubleshooting.
I and it works well on unpowered
circuit boards . Even electronic
service centers operating under
tight budget constraints can af-
ford this method.
It is worth noting that two
functionally identical lCs which
c seem to be operating normally
can have different pin sig-
natures because of differences
in chip fabrication. You might
I encounter this when testing
j
,
I functionally identical IC's from
different manufacturers. Dif-
ferent signatures do not neces-
I sarily indicate a device fault.
,
I With experience in the careful
interpretation of signatures,
signature analysis can help you
d
to identify defective compo-
nents quickly-even those with
marginal problems. Defective
ICs (open-circuited or short-cir-
cuited) can be isolated rapidly
by persons with little or no expe-
rience doing this. n
FIG. 9-NORMALIZED CURRENT VS.
VOLTAGE SIGNATURES for electronic
components : resistor (a), Inductor or ca-
pacitor (b), silicon signal diode (c), light-
emitting diode (d), and Zener diode (e). 73

HON E.-CALL RESTRICTO
continuedjrom page 56
prototype unit. Run the wires
through the slots and assemble
the two halves of the case.
Operation
Locate a suitable phone jack
in your home or business and
plug in the phone cord of the
Telephone Call Restrictor. Put it
in a location that is not accessi-
ble to those whose phone access
you wish to control, and plug
the wall adapter into an AC out-
let.
Refer to Tuble 1 for the set of
programming commands that
can be entered from your Touch-
Tone phone. Initially, before pro-
gramming, set the call restric-
tor to the ''.Allow Group" mode.
Because there have not been
any numbers entered into the
EEPROM. all numbers that
someone attempts to dial will be
blocked. Pick up the phone and
NOW Find the Right Part for Your VCR!
w!~e ISCET VCR CROSS REFERENCE
NEW! Th e Fourth Edition is contained on a
dis ke tt e for IBM PC AT/XT compati bles ,
DOS 2.1 or higher. The disk software allows
technicians to search by manufacturer for
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bers. A parts editing sequence gives an on-
screen view of all substitute s for parts en-
tered. With the diskette , the technician can
update fil es by add ing mod el and parts
1 New York State residents must add
applicable local sales tax to total.
74 L
'----------------------------------~------------
try to dial any number. You
should hear a tone after press-
ing the first digit, and a busy
signal will be placed on the line
to prevent you from completing
the call. If that does not occur,
the call restrictor is not operat-
ing properly.
Make a list in advance of the
telephone numbers that you
want to either block or allow. If
you want to add or remove num-
bers. that list will come in
handy. When programming the
unit, LEDl will light imme-
diately prior to the input of tele-
phone numbers and/or pass-
word. indicating thatthe cur-
cui t is in the programming
mode and that a valid password
has been entered (if applicable).
Until you decide on a password
and have entered it into the
EEPROM. omit this number
wherever it appears in the pro-
gramming sequence in Tuble 1.
Be careful not to enter a pass-
word and then forget the
number. If that occurs. you will
The 320-page, Fourth Edition of the VCR
Cross Reference contains both model
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1300 new parts and 360 new models have
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VCR 's are made in a few factories from
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listings from a monitor or printed page.
have to replace the EEPROM
with a blank chip.
The EEPROM has enough
memory to hold 248 characters
including the # sign which sep-
arates the telephone numbers.
You can enter full 7- or ll-dig-
it numbers. or you can enter
partial numbers such as 786 ,
and all numbers beginning
with that prefix will be consid-
ered part of the list. A prefix can
be any length; entering 1-900
will add all 900 numbers to the
list, while entering 1-9 will add
all numbers beginning with 1-9
(1-900, 1-976, 1-905, etc.).
At any time you can bypass
the call r e strictor from any
phone on the lin e simply by
pressing #. your password, and
then hanging up. The unit is
then disabled until the next call
is made, and is re-enabled upon
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trol of your phone, and your bill,
whether at home or at work. n
Only $36.00 tor pages
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RAY MARSTON

THIS IS THE TlfIRD ARTICLE IN A SE-

ries on phase-locked loop and
related circuits. It focuses on
the monolithic NE565 phase-
locked loop and the NE566
function generator, both prime
sourced by Philips (Signetics)
but alternate sourced by at least
four other multinational sup-
pliers . The electrical charac-
teristics of these two PLL !Cs are
described, and their block di -
agrams are presented. Circuit
schematics based on these de-
vices are included for learning
and experimentation.
The last two articles in this
series explained the basic oper-
ating principles of the phase-
locked loop and examined ap-
plications for the popular
CD4046B PLL IC.

The NE565 PLL IC

The NE565 is a general pur-
pose monolithic PLL used in cir-
cuits for frequency-shift keying
(FSK), telemetry receivers. tone
decoders, and FM discrimi -
nators, to mention just a few.
Figure 1 shows the principal
functional blocks of the NE565 :
phase detector (comparator).
amplifier. stable voltage control
oscillator (VCO). and low-pass
filter. The self-contained adapt-
able filter and demodulator
cover a frequency range of0.001
Hz to 500 kHz.
The center frequency of the
NE565 is determined by the
free-running frequency of the
+V
INPUT PHASE
DETECTOR
0
5 a result, its VCO can ·t function
4 NE565
0
Jl__f
vco
8
9--/\/V\
R C1
v~----
+v TIMING
FIG. 1-BLOCK DIAGRAM OF THE NE565 phase-locked loop IC.
Learn more about designing with
phase-locked loop circuits in this
continuation of last month's article
VCO. This frequency can be ad-
justed externally with a resistor
or capacitor. The low-pass filter.
which determines the capture
characteristics of the loop, is
7
AMPLIFIER l--'INlr- --+:-..__.r. oEMOD. OUTPUT
,_____ ___,,__
3
.G_
OK_--+--~6- - r REF. OUTPUT
-V
formed by an internal resistor
and an external capacitor. Fig-
ure 2 is the pinout diagram of
the most popular plastic, 14-pin
DIP package for the NE565.
The NE565 is not as versatile
as the CD4046B because the
voltage control tnput pin of its
VCO section is permanently
tied to the amplifier output
through the internal 3.6-kil-
ohm filter resistor (see Fig. l ). As
separately from the rest of the
device. While the NE565 works
well in many of the same ap-
plications as the CD4046B, un-
like that PLL device, it is not
recommended as a general-pur-
pose signal generator.
Figure 3 is the the schematic
for an NE565 with external
components organized as a sig-
nal tracker or FM demodulator.
The PLL is powered by a split 12- 63
 volt ( + 6-volt and - 6-volt) unused pin 3 is grounded.
power supply. T~e external sig- Output pin 4 of the VCO is
nal input to be tracked or de- tied to pin 5, the phase detec-
modulated is typically con- tor's input terminal. to complete
nected to input pin 2 of the the phase-locked loop. The free-
phase detector of the PLL, while running frequency lf0) of the
VCO can be adjusted with the
RC network connected to pins 8
TOP VIEW
and 9 so that it corresponds to
the mid-range value of the exter-
NE565
14 nal input signal.
V- NC
Under those conditions, the
VCO's frequency can "lock'" to
2 13
INPUT NC the input signal. This frequen-
cy lock condition occurs be-
3 12 cause the mean DC level of the
INPUT NC
phase detector's amplified out-
4
VCO OUTPUT NC
1f put is directly proportional to
the difference between the in-
5 PHASE
V+
10 put and VCO frequencies, and it
COMPARATOR
VCOINPUT can act to voltage control the
6 REFERENCE EXTERNALC 9 VCO input.
OUTPUT FORVCO As a consequence. if the input
7 DEMODULATED EXTERNAL R 8
frequency rises above that of the
OUTPUT FORVCO VCO. the detector's output also
rises and automatically drives
the VCO's frequency toward
FIG. 2-PINOUT DIAGRAM of the NE565. that of the input until locking
occurs.
The single-pole loop filter
~----<11---- +6V
formed by capacitor C3 (be-
tween pins 7 and 10) and the
R1
internal 3.6-kilohm resistor at
pin 7 causes a short time delay.
Therefore, if the input signal is
noisy, has jitter, or is frequency
modulated (FM), the VCO locks
to the mean frequency of the
input signal and generates a
"clean" output at pin 4 or 5.
This produces a demodulated
FM output at pin 7. The 0.001
µF capacitor (C2) connected be-
tween pins 7 and 8 assures cir-
cuit stability.
NE565 characteristics
Table 1 summarizes the lead-
ing characteristics of the
NE565. The IC is normally con-
figured with a split (positive and
negative) power supply, which
must be between ± 6 and ± 12
volts, but it can also be powered
by a single-ended + 12 to + 24-
volt supply.
The phase detector section of
the IC has a typical input im-
pedance of 10 kilohms on each
terminal. The IC can lock and
track to input impedance of 10
kilohms on each terminal, and
lock and track to input signals
with amplitudes as low as 1 mil-

TABLE 1-ELECTRICAL CHARACTERISTICS OF THE NE565

8 10 Parameter Min Typ Max Unit
2
DEMODULATEO
Supply voltage ±6 ±12 v
EXTERNAL OUTPUT Input impedance 5 10 kn
SIGNAL
INPUT REFERENCE
Input level for tracking 10 mVRMS
NE565 OUTPUT VCO Characteristics
3 4 Center frequency 500 kHz
JU
vco
Drift with temperature 300 ppm/°C

19 1
OUTPUT

--6V
Drift with supply voltage
Triangle wave
0.2 1.5 %/V

,/V'V C1
Output voltage level 1.9 2.4 3 Vp-p
Linearity 0.5 %
FIG. 3-EXTERIOR COMPONENTS for a
signal trackerand FM-demodulator. Square wave
Logic "1" output voltage +4.9 +5.2 v
Logic "O" output voltage -0.2 +0.2 v
Rise time 20 ns
Ir v' V' Fall time 50 ns
I\. I/ I\ I/
,,._\ I/
Output current (sink) 0.6 mA

. - ..-
~
' Output current (source) 5 10 mA
+6
..,. Demodulated output
~ ~ +4
0.. CJ)
Output voltage level 4.0 4.5 5.0 v

-
I-~ +2 Maximum voltage swing 2 Vp-p
:::>o
i= c o
:::J
0 -2 "" -~ .. .... Output voltage swing
Total harmonic distortion
200
0.4
300
1.5
mVp-p
%
+V =-V=6V
Output impedance 3.6 kQ
FIG. 4-VCO OUTPUT WAVEFORMS for Offset voltage (pins 6 to 7) 50 200 mV
the NE565 with a plus and minus 6-volt AM rejection 40 dB
64 power supply.
 livolt RMS. Normally. input sig-
nals should be AC coupled, but
they can be DC coupled if the
DC resistances seen from pins 2
and 3 are equal and there is no
DC voltage difference between
those pins.
The high stability of the
NE565's VCO can be seen in its
typical drift with temperature
specification of 300 ppm/°C and
its typical drift with supply volt-
age specification is 0. 2 % per
volt when the supply voltage is
± 6 to ± 7 volts. Both of these
values are measured atj 0 • FIG. 5-FREQUENCY SHIFT KEYING (FSK) demodulator circuit.
The VCO provides well
formed. TTL-compatible square
waves and triangle waves, as
shown in Fig. 4. Those wave-
forms were obtained with the IC
powered by a split 12-volt sup-
ply. The square waves, with typ-
ical rise and fall times of 20 and
50 nanoseconds, respectively,
appear at pin 4, and highly lin-
ear triangle waves appear at pin
9 of the VCO.
The VCO's free-running fre-
quency {f0 ) is set by trimmer po-
tentiometer R3 in series with
the + 6-volt power source be-
tween pins 8 and 10 and by ca-
FIG. 6-60 kHz FM DEMODULATOH with a single-ended power supply.
pacitor Cl in series with the
- 6-volt power source between
pins 9 and 1. That frequency in
kilohertz can be calculated as:
j 0 = 1.2/(4 RC)
where R is in kilohms and C is SCHMID
TRIGGER
in micofarads.
Resistor R3 can have any val-
ue between 2 and 20 kilohms,
but the optimum value is about
5 kilohms. Capacitor Cl can
have any value. Normally, the
NE565 will phase-lock to any in-
put signal frequency that is
within the range of plus or
FIG. 7-FUNCTIONAL BLOCK DIAGRAM OF THE NE566 function generator.
minus 60% of thej0 value. This
is known as the circuit's lock
range. FSK demodulator GROUND v+
The output section of the IC Frequency shift keying (FSK)
yields a demodulated output at is widely accepted in digital NC NE566
pin 7, and pin 6 gives a DC refer- communications systems. The SQUARE WAVE
ence voltage that is close to the transmitter generates a contin~ OUTPUT
R1

DC potential of pin 7. If a re-
sistor is placed between pins 6
and 7, the gain of the IC's out-
put stage can be reduced with
with little change in the DC volt-
age level of the output. This al-
lows the lock range to be
decreased to a value as low as
20% ofj0 , with little change in
thef0 value.
uous two-tone carrier signal TRIANGLE WAVE MODULATION
from binary signals with a mark OUTPUT INPUT .
or logic 1 state represented by
one tone and the space or logic FIG. 8--PINOUT DIAGRAM of the NE566
0 state represented by another function generator.
tone. An FSK decoder in the re-
ceiver converts the two-tone car- coder of a 1070-Hz to 1270-Hz
rier back to a binary signal. input waveform. When the sig-
Figure 5 shows the NE565 nal appears at the input, the
(ICl) organized as an FSK de- loop locks to it and tracks it be- 65
 100
TABLE 2-ELECTRICAL CHARACTERISTICS OF THE NE566 +V = 12 VOLTS
~
Ve '7 10 VOLlS
50
Parameter Min Typ Max Unit ::c
r.

Supply voltage ±6 ±24 v g

g_ 20
"
VCO Characteristics M'
Maximum operating frequency 1 MHz e:. 10

""" ~ '
UJ
(.)
Drift with temperature 300 ppm/°C
~ 5
Drift with supply voltage 0.2 2.0 %/V ~
Control terminal input Cii
impedance 1 MQ ~ 2 '" ' '
FM distortion(±% deviation) 0.4 1.5 % 1 ''
0.1 0.2 0.5 1 2 5 10
Maximum sweep rate 1.0 mHz
NORMALIZED FREQUENCY
Sweep range 10:1
FIG. 12-GRAPH OF NORMALIZED fre-
Triangle wave output quency of the Fig. 9 circuit as a function
Impedance 50 Q of resistance R3.
Output voltage level 1.9 2.4 Vp-p ... +V = 12 V.OLTS
Linearity 0.5 % £;: ~
c.. en +6
Square wave input f- f-
::::> _J +5
/ \. / \. /
c..O
Impedance
Voltage 5.0
50
5.4
Q
Vp-p
f- :::.
::::>
0
+4
/
" /
" /

Duty cycle
Rise time
40 50
20
60 %
ns
"'
~ fil +10
+12 - ...__
--
f- ~ +B
Fall time 50 ns =>o

10 I I
~ 2:.
::::>
0
+6
+4
-- I -- - -
tween the two frequencies, with
a corresponding DC shift at the ~
M' 1.0
"'\. +V = 12 VOLTS
Ve= 10.5 VOLTS
R3=4K -
FIG. 13-GRAPH OF VCO OUTPUT
output. s \ waveforms for the generator circuit of

'
Loop filter C2 has a small val- UJ
u Fig. 9.
z 0.1
ue to eliminate overshoot on the ~
"\
output pulse, and a three-stage Li \. circuitry.
< 0.01 An NE529 between pin 6 of
RC ladder filter removes carrier c..
< \.
components from the output. u ICl , the NE565, and the output
This filter has a band edge that 0.001
\. of the circuit makes the output
\.
is approximately half way be- of the filter CMOS logic compati-
tween the maximum FSK key-
ing rate (300 baud or 150 Hz)
and twice the input frequency
(about 2200 Hz).
0.0001
1 10

FIG. 10-GRAPH OF FREQUENCY as a

1o2
FREQUENCY - Hz
~'>
1U"" 1o4 105
' 10
6 ble. Adjusting trimmer potenti-
ometer R3 sets the free-running
frequency of the VCO to give a
slightly positive output voltage
function of capacitance for an NE566
The NE529 (IC2) ·is a high- when R3 = 4 kilohms. when a 1070-Hz input signal is
speed analog voltage com- appiied.
parator that combines a Schot- 2.5 The input connection of the
+V= 12VOLTS
tky diode with two high-speed circuit shown in Fig. 5 is typical
>- for applications where a DC
TTL gates and a precision am- ~ 2.0

+10V TO 4'V
UJ
::::>
a /
./ voltage is present at the source,
preventing a direct connection.
~ 1.5
u.. v Both input terminals are re-
R3 fil / turned to ground with identical
R1
1·5K
C2
.001
2KTO
2QI(
N
:J
<
::!:
~ 0.5
1.0

/
v resistors. In this circuit, the val-
ues of resistors Rl and R2 were
selected to give a 600-ohm input
z v
1/
/ impedance.
C1
0 0.5
1.0 1.5 2.0 2.5 3.0
Single-ended power
CONTROL VOLTAGE
(BETWEEN PIN B AND PIN 5) - VOLTS Figure 6 shows the NE565
FIG. 11-GRAPH OF NORMALIZED fre-
configured as a 60-kHz FM de-
quency of the Fig. 9 circuit as a function modulator that is powered from
of control voltage. a single-ended 12- to 24-volt
supply.
MOOUl..ATION
IFUT plifier on a monolithic chip. It is A resistive voltage divider (Rl
FIG. 9-FIXED FREQUENCY GENER- useful in analog to digital con- and R2) and R3 and R4 apply a
ATOR circuit based on the NE566 func- version and can act as an inter- balanced bias voltage to input
66 tion generator. face between TTL and ECL pins 2 and 3 of the NE565. The

FIG. 14-THREE-BAND FM GENERATOR based on the NE566 general-purpose func-
tion generator.
60-kHz FM input signal is AC-
coupled to pin 2. The VCO's free-
running frequency is set to 60
kHz with R6, C2 and trimmer
potentiometer R5. The decoded
output signals are fed through a
three-stage, low-pass filter to
minimize the effects of un -
wanted noise on the signals.
NE566 fundamentals
The NE566, a general-pur-
pose function generator, is a lin-
ear voltage-controlled oscillator
capable of producing buffered
squarewave and triangle-wave
outputs, at fixed and variable
frequwncies, up to a maximum
of about 1 MHz. Its frequency of
oscillation is determined by an
external resistor and capacitor
and the voltage applied to the
control pin.
The oscillator can be pro-
grammed over a ten to one fre-
quency range by the appropri-
ate selection of an external
resistance. It can also be modu-
lated over a ten to one range by a
control voltage. The NE566
finds applications in tone, sig-
nal, and clock generators, as
well as FM modulators.
Figure 7 is a block diagram of
the NE566. The principal
blocks are current sources, a
Schmitt trigger, and two buffer
amplifiers. 1\vo essential exter-
nal components, Rl and Cl. are
shown. The VCO section con-
sists of the pair of voltage-con-
trolled current sources that
linearly charge or discharge an
external timing capacitor..
A linear triangle wave is gen-
erated across the capacitor and
appears at pin 3, and a square
wave generated at the Schmitt
trigger switches the current
sources when the capacitor
voltage reaches preset levels.
These waveforms are available
at the output pins of the buffer
amplifiers.
Figure 8 is the pinout di-
agram for the popular 8 -pin
plastic DIP package. The NE566
is, however, also packaged in a
14-pin DIP package. Tuble 2 lists
selected electrical charac-
teristics of the NE566. It can be
seen that the impedance values
for both the triangle-wave and
squarewave outputs are a low
50 ohms.
Figure 9, a schematic show-
ing the NE566 configured as a
fixed-frequency FM waveform
generator, shows the locations
of the external components re-
quired for its functioning. Fre-
quency is determined by re-
sistor R3 with capacitor C3 and
by µie voltage applied to its con-
trol terminal.
Resistor R3 must have a value
between 2 and 20 kilohms but
capacitor C3 can have any val-
ue. The control voltage must be
between % ,and the full supply
voltage.
The output frequency can var-
ied or modulated over a ten to
one range by variation of the
control voltage. Capacitor C2,
connected between pins 5 and
6, has a value of O.OOlµF to sta-
bilize the circuit.
The operating frequency of
the NE566 is:
f = "" ( + V - VcJIR3 x C3 x + V
0
Resistor R3 should be in the
range of 2 to 20 kilohms.
Figure 10 is a graph of output
frequency as a function o( the
values of capacitor C3 when R3
has a value of 4 kilohms. The
frequency can be varied from 5
Hz with a C3 of lOµF to about
200 kHz with a C3 of O.OOOlµF.
Figure 11 is a graph of nor-
malized frequency as a function
of control voltage, and Fig. 12 is
a graph of normalized frequen-
cy as a function of resistance
R3. Figure 13 is a graph of VCO
outputs of the circuit in Fig. 9
when the power supply is 12
volts.
Figure 14 shows a modifica-
tion that can be made to the Fig.
9 schematic to convert it into a
wide-range, three-band FM gen-
erator. The frequency can be al-
tered by trimmer potentiometer
R4, and three different frequen-
cies can be obtained with selec-
tor switch Sl in series with C3,
C4, and C5 in parallel and con-
. nected to pin 7 of the NE566. As
stated earlier about Fig. 9, ca-
pacitor C3 can have any value,
so C3, C4, and C5 can have val-
ues to give three different fre-
quencies.
The voltage levels of the tri-
angle-wave and squarewave
outputs can be varied by trim-
mer potentiometers R6 and R7.
Those waveforms can be fre-
quency modulated by applying
the modulation waveform to pin
5 through input capacitor Cl.
Resistor R3 raises the circuit's
input impedance to its value of
22 kilohms.
The NE565 PLL and associ-
ated NE566 function generator
are useful intergrated circuits
to be familiar with. The circuits
presented here should give you
a working knowledge of the ICs'
applications.
The final article in this series
about PLL devices w111 describe
the NE567, a highly stable
phase-locked loop device. Al-
though it is primarily used as a
tone decoder, the IC has addi-
tional applications as well. n 67