----------------------------------------------------------------------------------

-- Company:
-- Engineer:
--
-- Create Date: 03/06/2018 13:15:00
-- Design Name:

-- Module Name: Numarator - Behavioral

-- Project Name:

-- Target Devices:

-- Tool Versions:

-- Description:
--

-- Dependencies:
--

-- Revision:
-- Revision 0.01 - File Created

-- Additional Comments:
--

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity ALU is
Port ( clk : in STD_LOGIC;

btn : in STD_LOGIC_VECTOR (4 downto 0);

sw : in STD_LOGIC_VECTOR (15 downto 0);

led : out STD_LOGIC_VECTOR (15 downto 0);

an : out STD_LOGIC_VECTOR (3 downto 0);

cat : out STD_LOGIC_VECTOR (6 downto 0));

end ALU;

architecture Behavioral of ALU is

signal tmp:STD_LOGIC_VECTOR(1 downto 0):="00";

signal en:STD_LOGIC;

signal x: STD_LOGIC_VECTOR(15 downto 0):=x"0000";

signal y: STD_LOGIC_VECTOR(15 downto 0):=x"0000";

signal z: STD_LOGIC_VECTOR(15 downto 0):=x"0000";

signal rez:STD_LOGIC_VECTOR(15 downto 0):=x"0000";

component Monoimpuls is

Port ( btn : in STD_LOGIC;

clk : in STD_LOGIC;

en : out STD_LOGIC);

end component;

component SSD is

Port ( digit : in STD_LOGIC_VECTOR (15 downto 0);

clk : in STD_LOGIC;

cat : out STD_LOGIC_VECTOR (6 downto 0);

an : out STD_LOGIC_VECTOR (3 downto 0));

end component;
begin

x(3 downto 0)<=sw(3 downto 0);

y(3 downto 0)<=sw(7 downto 4);

z(7 downto 0)<=sw(7 downto 0);

M: Monoimpuls port map(btn=>btn(0),clk=>clk,en=>en);

process(clk)

begin

if rising_edge(clk) then

if en='1' then

if sw(0)='1' then

tmp<=tmp+1;

else

tmp<=tmp-1;

end if;

end if;

end if;

end process;

process(tmp,x,y,z)

begin

case tmp is

when "00" => rez<=x+y;

when "01" => rez<=x-y;

when "10" => rez(15 downto 2)<=z(13 downto 0);

rez(1 downto 0)<="00";

when others => rez(13 downto 0)<=z(15 downto 2);

 rez(15 downto 14)<="00";

end case;

end process;

S: SSD port map(rez,clk,cat,an);

--led(7)<=conv_integer(rez) xor 1;

end Behavioral;