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TRAINING REPORT
ON
VLSI DESIGN
Submitted by–
Submitted to – Bharat Suthar
Branch – ECE
Training Coordinator Batch – C1
Electronics & Communication Roll No. – 14EEBEC016
1
Acknowledgement
I am grateful to Sir H. P. Vyas and Sir Lomesh Acharaya for giving guidelines to
make the training successful and am very thankful to lomesh sir which did hard
work on us. In training i have improved my programming skills and learn
technical things about VSLI.
You’re sincerely
Bharat Suthar
2
List of Abbreviation
List of Table
List of Figure
Contents
Chapter 1:.......................................................................................................9
1.1 What is an FPGA?........................................................................................9
1.2 Why do we need FPGAs? ..........................................................................10
1.3 Steps in VSLI Chip Design ........................................................................11
1.4 Moore’s Law ..............................................................................................14
1.5 Available Implementation Technologies ...................................................15
Chapter 2:.....................................................................................................23
1.1 VHDL :- ....................................................................................................23
2.2 Data Type in VHDL...................................................................................29
2.3 Sequential Processing:- ..............................................................................33
Chapter 3: .....................................................................................................38
3.1 Combinational Circuits ..............................................................................38
3.1.1 Circuit-1:- Desgin a Half-Adder .............................................................38
3.1.2 Circuit-2:-Design a Full-Adder ...............................................................39
3.1.3 Circuit-3:- Design a 1 bit magnitude comparator....................................39
3.1.4 Circuit-4:- Design a BCD code to seven segment ..................................41
3.1.5 Circuit-5:- Design a Binary to grey code conversion and display result on
seven segment. .................................................................................................42
3.1.6 Circuit-6:-Desgin a Ripple Carry adder using structural modelling. ......43
3.1.7 Circuit-7:-Design a 16x1 Mux using 8x1 and 2x1 Mux .........................45
3.1.8 Circuit-8:- Design a 2-bit magnitude comparator ...................................47
3.1.9 Circuit-9:-Design a 8x3 Encoder ............................................................48
Chapter 4:.....................................................................................................51
4.1 Sequential Circuit.......................................................................................51
Flip Flop.............................................................................................................51
8
Chapter 1:
1.1 What is an FPGA?
Field Programmable Gate Arrays are two dimensional array of logic blocks and
flip-flops with an electrically programmable interconnections between logic
blocks.
At the highest level, FPGAs are reprogrammable silicon chips. Using prebuilt
logic blocks and programmable routing resources, you can configure these chips
to implement custom hardware functionality without ever having to pick up a
breadboard or soldering iron.
The interconnections consist of electrically programmable switches which is why
FPGA differs from Custom ICs, as Custom IC is programmed using integrated
circuit fabrication technology to form metal interconnections between logic
blocks.
In an FPGA logic blocks are implemented using multiple level low fan-in gates,
which gives it a more compact design compared to an implementation with two-
level AND-OR logic. FPGA provides its user a way to configure:
1. The intersection between the logic blocks and
2. The function of each logic block.
Logic block of an FPGA can be configured in such a way that it can provide
functionality as simple as that of transistor or as complex as that of a
microprocessor. It can used to implement different combinations of
combinational and sequential logic functions. Logic blocks of an FPGA can be
implemented by any of the following:
1. Transistor pairs
2. combinational gates like basic NAND gates or XOR gates
3. n-input Lookup tables
4. Multiplexer’s
5. Wide fan-in And-OR structure
FPGA
Architecture
Systems typically consisted of few large scale integrated components and large
number of SSI (small scale integrated circuit) and MSI (medium scale integrated
circuit) components.
Initial attempt to solve this problem led to development of Custom ICs which
were to replace the large amount of interconnect. This reduced system complexity
and manufacturing cost, and improved performance. However, custom ICs have
their own disadvantages. They are relatively very expensive to develop, and delay
11
Custom ICs:
2. Cost of manufacture
Therefore the custom IC approach was only viable for products with very high
volume, and which not time to market sensitive were.
Synthesis
Implement Design
Test Vector
Design specification
VHDL/Verilog
Behavioral
Codes Design Entry
Simulation
Codes
Device Selection
Netlist
Translate
Mapping
Programming Unit
2. RTL Description: - In this step the designer describe the design in form of
coding. For VLSI many hardware description languages are used. Verilog,
VHDL etc. are example of hardware description language. The coded form
of design is known as RTL description.
3. Functional Verification and Testing: - After writing the HDL code for
design, test vectors are applied to design and simulated. In simulation
process the functionality of design is tested and output is compared with
requirements.
circuits. The faster microchips process electrical signals, the more efficient a
computer becomes.
Costs of these higher-powered computers eventually came down as well,
usually about 30 percent per year. When designers increased the performance of
computers with better integrated circuits, manufacturers were able to create better
machines that could automate certain processes. This automation created lower-
priced products for consumers, as the hardware created lower labor costs
Societal Impact
Fifty years after Moore's law, contemporary society sees dozens of benefits from
his vision. Mobile devices, such as smartphones and tablet computers, would not
work without very small processors. Smaller and faster computers improve
transportation, health care, education and energy production. Just about every
facet of a high-tech society benefits from the concept of Moore's law put into
practice
The Future
Thanks to nanotechnology, some transistors are smaller than a virus. These
microscopic structures contain carbon and silicon molecules aligned in perfect
fashion that help move electricity along the circuit faster. Eventually, the
temperature of the transistors make it impossible to create smaller circuits,
because cooling the transistors takes more energy than what passes through the
transistors. Experts show that computers should reach physical limits of Moore's
law sometime in the 2020s. When that happens, computer scientists can examine
entirely new ways of creating computers.
2. Standard Cell
16
2. Gate Array
Implementation Choices-
Integrated Circuits could be:-
-PLD 100’s
With increasing numbers of logic gates going from 100 gates to 10 M gates.
Implementation Technologies
We can implement a design with many different implementation technologies-
-There are also retargeting tools which will convert a net list from one
technologies to another.
1. Full Custom
Designer hand draws geometries which specify transistors and other devices for
and integrated circuits.
Can achieve very high transistor density (transistor per square micron);
unfortunately, design time can be very long (multiple months).
Involves the creation of a completely new chip, which consists of about a dozen
masks (for the photolithographic manufacturing process).
Fabrication costs are high- all custom marks must be made so non-recurring
engineering costs (NRE) is high (in the thousands of dollars).
-if required number of chip is high then can spread these NRE costs across the
chips.
The first custom chip costs you about $200,000, but each additional one is much
cheaper.
Full custom is currently the only option for mixes Analog/Digital chips.An
example VLSI layout is shown below in figure 1.3
2.Standard Cell
Desginer uses a library of standard cells; an automatic place and route tool does
the layout.
-Not bad for random logic, can be significant for data path type designs.
Design time can be musch faster than full custom because layout is automatically
generated.
Still inviles creatio of cistom chip so all masdks must stillbe made; manufacturing
costs same custom. as full
3.Gate Array
Desginer uses a library of a standard cells.
The designer is mapped onto and arrat of transistor which os already created on a
wafer; wafers with trasnistor arrays can be created ahead of time.
A routing tool creates the masks for the routing layers and customize the pre-
created gate array for the user’s design.
Fabrication costs are cheaper than standard cell or full custom because the gate
array wafers are ,ass produced;
-because only a few (1-3) unique masks have to be created for each design.
-because the wafers are already created and are only missing the routing
layers.
-The more routing layers, the higher the cost,the longer the fabrication
time,but the better usage of the available transistor on the array.
Almost all high volume produstion of complex digital designs are done in either
Standard Cell or Gate Array.
-Gate Arrays used to be more popular, but recently Standard Cells has shown
aresurgence in use.
20
1.7 Advantages
Full custom can give best density and performance.Faster design time and ease of
design are principle advantages of gate array and standard cell over full custom.
Fast fabrication time and lower cost are principle advantages of gate arrays over
standard cell.
Gate arrays offer much higher density over FPGAs and are cheaper than FPGAs
in volume production.
PLD’s still hold a speed advantage over most FPGAs are usefull primarily for
high speed decoding and speed critical glue logic.
Chapter 2:
1.1 VHDL :-
- VHDL stands for VHSIC Hardware Description Language and VHSIC stands
for Very High Scale Integrated Circuit. VHDL is a programming language which
is used to describe the behavior of a digital circuit. VHDL is commonly used to
write text models that describe a logic circuit. This text model of a circuit is
simulated by various tools.
Terminology in VHDL
1. Entity:- All designs are expressed in terms of entities. An entity is the most
basic building block in a design. The uppermost level of the design is the
top-level entity. If the design is hierarchical, then the top-level description
will have lower-level descriptions contained in it. These lower-level
descriptions will be lower-level entities contained in the top-level entity
description.
24
Ex.1
Entity xor_g is
port (a,b:in std_logic ; c:out std_logic);
end xor_g;
1. Data Flow:-
In this modeling style, the flow of data through the entity is expressed primarily
using concurrent signal assignment statements. The structure of the entity is not
explicitly specified in this modeling style, but it can be implicitly deduced.
For example half adder implement using dataflow-
Ex.2
entity hf_adder is
port(a,b:in std_logic ; s,c:out std_logic);
end hf_adder;
architecture dataflow of hf_adder is
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begin
s<=a xor b;
c<=a and b;
end dataflow;
2. Behavioural:-
The behavioral style of modeling specifies the behavior of an entity as a set of
statements that are executed sequentially in the specified order. This set of
sequential statements, that are specified inside a process statement, do not
explicitly specify the structure of the entity but merely specifies its
functionality. A process statement is a concurrent statement that can appear
within an architecture body.
For example Mux is implement using behavioral-
Ex.3
entity mux2x1 is
port(sum,minus: in std_logic_vector(1 downto 0);
sel:in std_logic;
output: out std_logic_vector(1 downto 0));
end entity;
architecture behav of mux2x1 is
begin
process(sum,minus,sel)
begin
case sel is
when '0' => output<=minus;
26
Ex.4
entity full_adder is
port(a,b,cin:in std_logic ;
sum,cout:out std_logic);
end entity;
architecture struct of full_adder is
component and_g is
port(a,b:in std_logic ; c:out std_logic);
end component;
component or_g is
port(a,b:in std_logic ; c:out std_logic);
end component;
component xor_g is
port(a,b:in std_logic ; c:out std_logic);
end component;
2. TestBench: - Test Bench is also a HDL code. This is not used to describe a
hardware, but to simulate a design. In test bench we call the component
or entity to be tested. Test vectors are applied to design and result is
verified in simulation process.
Now how to write testbench first let’s see the testbench of XOR gate
Ex.5
entity xor_tb is
end xor_tb;
architecture TestBench of xor_tb is
component xor_g is
port(a,b:in std_logic ; c:out std_logic);
end component;
signal a,b,c:std_logic;
begin
A1:xor_g port map(a,b,c);
process
begin
--case 1;
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a<='0'; b<='0';
wait for 10 ns;
--case 2;
a<='0'; b<='1';
wait for 10 ns;
--case 3
a<='1'; b<='0';
wait for 10 ns;
--case 4;
a<='1'; b<='1';
wait for 10 ns;
end process;
end architecture;
After simulation in ModelSim altera waveform as shown in figure 2.1
1. Scalar:- Scalar types describe objects that can hold, at most, one value at
a time.
The type itself can contain multiple values, but an object that is declared scalar
type can hold, at most, one of the scalar values at any point in time. Referencing
the name of the object references the entire object.
Scalar types encompass these four classes of types:
-Integer types
-Real types
-Enumerated types
-Physical types
b. Real type: - Real type is used to declare object the contain fractional
values/real numbers. The minimum range of real numbers is also specified by
31
the Standard package in the Standard Library, and is from -1.0E+38 to +1.0E+38.
Time cannot be assigned to a real value.
example – port(a:in real := 3.132e-2);
ii. Record type:- Record types group objects of many types together
as a single object. Each element of the record can be accessed by its field
name. Record elements can include elements of any type, including arrays
and records. The elements of a record can be of the same type or different
types. Like arrays, records are used to model abstract data elements.
Following is an example of a record type declaration:
convert binary data into integer – In VHDL we use a function to convert binary
data into integer.
y<=conv_integer(x);
where y is an integer object and x is an std_logic type object.
if [boolean-expressionthen
sequential-statements
[ elsif boolean-expression then
sequential-statements
[ else -- else clause.
sequential-statements ]
end if;
Ex.6
end process;
end architecture;
(ii) Case Statement:- The case statement is used whenever a single expression
value can be used to select between numbers of action. Case statement is written
under process. Case statement starts with ‘case’ keyword and ends with ‘end case’
keyword. Keyword ‘when’ is used to define choices.
If the value of instruction is one of the choices listed in the WHEN clauses, then
the statement following the WHEN clause is executed.
case expression is
when choices => sequential-statements -- branch #1
when choices => sequential-statements -- branch #2
-- Can have any number of branches.
[ when others => sequential-statements ] -- last branch
end case;
Fig 2.3-Mux
entity mux is
port(s:in std_logic_vector(1 downto 0);
i:in std_logic_vector(3 downto 0);
y:out std_logic);
end mux;
architecture behave of mux is
36
begin
process(s,d)begin
case s is
when “00” => y<=i(0);
when “01” => y<=i(1);
when “10” => y<=i(2);
when “11” => y<=i(3);
when others => y<=’0’;
end case;
end process;
Ex.8:-
Ripple carry adder using loop
entity rca is
port(a:in std_logic_vector (3 downto 0);
b:in std_logic_vector (3 downto 0);
cin:in std_logic;
sum:out std_logic_vector (3 downto 0);
cout:out std_logic);
end entity;
architecture lv of rca is
begin
process (a,b,cin)
variable c: std_logic_vector(4 downto 0);
begin
c(0):= cin;
for i in 0 to 3 loop
sum(i)<=(a(i) xor b(i) xor c(i));
c(i+1):= ((a(i) and b(i)) or (b(i) and c(i)) or (a(i) and
c(i)));
end loop;
cout<= c(4);
end process;
end architecture;
38
Chapter 3:
3.1 Combinational Circuits
Combinational logic circuits are circuits in which the output at any time depends
upon the combination of the input signals at that instant only and does not depends
upon past value.
The half adder is an example of a simple, functional digital circuit built from two
logic gates. The half adder adds two one-bit binary numbers (AB). The output is
the sum of the two bits (S) and the carry (C).figure shown below.
library ieee;
use ieee.std_logic_1164.all;
entity hf_adder is
port(a,b:in std_logic ; s,c:out std_logic);
end hf_adder;
architecture dataflow of hf_adder is
begin
s<=a xor b;
39
c<=a and b;
end dataflow;
The full adder is an example of a simple, functional digital circuit built from five
logic gates. The full adder adds two three-bit binary numbers (ABC). The output
is the sum of the three bits (S) and the carry (C) figure shown below.
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(a,b,cin:in std_logic ; s,cout:out std_logic);
end full_adder;
architecture dataflow of full_adder is
begin
s<=a xor b xor cin;
cout<=(a and b) or (b and cin) or ( a and cin);
end dataflow;
Magnitude comparator is used to compare two binary number and make decision
that whether the numbers are equal or which number is larger and which is
smaller.
Truth table as shown in figure below.
library ieee;
use ieee.std_logic_1164.all;
entity mag_comparator is
port(a,b:in std_logic ; x,y,z:out std_logic);
end entity;
architecture dataflow of mag_comparator is
begin
x<=a and (not b);
y<= a xnor b;
z<= (not a)and b;
end architecture;
41
Common Anode: All the Negative terminals (cathode) of all the 8 LEDs are
connected together. All the positive terminals are left alone.
Common Cathode: All the positive terminals (anode) of all the 8 LEDs are
connected together. All the negative thermals are left alone.
library ieee;
use ieee.std_logic_1164.all;
entity bcd_7_segment is
port (w,x,y,z:in std_logic; a,b,c,d,e,f,g:out std_logic);
42
end bcd_7_segment;
architecture datalflow of bcd_7_segment is
begin
a<= w or y or (x xnor z);
b<= (not x) or (y xnor z);
c<= x or (not y) or z;
d<= w or (y and (not z)) or (x xor (y or (not x)));
e<= (not z) and ((not x) or y);
f<= w or ((not y) and (not z))or(xand((not y)or (not z)));
g<= (w or (y and (not z)) or (x xor y));
end architecture;
3.1.5 Circuit-5:- Design a Binary to grey code conversion and display result
on seven segment.
library ieee;
use ieee.std_logic_1164.all;
entity binary_grey_7 is
port(w,x,y,z:in std_logic; a:out std_logic_vector(6
downto 0); b:out std_logic_vector(6 downto 0) );
43
end binary_grey_7;
architecture mix of binary_grey_7 is
signal s:std_logic_vector (3 downto 0);
begin
s(3)<= w;
s(2)<= w xor x;
s(1)<= x xor y;
s(0)<= y xor z;
process(s)
begin
case s is
when "0000"=> a<="1111110" ;b<="1111110";
when "0001"=> a<="1111110" ;b<="0110000";
when "0011"=> a<="1111110" ;b<="1111001";
when "0010"=> a<="1111110" ;b<="1101101";
when "0110"=> a<="1111110" ;b<="1011110";
when "0111"=> a<="1111110" ;b<="1110000";
when "0101"=> a<="1111110" ;b<="1011011";
when "0100"=> a<="1111110" ;b<="0110011";
when "1100"=> a<="0110000" ;b<="1101101";
when "1101"=> a<="0110000" ;b<="1111001";
when "1111"=> a<="0110000" ;b<="1011011";
when "1110"=> a<="0110000" ;b<="0110011";
when "1010"=> a<="0110000" ;b<="1111110";
when "1011"=> a<="0110000" ;b<="0110000";
when "1001"=> a<="1111110" ;b<="1111011";
when "1000"=> a<="1111110" ;b<="1111111";
when others => a<="1111110" ;b<="1111110";
end case;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity ripple_adder is
port(a:in std_logic_vector (3 downto 0);
b:in std_logic_vector (3 downto 0);
cin:in std_logic;
sum:out std_logic_vector (3 downto 0);
cout:out std_logic);
end ripple_adder;
architecture struct of ripple_adder is
component full_adder is
port(a,b,cin:in std_logic ;
sum,cout:out std_logic);
end component;
signal c: std_logic_vector (2 downto 0);
begin
45
fulladder1:full_adder portmap(a(0),b(0),cin,sum(0),c(0));
fulladder2:full_adder portmap(a(1),b(1),c(0),sum(1),c(1));
fulladder3:full_adder portmap(a(2),b(2),c(1),sum(2),c(2));
fulladder4:full_adder portmap(a(3),b(3),c(2),sum(3),cout);
end architecture;
In electronics, a multiplexer (or mux) is a device that selects one of several analog
or digital input signals and forwards the selected input into a single line. A
multiplexer of 2n inputs has ⌈n⌉ select lines, which are used to select which input
line to send to the output.
Figure a shown below:
library ieee;
use ieee.std_logic_1164.all;
entity mux_16x1 is
port (i:in std_logic_vector (15 downto 0);
lines: in std_logic_vector (3 downto 0);
z:out std_logic);
end entity;
architecture struct of mux_16x1 is
component mux_8x1 is
port(d:in std_logic_vector (7 downto 0);
sel:in std_logic_vector (2 downto 0);
y:out std_logic);
end component;
component mux_2x1 is
port(w:in std_logic_vector(1 downto 0);
sel:in std_logic; y:out std_logic );
end component;
signal d1,d2:std_logic_vector(7 downto 0);
signal d0: std_logic_vector(1 downto 0);
signal x1,x2: std_logic;
signal sel: std_logic_vector(2 downto 0);
signal y: std_logic_vector (7 downto 0);
begin
d1<=(i(15)&i(14)&i(13)&i(12)&i(11)&i(10)&i(9)&i(8));
d2<=(i(7)&i(6)&i(5)&i(4)&i(3)&i(2)&i(1)&i(0));
d0<=(x1&x2);
sel<=(lines(2)&lines(1)&lines(0));
end architecture;
47
Inputs Outputs
A B X(A>B) Y(A=B) Z(A<B)
00 10 0 0 1
10 11 0 0 1
11 01 1 0 0
01 01 0 1 0
11 10 1 0 0
01 00 1 0 0
library ieee;
use ieee.std_logic_1164.all;
entity bit2_mag_comp is
port (a,b:in std_logic_vector (1 downto 0); q,w,e:out
std_logic);
end entity;
architecture struct of bit2_mag_comp is
component mag_comparator is
port(a,b:in std_logic ; x,y,z:out std_logic);
end component;
signal t3,t2,t1,r3,r2,r1: std_logic;
begin
mag1: mag_comparator port map (a(1),b(1),t3,t2,t1);
mag2: mag_comparator port map (a(0),b(0),r3,r2,r1);
process(t,r)
begin
if (t="010") then
if(r="010") then
48
q<='0';w<='1';e<='0';
else
q<='0';w<='0';e<='1';
end if;
elsif (t="100") then
q<='1';w<='0';e<='0';
else
q<='0';w<='0';e<='1';
end if;
end process;
end architecture;
library ieee;
49
use ieee.std_logic_1164.all;
entity encoder is
port(D:in std_logic_vector(7 downto 0); y:out
std_logic_vector(2 downto 0); en:in std_logic);
end encoder;
architecture behav of encoder is
begin
process(en,D)
begin
if (en='1') then
case D is
when "00000001" => y<="000";
when "00000010"=> y<="001";
when "00000100"=> y<="010";
when "00001000"=> y<="011";
when "00010000"=> y<="100";
when "00100000"=> y<="101";
when "01000000"=> y<="110";
when "10000000"=> y<="111";
when others => y<="000";
end case;
else
y<="000";
end if;
end process;
end architecture;
After simulation in Modal Sim Altera we got this Waveform as shown below in
fig 3.8.
the basic problem is that we have 8 input data lines but on board we have only 4
dip switch keep in mind that we can also use external switch but how to do with
4 switches.
Basic idea is you can store 8 bits data in a signal or u can define inout mode in
entity.
50
Chapter 4:
4.1 Sequential Circuit
The combinational circuit does not use any memory. Hence the previous state of
input does not have any effect on the present state of the circuit. But sequential
circuit has memory so output can vary based on input. This type of circuits uses
previous input, output, clock and a memory element.
Flip Flop
Flip flop is a sequential circuit which generally samples its inputs and changes
its outputs only at particular instants of time and not continuously. Flip flop is
said to be edge sensitive or edge triggered rather than being level triggered like
latches.
VHDL code is
library ieee;
use ieee.std_logic_1164.all;
entity jk_ff is
port(j,k,clk,rst: in std_logic;
q,qbar:out std_logic);
end entity;
architecture behav of jk_ff is
signal w: std_logic;
begin
process(j,k,clk,rst)
begin
if(clk'event and clk='1') then
if (rst='1') then
53
w<='0';
library ieee;
use ieee.std_logic_1164.all;
entity d_ff is
port ( d,rst,clk:in std_logic ;
q ,qbar:out std_logic);
end entity;
architecture behav of d_ff is
signal w: std_logic;
begin
process (d,rst,clk)
begin
if(clk'event and clk='1') then
if (rst='1') then
w<='0';
else
w<=d;
end if;
end if;
end process;
q<=w;
qbar<= not w;
end architecture;
Serial In Serial Out (SISO) shift registers are a kind of shift registers where
both data loading as well as data retrieval to/from the shift register occurs in
serial-mode. Figure 1 shows a n-bit synchronous SISO shift register sensitive to
positive edge of the clock pulse. Here the data word which is to be stored is fed
bit-by-bit at the input of the first flip-flop. Further it is seen that the inputs of all
other flip-flops (except the first flip-flop FF1) are driven by the outputs of the
preceding ones say for example, the input of FF2 is driven by the output of FF1.
At last the data stored within the register is obtained at the output pin of the
nth flip-flop in serial-fashion.
Figure show below in fig1.7
Fig 4.4-SISO
library ieee;
use ieee.std_logic_1164.all;
entity serial_iso is
port(d,clk,rst:in std_logic;
x:out std_logic);
end entity;
architecture behav of serial_iso is
signal w: std_logic_vector (3 downto 0);
begin
process(d,clk,rst)
begin
if(clk'event and clk='1') then
if (rst='1') then
w<="0000";
else
w(0)<=d;
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w(1)<=w(0);
w(2)<=w(1);
w(3)<=w(2);
end if;
end if;
end process;
x<=w(3);
end architecture;
4.1.4 Circuit 4:- Design Parallel in Parallel Out Shift Register (PIPO).
Fig 4.6-PIPO
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VHDL code:
library ieee;
use ieee.std_logic_1164.all;
entity pipo is
port(d:in std_logic_vector (3 downto 0);
clk,rst:in std_logic;
x:out std_logic_vector (3 downto 0));
end entity;
architecture behav of pipo is
begin
process(d,clk,rst)
begin
if(clk'event and clk='1') then
if (rst='1') then
x<="0000";
else
x<=d;
end if;
end if;
end process;
end architecture;
A digital circuit which is used for a counting pulses is known counter. Counter is
the widest application of flip-flops. It is a group of flip-flops with a clock signal
applied.
VDHL CODES:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
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entity up_counter is
port(clk,rst:in std_logic;
y:out std_logic_vector(3 downto 0));
end entity;
architecture behav of up_counter is
signal temp : std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if (rst='1') then
temp<="0000";
elsif (clk'event and clk='1') then
temp<=temp + '1';
end if;
end process;
y<=temp;
end architecture;
4.1.6 Circuit 6:-Design 4-bit UP/down Counter with halt input and display
the result on seven segment.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity downcount is
port(clk,rst,hlt,ud:in std_logic;
a,b:out std_logic_vector(6 downto 0));
end entity;
architecture behav of counter_7segment is
signal pulse_counter: std_logic_vector (3 downto 0);
signal pulse :std_logic;
signal temp : std_logic_vector(3 downto 0);
begin
process(clk)
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begin
if (clk'event and clk='1') then
if ( pulse_counter < X"2FAF080") then
pulse_counter <= pulse_counter+X"1";
pulse<='1';
else
pulse_counter<=(others=>'0');
pulse<='0';
end if;
end if;
end process;
process(pulse,rst)
begin
if (rst='1') then
temp<="0000";
elsif (pulse'event and pulse='1') then
if (ud='1') then
if (hlt='1') then
temp<=temp + '1';
else
temp<=temp;
end if;
else
if (hlt='1') then
temp<=temp-'1';
else
temp<=temp;
end if;
end if;
end if;
end process;
process(temp)
begin
case temp is
when "0000"=> a<="1111110" ;b<="1111110";
when "0001"=> a<="1111110" ;b<="0110000";
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begin
process(clk)
begin
if (clk'event and clk='1') then
if ( pulse_counter < X"2FAF080") then
pulse_counter <= pulse_counter+X"1";
pulse<='1';
else
pulse_counter<=(others=>'0');
pulse<='0';
end if;
end if;
end process;
process
begin
if (pulse'event and pulse='1') then
if (rst='1' ) then
q<="0001";
else
q(3)<=q(0);
q(2)<=q(3);
q(1)<=q(2);
q(0)<=q(1);
end if;
end if;
end process;
y<=q;
end architecture;
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A Johnson counter is a circular shift register with the complemented output of the
last flip‐flop connected to the input of the first flip‐flop. This counter is similar to
Ring counter except for one thing that in ring counter the input to first flip flop is
the non-complemented output of last flip-flop.
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VHDL CODES:
library ieee;
use ieee.std_logic_1164.all;
entity jcount is
port(clk,rst:in std_logic;
y:out std_logic_vector(3 downto 0));
end jcount;
architecture behav of jcount is
signal w:std_logic_vector(3 downto 0):="0000";
begin
process(clk)
begin
if(rst='0')then
w<="0000";
elsif(clk'event and clk='0')then
w(3)<=(not w(0));
w(2)<=w(3);
w(1)<=w(2);
w(0)<=w(1);
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end if;
end process;
y<=w;
end behav;
There are two types of finite state machines that generate output −
VHDL CODES:
library ieee;
use ieee.std_logic_1164.all;
entity fsm_1001 is
port(x,clk,rst:in std_logic;
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y:out std_logic);
end entity ;
architecture behav of fsm_1001 is
if (rst='1') then
ps<=s0;
elsif (clk'event and clk='1') then
ps<=ns;
end if;
end process;
end if;
when s3=>
if (x='1') then
ns<=s1;
else
ns<=s2;
end if;
end case;
end process;
end architecture;
RTL Level:
Chapter 5:
5.1 Implemented digital circuits
Implemented digital circuits on Altera FPGA board in my summer
training session and digital circuits list as shown below.
i. All basic gate for e.g. AND, OR, NOT, XOR etc.
ii. Half adder
iii. Full adder
iv. Half add/sub
v. Full add/sub
vi. Mux
vii. BCD
viii. Binary to Grey
ix. BCD to 7-segment
x. Ripple carry adder
xi. Magnitude comparator
xii. Design a 16x1 mux using 8x1 and 2x1 mux’s
xiii. Carry look ahead adder
xiv. Ripple carry adder using loop
xv. Encoder
xvi. Decoder
xvii. Flip flop
xviii. Flip flop using other flip flop
xix. Serial in serial out shift register
xx. Parallel in parallel out shift register
xxi. Serial in parallel out shift register
xxii. Parallel in serial out shift register
xxiii. Counter
xxiv. Up/down counter with halt input
xxv. Frequency divider circuit
xxvi. Counter using data flow modelling
xxvii. Ring counter
xxviii. Johnson counter
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Fig 5.1-EVM
When cast_vote is enable counters start working than if voter votes candidate P1
counter 1 counts and vote counts if Vote_done is enable. Like this circuits works
and I have this using behavioural modelling.
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VHDL CODES:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity evm1 is
port(p1,p2,p3,cast_vote,clk,rst:in std_logic;
count1,count2,count3:out std_logic_vector(3 downto
0);
vote_done: out std_logic );
end entity;
architecture behav of evm1 is
signal c1,c2,c3: std_logic_vector(3 downto 0);
begin
process(clk,rst,p1,p2,p3)
begin
if(rst='1') then
c1<="0000";
c2<="0000";
c3<="0000";
vote_done<='0';
elsif(clk'event and clk='1') then
if(p1='1' and p2='0' and p3='0' and cast_vote='1')
then
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c1<=c1 + '1';
vote_done<='1';
elsif(p1='0' and p2='1' and p3='0' and cast_vote='1')
then
c2<=c2 + '1';
vote_done<='1';
elsif(p1='0' and p2='0' and p3='1' and cast_vote='1')
then
c3<=c3 + '1';
vote_done<='1';
else
c1<=c1;
c2<=c2;
c3<=c3;
vote_done<='0';
end if;
end if;
end process;
count1<=c1;
count2<=c2;
count3<=c3;
end architecture;
i. Binary Multiplier.
ii. Wallace Multiplier.
iii. Booth Multiplier.
iv. Modified Booth Multiplier.
v. EVM using Structural Modelling.
vi. Universal shift register.
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References
1. Wikipedia www.wikipedia.com
2. VHDL Programming By Example Douglas Perry.
3. VHDL primer by J bhasker.
4. Altera https://www.altera.com/
5. Xilinx - All Programmable https://www.xilinx.com/