Physica E 69 (2015) 27–33

Contents lists available at ScienceDirect

Physica E
journal homepage: www.elsevier.com/locate/physe

Simulation analysis of a novel fully depleted SOI MOSFET: Electrical

and thermal performance improvement through trapezoidally doped
channel and silicon–nitride buried insulator
Hadi Shahnazarisani, Saeed Mohammadi n
Electrical and Computer Engineering Department, Semnan University, Semnan, Iran

H I G H L I G H T S G R A P H I C A L A B S T R A C T

We have introduced a novel nano- We introduce a novel nano-scale SOI MOSFET structure with vertical trapezoidal doping distribution,
scale SOI MOSFET structure. additional side gate, and dual material buried insulator, and show that the on–off current ratio and the

It is based on vertical trapezoidal self-heating effect of the proposed device improve considerably rather than those of the conventional
doping distribution and additional structure.
side gate.

We have also used dual material
buried insulator to improve self-
heating.

We have shown the improvement of
Ion/Ioff and self-heating effect.

art ic l e i nf o a b s t r a c t

Article history: In this paper, we present a novel nano-scale fully depleted silicon-on-insulator metal-oxide semi-
Received 8 August 2014 conductor field-effect transistor (SOI MOSFET). On-state current increment, leakage current decrement,
Received in revised form and self-heating effect improvement are pursued in our proposed structure. The structure makes use of a
16 December 2014
buried insulator layer which consists of two materials to reduce the self-heating effect. On the other
Accepted 6 January 2015
Available online 7 January 2015
hand, to modify the sub- and super-threshold drain current, vertical trapezoidal doping distribution and
additional side gate technique are employed. Our novel transistor is named dual material buried in-
Keywords: sulator vertical trapezoidal doping SOI MOSFET (DV-SOI MOSFET). We investigate the electrical perfor-
Silicon on insulator mance and thermal behavior of the DV-SOI MOSFET using a commercial device simulator. We demon-
Self-heating
strate that the proposed structure increases on–off current ratio by orders of magnitude and considerably
Leakage current
improves self-heating effect in comparison with the conventional uniform doping fully depleted silicon-
Dual material buried insulator
Vertical trapezoidal doping on-insulator MOSFET (C-SOI) which uses side gate for better electrical performance.
Side gate & 2015 Elsevier B.V. All rights reserved.

1. Introduction
To achieve higher performance and lower power consumption,
transistors have been scaled in the past decades. Scaling of
n
Corresponding author. Fax: þ 98 2333654123.
E-mail address: sd.mohammadi@semnan.ac.ir (S. Mohammadi).
MOSFETs has raised adverse short channel effects (SCEs) [1–3]. The
main short channel effects are the threshold voltage roll-off, the
degradation of the subthreshold swing, and the drain induced
barrier lowering effect [2–4]. SCEs lead to the increment of the Off-
state current, and degradation of the on–off current ratio. Two
common approaches to minimize these effects are using thinner
gate oxide and doping the channel with a higher dose of impurity

http://dx.doi.org/10.1016/j.physe.2015.01.012
1386-9477/& 2015 Elsevier B.V. All rights reserved.
28 H. Shahnazarisani, S. Mohammadi / Physica E 69 (2015) 27–33
[5,6]. Gate leakage current increment, carrier mobility degrada-
tion, and random dopant fluctuation are some of the negative
consequences of using these techniques in the nano-scale regime
[7]. Hence alternative MOSFET structures have been proposed. SOI-
MOSFET is one of the most promising structures for further
downscaling of the conventional bulk technology [8,9]. Thin body
nature of this device has the advantage of suppressing SCEs due to
better electrostatics influence of the gate compared to that of bulk
structures [10,11]. This enables us to reduce the doping level of the
channel. However, short channel effects still occur in SOI-MOSFETs
but to a lesser extent than in bulk MOSFETs.
One of the main difficulties in SOI-MOSFETs is dissipating the
heat generated in the active region of the device, since the buried
insulator layer blocks the heat flow toward out of the body of the
device [10]. Compensation of the self-heating effect is an im-
portant issue for improving the device performance. Although, the
straightforward approach for the heat dissipation seems to be the
reduction of the buried oxide thickness, but it degrades the
blocking voltage and the conduction capability [11,12].
The advantages of the SOI-MOSFET structures compared to the
conventional MOSFET structure have been widely investigated
[13,14], and the use of SOI technology in the integrated circuits
seems indispensable in the future. However, ongoing researches to
optimize electrical performance and thermal behavior of SOI-
MOSFETs continue. Recently, several SOI-MOSFET structures have
been reported in the literature to improve AC performance and
self-heating effect [15–17].
In this paper, we employ the idea of using a higher thermal
conductivity dielectric as buried insulator instead of using silicon
dioxide. Recently utilization of silicon nitride layer as dielectric in
different MOSFET structures has been taken into consideration
[18,19]. The thermal conductivity of Si3N4 is 0.185 W K  1 cm  1
that is dramatically higher than that of SiO2, which is
0.014 W K  1 cm  1. However, to have a better interface between
the buried insulator and the Si body of the SOI device, Si3N4 layer
is used with a thin SiO2 layer in stacked configuration. On the
other hand, to improve the on–off current ratio, we employ a
channel doping engineering technique in our proposed structure.
Here, the doping density of the channel is distributed in a trape-
zoidal form in the vertical direction. This doping distribution
profile results in a higher potential barrier against the injected
carriers from the source, as they are further from the gate.
To simulate and examine the different characteristics of the
proposed SOI device, the ATLAS device simulator is used. In the
simulator environment the basic Poisson and drift–diffusion
equations and some other impressive physical models such as
Shockley–Read–Hall (SRH), and Auger recombination models are
utilized simultaneously. Furthermore, carrier velocity saturation,
carrier–carrier scattering at high doping concentrations, the de-
pendence of mobility on temperature, and the influence of vertical
electric fields are taken into account, too. Quantum models are
also activated for accurate simulation of devices. Comparing the
experimental data [20,21] and the simulation results of the drain
current of a similar structure (Fig. 1), it is shown that ATLAS is a
suitable numerical simulator for accurate examination of our
semiconductor device.
2. DV-SOI structure
Schematic cross-sections of the DV-SOI structure and the C-SOI
structure are shown in Fig. 2(a) and (b), respectively. The DV-SOI
structure consists of dual material buried insulator instead of just
SiO2 beneath active region (channel region). Because of the higher
thermal conductivity of Si3N4 than that of SiO2, the better heat
conduction path from the active region of the device to the
Fig. 1. Good agreement between experimental profile [21] and simulated profile.
Data are reported for VG ¼ 0.3 V, Gate metal work function ¼ 4.5 eV, T ¼ 300 K,
NA ¼ 1  1018 cm  3.
substrate is achieved in the proposed structure in comparison with
the C-SOI structure. It is worth noting that the Si3N4–Si interface
quality is rather poor [22]. Therefore, we have used a thin layer of
SiO2 on top of the Si3N4 layer for having a better interface quality.
The distribution of the dopant atoms in the channel of the
proposed transistor is vertically trapezoidal. Doping density dis-
tributions in the DV-SOI and C-SOI structures are shown in Fig. 3. It
can be seen from the figure that, the channel is doped linearly
from the bottom with higher concentration to the top with lower
concentration in the DV-SOI structure. In order to study the effect
of vertically trapezoidal doping profile on the electric character-
istics of the device, a sample of doping distribution is simulated.
The vertically trapezoidal doping is linearly graded from
1  1015 cm  3 to 1  1019 cm  3.
For making a fair comparison, all the device parameters of the
DV-SOI are chosen equal to those of the C-SOI unless otherwise
stated. In the C-SOI structure, the uniform doping level of
1  1018 cm  3 is utilized for the channel which yields the same
threshold voltage, Vth ¼0.279 V, for the both structures. Para-
meters for the DV-SOI structure are listed in Table 1. A tempera-
ture of 300 K was employed by default in the simulations. Our
simulations results show that the proposed structure has better
sub- and super-threshold performance rather than conventional
structure. This can be observed in Fig. 4, where we have plotted
the drain current versus gate voltage characteristics of both de-
vices in linear and logarithmic scale at VDS ¼0.5 V.
3. Results and discussion
3.1. Self-heating effect improvement
In the SOI transistors, the difference between the channel and
ambient temperature is reported by McDaid [23]:
Pt tb
ΔTC =
Kd A (1)
where tb is the thickness of the buried layer, Kb is the thermal
conductivity of the buried layer, and A is the effective channel
length multiplied by the device width that is the area over which
the power is generated.
Because of the higher thermal conductivity of Si3N4
(0.185 W K  1 cm  1) compared to that of SiO2 (0.014 W K  1 cm  1),
we have replaced the commonly used insulator SiO2 with silicon ni-
tride, in the DV-SOI structure, expecting much smaller values of ΔTc in
 H. Shahnazarisani, S. Mohammadi / Physica E 69 (2015) 27–33 29

Fig. 2. Cross section of the (a) DV-SOI MOSFET and (b) C-SOI MOSFET structures.

Fig. 3. Doping distribution profile in the channel for the DV-SOI and C-SOI
structures.

Table 1
Typical parameters for the DV-SOI MOSFET and
C-SOI MOSFET structures.

Parameter Value

Channel length 30 nm
Main gate length, LM 14 nm
Side gate length, LS 14 nm
Gate oxide thickness, tf 1.2 nm
Buried oxide thickness, tBOX 100 nm
Thin silicon thickness, tSi 15 nm
Thin silicon film doping, NA 1  1018
Gap length, Z 2 nm
Source/drain doping, Nd 1  1020
Gate metal work function 4.5 eV
Voltage difference, VDiff 0.3 V
p-Type substrate doping 1  1013
Si3N4 thickness, tSi3N4 87.5 nm Fig. 4. Drain current versus gate voltage characteristics of the DV-SOI and C-SOI
Buried oxide thickness up of Si3N4 12.5 nm MOSFETs in linear and logarithmic scale at VDS ¼0.5 V. The parameters of these
structures are assumed according to Table 1.
30 H. Shahnazarisani, S. Mohammadi / Physica E 69 (2015) 27–33
Fig. 5. Steady state distribution of the temperature for (a) DV-SOI MOSFET and (b) C-SOI MOSFET structures. The bias conditions for both structures are VGS ¼  2 V and VDS
¼ 1 V. The other simulation parameters are listed in Table 1.
the DV-SOI structure in comparison with the conventional structure.
Fig. 5(a) and (b) shows the steady state heat distribution in the
DV-SOI and C-SOI structures at the same bias conditions (VGS
¼  2 V and VDS ¼1 V), respectively. The other parameters of the
structures are listed in Table 1. It can be seen in the figures that,
the temperature of the DV-SOI structure is considerably lower
than the temperature of the C-SOI structure because of the better
heat flow path in the proposed structure.
The channel temperature versus the drain voltage bias when
the gate voltage is held at  2 V is shown in Fig. 6. Generally, the
higher drain voltage bias leads to the higher lattice temperature,
however, in the DV-SOI structure due to the improved self-heating
effect, the slope of the curve is much smoother rather than the
slope in the curve of the C-SOI structure.
One of the main consequences of the higher temperature lat-
tice is dominant phonon scattering mechanism, which decreases
the carrier mobility considerably. It has been shown that this de-
pendence can be stated as [24]:
⎛ T ⎞−K
μ eff = μ eff,0 ⎜ ⎟
⎝ T0 ⎠
Fig. 6. Channel temperature versus drain bias for C-SOI MOSFET and DV-SOI
MOSFET structures at VGS ¼  2 V. The other simulation parameters are listed in
Table 1.
where μeff,0 is the effective mobility at ambient temperature, T is
the average channel temperature, T0 is the ambient temperature,
and k is the mobility temperature exponent that for NMOS tran-
sistors has a typical value in the range of 1.5–1.7 [25,26]. Therefore,
the proposed structure shows higher mobility in the channel
region due to temperature reduction and we expect that the drain
current increases. Fig. 7(a) and (b) shows the electron concentra-
tion of the C-SOI, and DV-SOI structures along the surface of the
devices. As it can be inferred from these figures, the electron
concentration of the DV-SOI structure increases with respect to the
C-SOI structure. So, we have achieved 15% electron concentration
increment in the maximum values of the proposed structure with
respect to the C-SOI structure.
Dependence of the maximum temperature of the lattice and
the gate-substrate capacitance of the device on the thickness of
the silicon nitride layer is investigated in Fig. 8. Decreasing the
buried layer thickness results in reduction of thermal resistance of
the layer and hence the maximum temperature of the lattice di-
minishes. On the other hand, as it can be observed from the figure,
when the thickness of silicon nitride layer decreases, the gate-
substrate capacitance of the device will increase, since the capa-
(2)
citance of the device depends on the dielectric constant and
thickness of the Si3N4 layer.
3.2. Leakage current reduction
To reduce the leakage current in the proposed DV-SOI transis-
tor, we have focused on the modification of the profile of the
channel potential in a way that the channel conduction can be
controlled better at the subthreshold region of the device opera-
tion. Although doping the channel with the higher dose of im-
purity is a well-known approach for reducing adverse short
channel effects, but, as stated before, it is not recommended for
nano-scale devices. One reason is considerable ionized impurity
scattering in highly doped channels, which leads to the weak
current drive. On the other hand, regions in the channel which are
further from the gate are more vulnerable to the short channel
effects. Here we dope the channel with a trapezoidal profile of
doping density, vertically. As a result, in addition to the higher
potential barrier at the depth of the channel, a slope in the po-
tential barrier is created in the channel due to the doping differ-
ence between the top of channel and the bottom of channel as
 H. Shahnazarisani, S. Mohammadi / Physica E 69 (2015) 27–33 31

Fig. 7. The profile of electron concentration along channel for (a) DV-SOI MOSFET and (b) C-SOI MOSFET structures at VGS ¼  2 V, and VDS ¼10 V conditions.

Fig. 8. Maximum temperature and gate-substrate capacitance versus thickness of
the silicon nitride layer for VGS ¼  2 V, and VDS ¼10 V.
shown in Fig. 9(a). It can be seen from Fig. 9(b) that a small po-
tential barrier is formed at the channel of the C-SOI structure, and
therefore, the OFF state leakage current is higher. But, in the
proposed DV-SOI structure, the conduction mechanism of the DV-
SOI should now be controlled by the potential barrier and the OFF
state leakage current decreases due to high barrier in the channel.
Furthermore, a slope on the potential profile aids the carrier
transport in the channel. Therefore, we are expecting that the ON
state current intensifies.
In the other word, by using the DV-SOI structure, the pene-
tration of the depletion regions of the reversed biased p–n junc-
tions of the drain and the source to the substrate is diminished. It
is shown that the leakage current of the reverse-biased p–n
junction is a function of junction area and doping concentration
[27].
Fig. 10 shows the DIBL and the threshold voltage of the DV-SOI
and the C-SOI structures for the channel lengths down to 20 nm.
DIBL and threshold voltage roll-off are because of the potential

Fig. 9. Conduction band energy of the (a) DV-SOI MOSFET and (b) C-SOI MOSFET structures at VGS ¼  2 V and VD ¼10 V.
32 H. Shahnazarisani, S. Mohammadi / Physica E 69 (2015) 27–33
Fig. 10. DIBL and threshold voltage of the DV-SOI and C-SOI structures versus
channel length.
barrier reduction in the short-channel device. Vertically trapezoi-
dal doping profile in the channel of the DV-SOI structure mitigates
the dependence of the height of the potential barrier on the drain
bias condition and the channel length variation. The former de-
creases the DIBL, and the latter reduces the threshold voltage roll-
off due to the channel length shrinkage.
As it can be inferred from the figure, when the channel length
decreases below 30 nm, the DIBL effect in the DV-SOI structure is
far less than that in the case of C-SOI structure. The strong de-
pendence of the threshold voltage of the C-SOI structure on the
drain bias is highly undesirable. This means that the channel
conductance goes out of the gate control in the C-SOI structures
with very short channel lengths.
The on–off current ratio (Ion/Ioff) of the DV-SOI is large com-
pared to that of the C-SOI. This can be clearly seen from Fig. 11,
where the Ion/Ioff ratio curves of both DV and C-SOI structures are
plotted against the channel length. Having better on-state drive
current along with lower off-state leakage current in the proposed
structure leads to the considerable improvement in the Ion/Ioff ratio
values.
3.3. High frequency characteristics
In this subsection we investigate the parameters related to the
small signal application of our device. The cut-off frequency, fT,
and maximum oscillation frequency, fmax, are the main parameters
in the high frequency characteristics of a device. The expressions
for the fT and fmax are as following [22–28].
Fig. 11. The ratio of Ion to Ioff (Ion/Ioff) versus channel length for the DV-SOI, and
C-SOI structures.
Fig. 12. Gate-source capacitance as a function of the frequency for DV-SOI MOSFET
and C-SOI MOSFET structures.
gm
fT =
2π (CGS + CGD + Cpar ) (3)
fT R DS
fmax =
2 RG (4)
where CGS and CGD are the gate-source and gate-drain capaci-
tances, Cpar is the parasitic input capacitance, RDS and RG are the
drain–source and gate resistances, and gm is transconductance,
respectively.
Gate–source and gate–drain capacitances for the two structures
are shown in Figs. 12 and 13. It can be inferred from the figures
that the carrier density around junctions is less modulated by
applied signals with higher frequencies. It is due to the gradual
mechanisms of movement, generation and recombination of car-
riers around junctions. This means lower capacitance of junction
for higher frequency signals. The difference between the curves for
C-SOI and DV-SOI in both figures can be attributed to the lower
doping density of the channel surface in DV-SOI structure and
deeper depletion region, hence, the parasitic capacitances of this
structure is lower compared to those of C-SOI structure.
The transconductance of the proposed and conventional
structures is observed in Fig. 14. It is shown that the transcon-
ductance is proportional to Cox/(Cox þ Cs) in which Cs is semi-
conductor capacitance [29,30]. We discussed the dependence of
this capacitance on the frequency in the previous paragraph. This
dependence justifies the variation of transconductance with re-
spect to frequency of applied signal in the figure. It can be inferred
from these figures that the high frequency characteristics of the
DV-SOI transistor are expected to be better, although not sig-
nificantly, than those of C-SOI transistor.
Fig. 13. Gate-drain capacitance as a function of the frequency for the DV-SOI
MOSFET and C-SOI MOSFET structures.
 H. Shahnazarisani, S. Mohammadi / Physica E 69 (2015) 27–33
Fig. 14. Transconductance as a function of the frequency for the DV-SOI MOSFET
and C-SOI MOSFET structures.
4. Conclusion
In this paper, a novel fully depleted silicon-on-insulator (SOI)
MOSFET with the vertical trapezoidal doping profile in the channel
and a Si3N4 layer in the box region has been introduced. To in-
vestigate the characteristics of the proposed structure, we have
simulated the transistor and compared the results with the si-
mulation results of a conventional uniform doping channel fully
depleted SOI MOSFET (C-SOI). The results show that the trape-
zoidal doping distribution in the channel region leads to the short
channel effects improvement. Hence, the dependence of the
threshold voltage on the channel length and the drain bias is weak
in the DV-SOI rather than in the C-SOI structure. Additionally,
compared to the C-SOI transistor, the higher on–off current ratio
(Ion/Ioff) is achieved in the DV-SOI structure. The other idea used in
this work was reduction of the thermal conductivity of the buried
insulator to mitigate the self-heating effect. Utilization of the Si3N4
layer as buried oxide considerably improved the self-heating effect
in the SOI-MOSFET, especially for the high temperature MOS ap-
plications. Simulation results demonstrated that the maximum
temperature in the active region of the proposed structure re-
duces. Furthermore, we investigated the main small signal para-
meters of the both devices and showed that the operating fre-
quency of our transistor is higher than that of the conventional SOI
transistor. Finally, the superior performance characteristics of the
novel structure make it a potential candidate for VLSI low power
integrated circuits.
References
[1] V. De, S. Borkar, Technology and design challenges for low power and high
performance, Proc. Int. Symp. Low Power Electron Des. (1999) 163e168.
[2] R.H. Dennard, F.H. Gaensslen, V.L. Rideout, E. Bassous, Design of ion-implanted
MOSFET's with very small physical dimensions, IEEE J. Solid State Circ. 9 (5)
(1974) 256e268.
[3] D.G. Borse, K.N.M. Rani, K.J. Neeraj, A.N. Chandorkar, J. Vasi, V.R. Rao, B. Cheng,
J.C.S. Woo, Optimization and realization of sub-100-nm channel length single
Halo p-MOSFETs, IEEE Trans. Electron Devices 49 (6) (2002) 1077e1079.
[4] G. Nicholas, B.D. Jaeger, D.P. Brunco, P. Zimmerman, G. Eneman, K. Martens,
M. Meuris, M.M. Heyns, High-performance deep submicron ge pMOSFETs with
halo implants, IEEE Trans. Electron Devices 54 (9) (2007) 2503e2511.
33
[5] S. Chakraborty, A. Mallik, C.K. Sarkar, V.R. Rao, Impact of halo doping on the
subthreshold performance of deep-submicrometer CMOS devices and circuits
for ultralow power analog/mixed-signal applications, IEEE Trans. Electron
Devices 54 (2) (2007) 241e248.
[6] R.J.E. Hueting, A. Heringa, Analysis of the subthreshold current of pocket or
halo-implanted nMOSFETsl, IEEE Trans. Electron Devices 53 (7) (2006)
1641e1646.
[7] A. Bansal, K. Roy, Asymmetric halo CMOSFET to reduce static power dissipa-
tion with improved performance, IEEE Trans. Electron Devices 52 (3) (2005)
397e405.
[8] Morteza Rahimian, A.A. Orouji, Nanoscale SiGe-on-insulator (SGOI) MOSFET
with graded doping channel for improving leakage current and hot-carrier
degradation, Superlattice. Microstruct. 50 (2011) 667e679.
[9] Ali A. Orouji, Hossein Elahipanah, A novel nanoscale 4H-SiC-on-insulator
MOSFET using step doping channel, IEEE Trans. Devices Mater. Reliab. 10 (1)
(2010) 92e95.
[10] S. Francis Balestra, M. Cristoloveanu, J. Benachir, Brini, Double-gate silicon-on-
insulator transistor with volume inversion: a new device with greatly en-
hanced performance, IEEE Electron Devices Soc. 8 (1987) 410–412.
[11] G.D. Wilk, R.M. Wallace, J.M. Anthony, High-k gate dielectrics: current status
and materials properties, IEEE 85 (1997) 486.
[12] Ali A. Orouji, M. Jagadesh Kumar, Shielded channel-double gate (SC-DG)
MOSFET: a novel device for reliable nanoscale CMOS applications, IEEE Trans.
Device Mater. Reliab. 5 (3) (2005) 509e514.
[13] Mohammad K. Anvarifard, Ali A. Orouji, Voltage difference engineering in SOI
MOSFETs: a novel side gate device with improved electrical performance,
Mater. Sci. Semicond. Process. 16 (2013) 1672–1678.
[14] Z. Lun, D.S. Ang, C.H. Ling, A novel subthreshold slope technique for the ex-
traction of the buried-oxide interface trap density in the fully depleted SOI
MOSFET, IEEE Electron Devices Lett. 21 (2000) 411–413.
[15] A. Kawamoto, H. Mitsuda, Y. Omura, Design guideline for minimum channel
length in silicon-on-insulator (SOI) MOSFET, IEEE Trans. Electron Devices 50
(2003) 2303–2305.
[16] H. Xiao, R. Huang, J. Liang, H. Liu, Y. Tian, R. Runsheng, Y. Wang, The localized-
SOI MODFET as a candidate for analog/RF applications, IEEE Trans. Electron
Devices 54 (2007) 1978–1984.
[17] R. Rao, N. Das Gupta, A. Das Gupta, Study of Random Dopant Fluctuation ef-
fects in FD-SOI MOSFET using analytical threshold voltage model, IEEE Trans.
Device Mater. Reliab. 10 (2010) 247–253.
[18] A. Majumdar, C. Ouyang, S.J. Koester, W. Haensch, Effects of substrate or-
ientation and channel stress on short-channel thin SOI MOSFETs, IEEE Trans.
Electron Devices 57 (2010) 2067–2072.
[19] K. Kim, J.G. Fossum, Double-gate CMOS: symmetrical-versus asymmetrical-
gate devices, IEEE Trans. Electron Devices 48 (2001) 294–299.
[20] M. Rahimian, A.A. Orouji, A novel nanoscale MOSFET with modified buried
layer for improving of AC performance and self-heating effect, Mater. Sci.
Semicond. Process. 15 (2012) 445–454.
[21] J.P. Colinge, C.A. Colinge, Physics of Semiconductor Devices, Springer Science &
Business Media, USA, 2005.
[22] Ali A. Orouji, Hadi Shahnazarisani, Mohammad K. Anvarifard, Simulation
analysis of a novel dual-trench structure for a high power silicon-on-insulator
metal–semiconductor field effect transistor, Mater. Sci. Semicond. Process. 26
(2014) 506–511.
[23] L.J. McDaid, S. Hall, P.H. Mellor, W. Eccleston, J.C. Alderman, Physical origin of
negative differential resistance in SOI transistors, Electron. Lett. 25 (1989) 827.
[24] S.M. Sze, Physics of Semiconductor Devices, Wiley, Hoboken, NJ, 1981
(Chapter 3).
[25] D.K. Sharma, K.V. Ramanathan, Modeling thermal effects on MOS IV char-
acteristics, IEEE Electron Device Lett. 4 (1983) 362.
[26] N. Yasuda, S. Ueno, K. Taniguchi, C. Hamaguchi, Y. Yamaguchi, T. Nishimura,
Jpn. J. Appl. Phys., Part 1 Regul. Pap., Short Notes Rev. Pap. 30 (1991) 3677.
[27] R. Pierret, Semiconductor Device Fundamentals, 235e300, Addison-Wesley,
MA, 1996 (Chapter 6).
[28] Hadi Shahnazarisani, Ali A. Orouji, Mohammad K. Anvarifard, A novel SOI
MESFET by π-shaped gate for improving the driving current, J. Comput.
Electron., Springer Science Business Media, New York (2014) http://dx.doi.org/
10.1007/s10825-014-0569-9.
[29] U. Sharma, R.V.H. Booth, M.H. White, Static and dynamic transconductance of
MOSFETs, IEEE Trans. Electron Devices 36 (1989) 954.
[30] S. Johansson, M. Berg, K. Persson, E. Lind, A high-frequency transconductance
method for characterization of high-k border traps in III–V MOSFETs, IEEE
Trans. Electron Devices 60 (2012) 776.