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Reduction of Leakage Power & Noise for DRAM Design using Sleep
Transistor Technique
Abstract-In this paper the analysis of DRAM logic RAM (SRAM) and Dynamic RAM (DRAM) . The
compatible 3T cell has been shown. Due to its high SRAM cell consist of a latch, it does not need to be
density and low cost of memory, it is universally used refreshed as the cell transistor holds the data as
by the advanced processor for on chip data and long as the power supply is not cut-off. The DRAM
program memory. DRAM has transistor-capacitor cell comprise of a capacitor to store binary
cell structure, where capacitor is charged to produce information and a transistor to access the capacitor,
1 or 0. Memory array, which is arranged in row and hence the information degraded constantly so the
column, is word line and bit line respectively. Here I DRAM cell need to be refreshed periodically.
have proposed sleep transistor technique at 3T dram
According to the structure of SRAM, it needs more
with semantic design, for improvement of leakage and
also calculated stability by calculating noise, slew rate transistor in order to store certain amount of data,
and settling time. This circuit proposed two voltage but a DRAM modules needs a transistor and a
source are connected to bit line and bit line bar capacitor for every bit of data whereas SRAM
respectively. switching of main transistor is needs 6 transistor i.e. DRAM has the 6 time larger
performed by word line, which is at low for write capacity with a similar number of transistors to an
operation and high for read operation. The SRAM module, this ultimately reduces the price of
simulation result shows that when a wide range of the memory. Due to its low price DRAM has
operating voltage is taken, which is from 0.7 to 1.3v become main memory in personal computers and
then it is observed that low voltage operation is
engineering workstations. SRAM is mainly used
suitable for low slew rate or low read access time and
the leakage current reduced as increase in the range for the high speed and low power consumption, so
of operating voltage. At 0.7v the leakage current is it is mainly used for cache memory in
595.4×10-12 amp, slew rate is 6.96×103 dB, noise microprocessor [2]-[3]. We proposed conventional
measurement is 5.995×10-14, settling time is 46.63×10- dynamic random access memory using 3 transistor
9
. The design has been carried out at the 45 cells with structural support to enable high
nanometre scale technology on cadence virtuoso performance designs, which is tolerant to process
simulating tool. variations for future generation of high
performance microprocessors. This paper describes
Keywords: DRAM, Leakage current, Leakage power, the parameters' variation in accordance with the
Slew Rate, Noise measurement, Settling time. operating voltage in nanotechnology [3].
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tunnelling leakage , sub-threshold leakage and rate capability (in volts / second) at all points in an
reverse bias band to band tunnelling junction amplifier which have to satisfy the condition
L 400 46.64
e p 350 46.62
300
a o 46.6
250
k w 200 46.58
leakage power
a e 150 0.7 0.8 0.9 1 1.1 1.2 1.3
g r 100 Voltage (volts)
e 50
0
0.7 0.9 1.1 1.3 Figure.6 shows improving result of settling time in 3T DRAM
voltage (volts) cell during Read operation
82
VI. CONCLUSION
Noise measurement (E-14)
We have proposed a 3T DRAM cell with sleep
transistor technique in which we present read/write
6 operation at a range of operating supply voltage. In
5.995 this paper it is observed that by adding up
5.99
Noise meas.
References
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