IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 63, NO.

10, OCTOBER 2016 919

Compensation Method for Multistage Opamps With

High Capacitive Load Using Negative Capacitance
Amirhossein Rasekh, Student Member, IEEE, and M. Sharif Bakhtiar, Member, IEEE

Abstract—It is shown that negative capacitance (NC) circuits

can be systematically used to improve the gain–bandwidth product
of the operational amplifiers (opamps). The NC circuit moves the
nondominant pole of the opamp to higher frequency by decreasing
the parasitic capacitance of the critical node. The impedance at the
input of the NC circuits is neither purely capacitive nor negative at
all frequencies. A design guide is presented by deriving the circuit
model for a conventional NC circuit and investigating the extent of
the improvement that can be achieved in a circuit by the use of the
NC circuit. The model is then used to present the design guide for
widebanding the multistage opamps with large capacitive loads.
Based on the proposed method, a three-stage opamp with a 15-nF
capacitive load was designed and fabricated in a 0.18-μm CMOS Fig. 1. (a) Cross-coupled NC circuit. (b) Circuit model for the NC circuit.
process. The measurements confirm that the opamp satisfies the
design target of 1.5-MHz bandwidth at the power consumption of and low BW at the presence of a large load capacitance have
75 μW. been proposed for three-stage opamps. An impedance adapting
Index Terms—Large capacitive load, low power, negative capac- compensation method is used in [4], where a serial RC imped-
itance (NC) circuit, operational amplifier (opamp), wideband. ance at the intermediate stage introduces a left half plane (LHP)
zero and boosts the performance without extra power consump-
I. INTRODUCTION tion. However, the driving capability of the opamp is limited to
the capacitive loads of about 150 pF. Current buffer Miller com-

O PERATIONAL amplifiers (opamps) are one of the most

used and often power consuming modules in a large vari-
ety of applications. Opamps are characterized by specifications
such as low frequency gain (AV 0 ), gain–bandwidth product
(GBW), output swing, input noise density, power consumption,
etc. Among all, the GBW of the opamp is most dependent on
the power consumption. This means that higher GBW often
leads to higher power consumption. The demand for extra
power is even more severe when the opamp is to drive a large
capacitive load. In applications such as liquid-crystal-display
drivers [1], where a number of these opamps are needed, the
low-power characteristic is to be an integral part of the design.
Two-stage opamps often present high gain and wide band-
width (BW) at the same time [2]. The BW enhancement of the
pole splitting in two-stage opamps quickly vanishes as the load
capacitance increases, resulting in more power consumption for
higher frequency behavior.
For large capacitive loads, three-stage opamps are used
in low-power and low-voltage applications. The conventional
nested Miller compensation (NMC) method for these opamps,
however, consumes considerable power [3]. A variety of meth-
ods to overcome two major problems of power consumption
pensation (CBMC) is used with cross feedforward paths in [5]
or with dual active capacitive feedback in [6] to drive a load
capacitance up to 0.8 nF. In [1], Yan et al. achieve a GBW of
0.95 MHz with a load capacitance of 15 nF by using CBMC
with active LHP zero. By using active LHP zero at the interme-
diate stage, the nondominant pole is cancelled; however, active
LHP zero itself generates two poles that degrade the GBW.
Instead of adding an LHP zero, a negative capacitance (NC)
circuit can be used to lower the effective capacitance of a critical
node and hence remove the nondominant pole. The equivalent
circuit of the NC circuit includes resistive and capacitive compo-
nents. The application of the NC circuit for widebanding should
therefore consider the effect of parasitic components, additional
power consumption, and the frequency band of the circuit.
In this brief, first, in Section II, the NC circuit is modeled, and
the pole-zero behavior of a circuit with a low frequency pole at
the presence of the NC circuit is studied. In Section III, CBMC
is analyzed for large capacitive loads, and a design guide
for the application of the NC circuit to multistage opamps is
given. Section IV describes the design of a three-stage opamp,
with the measurement results of the fabricated opamp given in
Section V. The conclusions are drawn in Section VI.

Manuscript received December 28, 2015; accepted February 29, 2016. Date II. NC C IRCUIT
of publication March 3, 2016; date of current version September 22, 2016. This
brief was recommended by Associate Editor T. Ge. A. NC Circuit Model
The authors are with the Department of Electrical Engineering, Sharif
University of Technology, Tehran 11365-9363 , Iran (e-mail: rasekh@ee.sharif. A conventional NC circuit consisting of two cross-coupled
edu; msharif@sharif.edu). n-channel transistors is shown in Fig. 1(a). The output re-
Color versions of one or more of the figures in this brief are available online
at http://ieeexplore.ieee.org. sistances of the current sources are both assumed to be R
Digital Object Identifier 10.1109/TCSII.2016.2538138 (the 1/2 coefficient read for the capacitor is used to simplify
1549-7747 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
920 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 63, NO. 10, OCTOBER 2016

Fig. 3. Pole of the circuit shown in Fig. 2(d) (pN ) versus k.

circuit now has one LHP zero and two poles. To investigate the
mechanism of the NC circuit, we define
Fig. 2. Equivalent model of a node after adding (a) ideal NC circuit, (b) real u  gm R0 (4)
NC circuit model, (c) normalized NC circuit model, and (d) approximation of C
normalized NC circuit model. k (5)
C0
R
ρ . (6)
the formulas). Assuming that M1 and M2 are matched and are R0
in the saturation regime, the impedance seen from the drain of Rewriting (3) in terms of simplifying parameters u, k, and ρ
M1 and M2 can be derived as gives (7), shown at the bottom of the page.
2 [R(gm + Cgs s) + RCs + 1] The poles and the zero of (7), normalized by the original
Zin = (1) circuit pole location p0 , can then be calculated as
(−gm + Cgs .s)(RCs + 1)
uρ + 1 u
where gm and Cgs are the transconductance and gate–source z1n = ≈ (8)
ρk k
capacitance of M1 and M2 , respectively. With gm RC  Cgs , √
uρ(1 − k) + ρk + 1 − Δn
(1) can be approximated as p1n = (9)
2ρk
√
2 2R uρ(1 − k) + ρk + 1 + Δn
Zin = − . (2) p2n = (10)
−gm + Cgs s RCs + 1 2ρk

From (2), The equivalent circuit for the NC circuit can be
derived as shown in Fig. 1(b).
B. Pole Removal Using NC Circuit
The BW of a simple RC circuit (R0 , C0 ) is limited to the
circuit’s pole location at p0 = 1/R0 C0 . To increase the circuit
BW, a negative capacitor −CN is put in parallel with C0
as shown in Fig. 2(a). The circuit BW is then increased to
1/R0 (C0 − CN ). Ideally, the BW could be infinitely increased
if CN was made equal to C0 . In reality, however, CN is not
just a negative capacitor and is to be replaced with its half
circuit model obtained from Fig. 1(b). By replacing CN with its
model, as shown in Fig. 2(b), and assuming Cgs  C and C0 ,
the circuit transfer function ZT = VA /Iin can be calculated as
in (3), shown at the bottom of the page. As seen from (3), the
where
Δn = [uρ(1−k)]2 + 2uρk(1−ρ) + 2uρ(1−ρk 2) + (1−ρk)2.
(11)
The zero (z1n ) is greater than (p1n , p2n ) and is at high frequen-
cies. At first glance, assume large values for u; then, the NC
circuit can be approximated with a first-degree circuit as shown
in Fig. 2(d) with a pole located at
ρ−1
pN = (12)
ρ(1 − k)
where pN is the pole frequency normalized to p0 . As can
be seen from (12) and is shown in Fig. 3, the circuit BW is
fairly insensitive to the variation of ρ and grows rapidly as k
approaches 1. It can also be shown that the stability condition
is satisfied for k < 1 and ρ > 1.

R0 (RCs + gm R + 1)
ZT = (3)
RR0 CC0 s2 + (RC + R0 C0 + gm RR0 C0 − gm RR0 C)s + (gm R − gm R0 + 1)

R0 (ρk(R0 C0 s) + uρ + 1)
ZT = 2 (7)
ρk(R0 C0 s) + (ρk + 1 + uρ(1 − k)) (R0 C0 s) + (uρ − u + 1)
RASEKH AND BAKHTIAR: COMPENSATION METHOD FOR MULTISTAGE OPAMPS WITH HIGH CAPACITIVE LOAD 921

Fig. 4. Pole loci as a function of u.

Fig. 6. Frequency response of ZT with parameters ρ = 10 and k = 0.8.

(a) Magnitude. (b) Phase.
Fig. 5. BW ω−3 dB as a function of u.

For more accurate analysis, a typical pole locus of the circuit

of Fig. 2(c) is shown in Fig. 4. For small values of u, the poles
are real. As u increases, the poles split out of the real axis and
become a pair of complex poles. As u is increased further, the
imaginary parts of the poles reach a maximum, and then, the
branches of the locus return to the real axis. From then on, for
higher values of u, one of the poles moves to high frequencies,
and the other pole reduces to pN . The circuit BW ω−3 dB as
a function of u is plotted in Fig. 5 for typical values of k Fig. 7. Three-stage opamp with CBMC.
and ρ. ω−3 dB is a function of the pole location and reaches
its maximum for u = uopt . As it can be seen from Fig. 5, phase slows down as u increases. That is, the extra power
the circuit BW increases with u until it reaches its maximum consumption for higher u moves the phase shift to higher fre-
at uopt and remains almost constant for higher values of u. quencies by reducing the circuit phase shift at low frequencies
That is, increasing u beyond u = uopt increases circuit power which potentially improves the phase margin (PM).
consumption without further improvement in the circuit BW.
The value of uopt and the corresponding ω−3 dBmax can be
derived by calculating ω−3 dB from (7) and solving III. A PPLICATION OF NC C IRCUIT TO M ULTISTAGE
H IGH C APACITIVE L OAD O PAMPS
d(ω−3 dB )
=0 (13) In a three-stage opamp with NMC, it can be shown [3] that,
du
for stability, the GBW of the circuit is constrained by
which gives gm1 gm3
GBW = ≤ (17)
2k(ρ − 1) Ca1 4CL
uopt ≈ (14)
ρ(1 − k)2
√ where gm1 and gm3 are the transconductance of the first and
2(ρ − 1) √
ω−3 dBmax ≈ = 2pN . (15) third stages, respectively, Ca1 is the compensation capacitor,
ρ(1 − k) and CL is the load capacitor. As indicated by (17), the GBW
reduces when the load capacitance increases, which makes
Assuming a typically large value for ρ and taking u = uopt , the
the circuit not suitable for the applications with large load
transfer function of Fig. 2(c) that is given in (7) reduces to
capacitance. To alleviate the problem, let us consider the three-
 
R0 s + (1−k) 2 stage opamp with the compensation capacitance Ca followed
2
ZT = 2  3−k  . (16) by a current buffer gmc as shown in Fig. 7. Assuming that the
2
s + 1−k s + (1−k) 2 gain of each stage (gmi Ri ) is sufficiently greater than 1, CL is
much larger than the other capacitors, and 1/R1 C1 , 1/R2 C2 
The frequency response of ZT [see (7)] is plotted in Fig. 6. gmc /Ca , the circuit transfer function can be approximated as in
As expected and shown in Fig. 6, the circuit BW increases (18), shown at the bottom of the next page, where p1 = 1/R1 C1
with u until the BW reaches its maximum and remains almost and p2 = 1/R2 C2 are the poles at the output of the first and
unchanged with further increase in u, while the decline in the second stages, respectively, and α = gm1 gm2 gm3 R1 R2 /CL .
922 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 63, NO. 10, OCTOBER 2016

3) To calculate the NC circuit parameters (k, u, and ρ),

we first choose ρ as large as possible. The maximum
frequency that the pole of a given circuit can be moved to,
using the NC circuit, is given in (15) where ω−3 dB,max is
normalized to the original pole location. Then, from (15),
we can write
√
3 2(ρ − 1)
x = (22)
ρ(1 − k)
Fig. 8. Pole locus of (18) as Ca increases from 0. from which, for ρ  1, k can be calculated as
√
For the uncompensated opamp, i.e., when Ca is small, the 2
k =1− 3 (23)
lowest circuit pole, being equal to p3 = 1/RL CL , is at the x
output node due to the very large CL . The large output transistor and finally from (14), we have
exhibits an input capacitance that makes the total capacitance at  √
the output of the second stage considerably larger than that of u = x3 x3 − 2 . (24)
the first stage. It can therefore be assumed that, in a practical
design, the pole order is p3 < p2 < p1 . 4) From (3) to (6), we therefore choose the transconduc-
The pole locus of (18) as a function of Ca is depicted in Fig. 8. tance, the resistor, and the capacitor of the NC circuit as
As Ca increases from zero, the dominant pole at −(1/RL CL ) gmN C = u/R2 , RNC = ρR2 , and CNC = kC2 .
reduces toward −(1/gm2gm3 R1 R2 RL Ca ), i.e., the −3-dB BW
of the circuit for large enough Ca (acceptable PM). The second As an example, suppose that we want to increase the GBW
and third poles, as can be seen from the loci, also move toward by 60%. (i.e., x = 1.6). Assuming a typical value of ρ = 10,
each other and make a pair of complex conjugate poles. k and u can be calculated from (23) and (24) as k = 0.65 and
The PM with GBW  p−3 dB that is almost equal to u = 11. It is to be noted that, as x is taken larger, the value of
GBW = gm1 /Ca can be derived from (18) as k approaches unity which is the borderline of stability (k is to
⎛  ⎞ be less than 1 for stability) and the circuit PM reduces to zero.
GBW p11 + p12 It can also be seen from (24) that the desire for larger BW that
PM = 90 − tan−1 ⎝ GBW2
⎠. (19) implies larger values for x also stipulates larger values for u that
α
GBW − p1 p2 grows rapidly with x which itself translates to increased power
consumption of the NC circuit.
For a PM of θ, the GBW can be calculated from (18) as
 2
√ p1 +p2 p1 +p2 1 IV. D ESIGN AND I MPLEMENTATION
GBW ≈ 3 αp1 p2 − + ×√ . (20)
3 cot θ◦ 3 cot θ◦ 3 αp p
1 2 A three-stage opamp that employs an NC circuit at the output
of its second stage is shown in Fig. 9(a).
In
 practical cases, the first term in (20) that is equal to
3 The first stage is a folded cascode with the differential input
gm1 gm2 gm3 /C1 C2 CL is dominant, and (20) can be further
pairs M1 and M2 followed by another differential pair M9 and
simplified as
 M10 in the second stage. A common mode feedback is used
√ gm1 gm2 gm3 to define the operating point of the second stage. A simple
GBW ≈ 3 αp1 p2 = 3 . (21)
C1 C2 CL class AB driver comprising M13 to M16 is used for the output
stage. The compensation capacitor (Ca ) is connected from
Therefore, for large CL , the comparison of (21) with (17) shows the output to the source of M5 to form a CBMC topology.
that the CBMC results in a GBW that can be considerably The NC circuit (M17 to M20 ) is connected to the output of the
greater than the GBW of NMC. second stage to remove the second circuit pole. The parameters
The first nondominant pole in the CBMC structure that has of the NC circuit are taken as ρ = 10, k = 0.65, and u = 11.
the highest deteriorating effect on the PM is p2 = 1/R2 C2 . For The NC circuit power consumption is 16% of the total power
further increase in the GBW of the CBMC, the NC circuit can consumption of the opamp.
be added to the second stage of the opamp (parallel to R2 , C2 ). For the sake of comparison, let us assume that the power con-
In order to use the NC circuit for increasing the GBW, we sumed in the NC circuit is used to increase the bias current of the
must pursue the following procedure. second stage for widebanding in the absence of the NC circuit.
1) Let us assume that we want to multiply the GBW by x The bias current of M19,20 is almost equal to the bias current
when x > 1. of M9,10 . If we remove the NC circuit and then double the bias
2) From (21), p2 must be increased by x3 (using the NC current of M9,10 , simulations show that the GBW is improved
circuit). by about 12% as opposed to the 60% improvement achieved

Vout (s) gm 1 gm 2 gm 3 R1 R2 RL
Av (s) = =    (18)
Vin (s) (gm 2 gm 3 R1 R2 RL Ca s + 1) αC gm1 s2
+ s 1 1 αCa
a p1 p2 p1 + p2 + gm1
RASEKH AND BAKHTIAR: COMPENSATION METHOD FOR MULTISTAGE OPAMPS WITH HIGH CAPACITIVE LOAD
Fig. 9. Three-stage opamp employing NC circuit. (a) Schematic. (b) Mi-
crophotograph of the fabricated IC.
Fig. 10. Measurement results. (a) Frequency response. (b) Transient response.
by the NC circuit. This is because, by doubling the bias current
in M9 and √ M10 , the circuit transconductance is improved by a
factor of 2. With respect to (21), this would increase the GBW
√ Solid-State Circuits, vol. 47, no. 9, pp. 2227–2234, Sep. 2012.
by 6 2 = 1.12 which is an improvement of only 12%.
V. E XPERIMENTAL R ESULTS
Fig. 9(b) shows the microphotograph of the fabricated IC
in a 0.18-μm CMOS technology. The measured frequency
response of the opamp with a 15-nF capacitive load is shown
in Fig. 10(a). The low frequency gain is greater than 100 dB,
the GBW is 1.5 MHz (3 MHz for CL = 1 nF), and the total
circuit power consumption is 75 μW. The measured transient
923
TABLE I
P ERFORMANCE S UMMARY AND C OMPARISON W ITH S TATE OF THE A RT
response of the circuit with CL = 15 nF and unity feedback is
given in Fig. 10(b).
Table I compares the opamp of this brief to some of those
reported previously.
VI. C ONCLUSION
It was shown that, by connecting the NC circuit to a node,
one zero and two poles, all at higher frequencies compared to
the original pole, are generated. The location of the poles and
zero can be controlled by the parameters of the NC circuit for a
better circuit BW. It was also shown that the performance of the
three-stage opamps with large capacitive load can be improved
using the NC circuit. The design guide for this application has
been given, and the effectiveness of the proposed method has
been demonstrated by an opamp fabricated to drive a 15-nF
capacitive load.
R EFERENCES
[1] Z. Yan, P.-I. Mak, M. Law, and R. Martins, “A 0.016-mm2 144-μW
three-stage amplifier capable of driving 1-to-15 nF capacitive load with
> 0.95-MHz GBW,” IEEE J. Solid-State Circuits, vol. 48, no. 2,
pp. 527–540, Feb. 2013.
[2] T.-H. Lin, C.-K. Wu, and M.-C. Tsai, “A 0.8-V 0.25-mW current-mirror
OTA with 160-MHz GBW in 0.18-μm CMOS,” IEEE Trans. Circuits
Syst. II, Exp. Briefs, vol. 54, no. 2, pp. 131–135, Feb. 2007.
[3] K. N. Leung and P. Mok, “Analysis of multistage amplifier-frequency
compensation,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl.,
vol. 48, no. 9, pp. 1041–1056, Sep. 2001.
[4] X. Peng, W. Sansen, L. Hou, J. Wang, and W. Wu, “Impedance adapting
compensation for low-power multistage amplifiers,” IEEE J. Solid-State
Circuits, vol. 46, no. 2, pp. 445–451, Feb. 2011.
[5] S. S. Chong and P. K. Chan, “Cross feedforward cascode compensation
for low-power three-stage amplifier with large capacitive load,” IEEE J.
[6] S. Guo and H. Lee, “Dual active-capacitive-feedback compensation for
low-power large-capacitive-load three-stage amplifiers,” IEEE J. Solid-
State Circuits, vol. 46, no. 2, pp. 452–464, Feb. 2011.
[7] D. Comer, D. Comer, J. Perkins, K. Clark, and A. Genz, “Bandwidth
extension of high-gain CMOS stages using active negative capacitance,”
in Proc. IEEE 13th ICECS, Dec. 2006, pp. 628–631.
[8] S. Galal and B. Razavi, “40-Gb/s amplifier and ESD protection circuit in
0.18-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, no. 12,
pp. 2389–2396, Dec. 2004.
[9] Q. Wu et al., “Frequency tuning range extension in LC-VCOs using
negative-capacitance circuits,” IEEE Trans. Circuits Syst. II, Exp. Briefs,
vol. 60, no. 4, pp. 182–186, Apr. 2013.