Elementary Cross-talk (Coupling) Analysis

Madhav P. Desai
February 19, 2011

1 The Problem
Consider the following situation (Figure 1). Two nodes V and A are each being
driven by drivers and terminated by receivers. The load capacitances due to
receivers on the two nodes are CV and CA respectively. In addition, the two
nodes are connected by a coupling capacitance with value Cm .
We can identify two phenomena that result from the presence of the coupling
capacitance.
1. If the node V is being held to a fixed value (say 0V ) by its driver, and
if the node A switches, then a disturbance will be observed at V . This
disturbance may exceed the the noise margin at node V .
2. If the value at V is being switched, then the effective charge sourced from
(or sunk into) the driver of V will depend on whether A is switching or
not, and the direction of the switching at A. Thus, the delay of the driver
for V will vary depending on the activity at A.

2 Coupling noise at V
Consider the first phenomenon described above. The node A is switched from
low to high, and the node B is being maintained at 0V . The switching at node
A causes a disturbance at node V . If we assume that the disturbance at V is
small, then the switching of A will be at a rise-time approximately equal to
tA A
R = Rd (Cm + CA ) (1)
Assume that the node A switches as a linear ramp. An elementary analysis of
the situation shows that the waveform at V is given by
t
Cm RV − V
t A
VV (t) = (1 − e R ) (0 ≤ t ≤ t )
R (2)
tA
R

where tVR = RV (Cm + CV ). Let Vp = VV (tA

R ). Then we further have
t−tA
− R
tV
VV (t) = Vp (1 − e R ) (t > tA
R) (3)

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In other words, the disturbance at V is a pulse with height Vp 1 .
Examining the pulse-height Vp , we find that it can be written as
tA
tV − VR

Vp = KC R (1 − e t
R ) (4)
tA
R

where KC = Cm /(Cm + CV ) is called the coupling constant at V . Some inter-

esting conclusions follow from this equation.

1. If tVR /tA
R → ∞, then Vp → KC .

2. If tA V
R /tR → ∞, then Vp → 0.

3. If tA V
R = tR , then Vp → 0.63KC .

The first situation corresponds to a floating victim and an aggressive driver,

and is the worst-case situation. The second situation corresponds to a weak
aggressor and a strong victim. The last situation is the typical one in a well
designed circuit.
If we look at the scaling trends in well-designed circuits, we have observed
that the maximum length of unbuffered√interconnect lcrit scales as S 3/2 . Thus,
the coupling capacitance Cm scales as S (because per-unit length lateral ca-
pacitance scales as 1/S). Also, the load capacitance (due to devices) scales as
√ S.
Thus, in well designed circuits, we expect that KC will scale as (1+A)/(1+A √S)
where A = CV /Cm . When CV >> Cm , this scaling is proportional to 1/ S,
but since the gap between Cm and CV narrows with scaling, the scaling factor
is getting closer to 1. We conclude that this coupling is already a problem in
sub 100nm circuits and is going to get worse, but only marginally (in the limit,
as S → 0, the value of KC → 1). Also note that if V and A are short wires
whose lengths are also scaled, then KC scales as (1 + A)/(1 + AS) (Why?). So,
in well-designed circuits coupling in ”long wires” scales better than coupling in
”short wires”2 .
What are the obvious solutions? Making the victim stronger than the ag-
gressor works well, but results in an asymmetric situation (what if the victim
becomes the aggressor?). Reducing KC is a good option and can be achieved
either by reducing Cm or by increasing CV . The option of increasing CV is
clearly wasteful if applied indiscriminately. Thus, reducing Cm appears to be
the most attractive option, and can be achieved either by increasing the spacing
or by introducing shield lines between the V and A lines. This option seems to
be counter-productive because of the reduction in signal density. But in fact the
use of shield lines may improve the available bandwidth inside a VLSI system
[1].
1 The width of the pulse will depend on tVR and tR
A
2 Of course, if the wires V and A were 1cm long without any buffering, the peak noise
would scale as 1/S 2 (why?), but this would be a terrible design in the first place.

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2.1 Reducing the number of sensitive signals
If the system is synchronous in nature, then the interference problem can be
contained to a great extent. For example, if the system has a single clock, and
if all state elements in the circuit are positive edge triggered, then it really
doesnt matter if there is coupling interference in most signals as long as they
have settled before they are sampled by a clock edge. In fact, only the clock
signal needs to be protected, and this can be done by shielding. Thus, choosing
an appropriate design paradigm (for example, synchronous positive edge trig-
gered) can simplify this problem considerably3 . One still has to pay attention to
interference effects in memories etc, but these are special and well-understood
cases.

3 Delay Variation
Note that the delay of the driver for V can vary in the range

RV CV ≤ Delay ≤ RV (CV + 2Cm ) (5)

depending on the activity at A. If we assume that the nominal delay of the

driver for V corresponds to the case when V switches while A is held constant,
then we find that
|ActualDelay − N ominalDelay|
max = KC (6)
N ominalDelay

Thus, the greater the coupling the greater the (relative) uncertainty in the delay
of the driver.
This delay variation in turn has two side-effects
1. The maximum clock-period in a synchronous system will need to be larger
than the worst-case maximum delay of a logic path. The delay variation
shown above will result in an overly conservative and hence inefficient
choice of clock-period.

2. The throughput of a buffered wire will be determined by its bit period,

which will need to be larger than the maximum delay incurred in any of
the buffers. The delay variation will thus impact the maximum rate at
which data can be sent along the wire.
Thus, if we look at this issue, we find that controlling KC has a direct
impact on the efficiency and performance of the system. In particular, the
use of shielding to reduce KC may reduce the effective signal density, but can
improve the overall efficiency of the system.
3 The synchronous model is not perfect either, but it is the easiest to work with.

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 V

Cc

Figure 1: Capacitive Coupling

References
[1] Vani Prasad, “Standardization of Interconnects: Towards an Interconnect
Library in VLSI Design”, Ph.D. Thesis, IIT Bombay, May 2006.