Vl7211 Vlsi Lab-Ii Manual

Ex.
No:
Date :
Frequency response and Noise analysis of Source follower

AIM:
To construct and test the frequency response and noise analysis of Source
follower using Tanner EDA tool.
SOFTWARE REQUIRED:
1) Simulation tool – Tanner EDA v16.0 S-Edit.
2) Simulation tool – Tanner EDA v16.0 T-Spice.
3) Simulation tool – Tanner EDA v16.0 W-Edit.
STEPS TO CREATE A SCHEMATIC AND RUN SIMULATION:

1) Create a New design
 File → New → New Design
2) Create a cell
 Cell → New View
3) Add the Library
 File → Open → Add Library
 "C:\Users\VLSI1\Documents\TannerEDA\TannerTools
v16.0\Process\ Generic_250nm\ Generic_250nm.tanner"
4) Draw the schematic diagram
 Select the specific library → component → Instance and select
necessary options in the instance and place the component in the cell.
5) Load the Library
 Setup → General → Library Files
6) Setup the Simulation
 Select the analysis type → Give the specifications for the required
analysis
7) Run the simulation
 Tools → Start Simulation
CIRCUIT DIAGRAM:
OUTPUT:
FREQUENCY RESPONSE:
NOISE ANALYSIS:
**** Noise Analysis Temperature = 25.0 Deg. C Tnom = 25.0 Deg. C
Frequency 1.0000 Hz
**** MOSFET squared noise voltages (sq V/Hz)
MM1
RD 0.
RS 0.
ID 14.9623a
FN 0.
RX 2.0936k
TOT 14.9623a
**** Resistor squared noise voltages (sq V/Hz)
RR1
R 12.0284a
FN 0.
RX 2.0936k
TOT 12.0284a
Total output noise voltage = 26.9907a Sq V/Hz
= 5.1953n V/Rt(Hz)
Transfer function value:
V(N_1)/VV0 = 531.0872m
Equivalent input noise at VV0 = 9.7823n
Noise integral from 1.0000 Hz to 1.0000 Hz
Total integrated output noise voltage = 0. V
Total equivalent input noise voltage = 0. V
Frequency 10.0000 Hz
MM1
RD 0.
RS 0.
ID 14.9623a
FN 0.
RX 2.0936k
TOT 14.9623a
RR1
R 12.0284a
FN 0.
RX 2.0936k
TOT 12.0284a
= 5.1953n V/Rt(Hz)
V(N_1)/VV0 = 531.0872m
Total integrated output noise voltage = 15.5858n V
Total equivalent input noise voltage = 29.3469n V
Frequency 100.0000 Hz
MM1
RD 0.
RS 0.
ID 14.9623a
FN 0.
RX 2.0936k
TOT 14.9623a
RR1
R 12.0284a
FN 0.
RX 2.0936k
TOT 12.0284a
= 5.1953n V/Rt(Hz)
V(N_1)/VV0 = 531.0872m
Frequency 1.0000k Hz
MM1
RD 0.
RS 0.
ID 14.9623a
FN 0.
RX 2.0936k
TOT 14.9623a
RR1
R 12.0284a
FN 0.
RX 2.0936k
TOT 12.0284a
= 5.1953n V/Rt(Hz)
V(N_1)/VV0 = 531.0872m
Noise integral from 1.0000 Hz to 1.0000k Hz
MM1
RD 0.
RS 0.
ID 14.9623a
FN 0.
RX 2.0936k
TOT 14.9623a
RR1
R 12.0284a
FN 0.
RX 2.0936k
TOT 12.0284a
= 5.1953n V/Rt(Hz)
V(N_1)/VV0 = 531.0872m
MM1
RD 0.
RS 0.
ID 14.9623a
FN 0.
RX 2.0936k
TOT 14.9623a
RR1
R 12.0284a
FN 0.
RX 2.0936k
TOT 12.0284a
= 5.1953n V/Rt(Hz)
V(N_1)/VV0 = 531.0872m
Total integrated output noise voltage = 1.6429u V
Total equivalent input noise voltage = 3.0934u V
Frequency 1.0000X Hz
MM1
RD 0.
RS 0.
ID 14.9623a
FN 0.
RX 2.0936k
TOT 14.9623a
RR1
R 12.0284a
FN 0.
RX 2.0936k
TOT 12.0284a

= 5.1953n V/Rt(Hz)
V(N_1)/VV0 = 531.0872m
Noise integral from 1.0000 Hz to 1.0000X Hz
MM1
RD 0.
RS 0.
ID 14.9623a
FN 0.
RX 2.0936k
TOT 14.9623a
RR1
R 12.0284a
FN 0.
RX 2.0936k
TOT 12.0284a
= 5.1953n V/Rt(Hz)
V(N_1)/VV0 = 531.0871m

MM1
RD 0.
RS 0.
ID 14.9617a
FN 0.
RX 2.0936k
TOT 14.9617a
RR1
R 12.0279a
FN 0.
RX 2.0936k
TOT 12.0279a
= 5.1952n V/Rt(Hz)
V(N_1)/VV0 = 531.0803m
RESULT:
Thus the source follower was constructed, the frequency response was
plotted and the noise analysis was performed using Tanner EDA tool.
MARKS AWARDED SIGNATURE OF THE FACULTY

Ex. No:2
Date : 18-02-2016
Design and Simulation of Two Stage Operational Amplifier
AIM:
To design and test the functionality of Two Stage Operational Amplifier using
Tanner EDA tool.
SOFTWARE REQUIRED:

2) Create a cell
3) Add the Library
 "C:\Users\VLSI1\Documents\TannerEDA\Tanner Tools
5) Load the Library
analysis
DESIGN:
SPECIFICATION:
If KN'=120µA/V2, KP'= 25 µA/V2, VTN = |VTP| = 0.5V, λN = 0.06V-1, and λP =0.08V-1,
design a two-stage, CMOS op amp that meets the following specifications. Assume
the channel length is to be 0.5µm and the load capacitor is CL = 10pF.
Av > 3000V/V VDD =2.5V GB = 5MHz SR > 10V/µs
60° phase margin 0.5V<Vout range < 2V ICMR = 1.25V to 2V Pdiss ≤ 2mW
SOLUTION:
1) The first step is to calculate the minimum value of the compensation capacitor Cc,
Cc > 0.22CL 1
Cc > 0.22 × 10pF = 2.2 pF
2) Choose Ccas 3pF. Using the slew-rate specification and Cc calculate I5.
I5 = SR × Cc 2
I5= (10x10-6) × (3x10-12)= 30µA
3) Next calculate (W/L)3 using ICMR requirements (use worst case
thresholds±0.15V).
5
3
(max) | 0 |(max) (min) 2
( ) = 30
( )
( ) ( )
4) Now we can check the value of the mirror pole, P3, to make sure that it is in fact
greater than 10GB. Assume the Cox = 6fF/µm2. The mirror pole can be found as
4
2
√
= -1.25 × 109(rads/sec)
( )
or 199MHz. Thus, P3, is not of concern in this design because P3>>10GB.

5) The next step in the design is to calculate gm1to get
gm1= GB. CC; 5

gm1 = (5x106)(2Π)(3x10-12) = 94.25µS
Therefore, (W/L)1 is
2 2
25
( ) ( ) 2
2 20 5
6) Next calculate VDS5,
( ) ( ) √ ( ) 6
2 5
5
5 ( ) 2
Using VDS5 calculate (W/L)5 from the saturation relationship.

( )
( )
( )
7) For 60° phase margin, we know that
√
gm6 = 2.2gm2(CL/Cc) and = =√ 7
√
S6 = S4
gm6 ≥ 0gm1 ≥ 2.5µS

Assuming that gm6 = 942.5µS and knowing that gm4 = 150µS, we calculate (W/L)6 as
W
( ) 0
L
8) Calculate I6 using the small-signal gm expression:

8
( 25 0 )2
2 5
(2)(25 0 )( 5)
Calculating (W/L)6 based on Vout(max), gives a value of 15. Since 190 exceeds the
specification and gives better phase margin, we choose (W/L)6 = 190 and I6 = 95µA.
With I6 = 95µA the power dissipation is Pdiss = 2.5V (30µA+95µA) =0.3125mW
9) Finally, calculate (W/L)7
(W/L)7= 6
Let us check the Vout(min) specification although the W/L of M7 is so large that this is
probably not necessary. The value of Vout(min) is
(2 5)
Vout(min)=VDS7 (sat) = √( = 0.281V
20 20)
Which is less than required. At this point, the first cut design is complete.
10) Now check to see that the gain specification has been met
AV = ( ) ( )
9
( ) ( )
AV = ( )( )( )
= 3180V/V
)(
CIRCUIT DIAGRAM:
OUTPUT:
RESULT:
Thus Two Stage Operational Amplifier was designed and the functionality is
verified using Tanner EDA tool.

Ex.No:3
Date : 25-02-2016
Design and Simulation Cascode Current Mirror

AIM:
To design and test the functionality of Cascode current mirror using Tanner
EDA tool.
SOFTWARE REQUIRED:

2) Create a cell
3) Add the Library
5) Load the Library
analysis
SPECIFICATION:
Consider the Cascode current mirror, where Iin = 100 µA and each transistor
has W/L =10 µm/0.4 µm. Find the minimum output voltage at Vout such that the
output transistors remain in the active region.
DESIGN:
Nominally, Iout = Iin, and thus we can find the small-signal parameters for thiscurrent
mirror to be
gm4 = √2 ( ) = 0.97mA/V
We also have
0
rds2 = rds4 = = =25KΩ
0
The output impedance is given by

rout =rds4[1 + rds2(gm4 + gs4 + gds4)]
rout = 25KΩ[25KΩ (0.97mA/V+ 0.2 × 0.97mA/V+ /25KΩ)] = 52.5KΩ
To find the minimum output voltage, we first need to determine Veff:

2
Veff = √ = 0.205V
( )
Thus, the minimum output voltage is determined to be 2Veff + Vtn=0.98V.

CIRCUIT DIAGRAM:
OUTPUT:
RESULT:
Thus the Cascode current mirror was designed and the functionality was
verified using Tanner EDA tool.

Ex.No:4
Date : 10-03-2016
Design and Simulation of Gate-level modeling
AIM:
To design the universal gates and combinational circuits using gate-level
modeling and verify the functionality.
SOFTWARE REQUIRED:
Simulation tool – Active HDL 8.1SP2
ALGORITHM:
1. Create a working library
 File → New → Workspace
2. Create a design
 File → New → Design
3. Create a file
 File → New → Verilog Source
4. Compile the design

 Design → Compile
5. Load the design

 Simulation → Initialize Simulation
6. Run the Simulation

 Simulation → Run For
NAND GATE:
SYMBOL:
TRUTH – TABLE:
INPUT OUTPUT
a b c
0 0 1
0 1 1
1 0 1
1 1 0
PROGRAM:
module nand2 (c,a,b);
output c;
input a,b;
nand(c,a,b);
endmodule
OUTPUT:
NOR GATE:
SYMBOL:
TRUTH – TABLE:
INPUT OUTPUT
a b c
0 0 1
0 1 0
1 0 0
1 1 0
PROGRAM:
module nor2 (c,a,b);
output c;
input a,b;
nor(c,a,b);
endmodule
OUTPUT:
HALF ADDER:
LOGIC DIAGRAM:
TRUTH – TABLE:
INPUT OUTPUT
a b s c
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
PROGRAM:
module halfadder (c,s,a,b);
output c,s;
input a,b;
xor(s,a,b);
and(c,a,b);
endmodule
OUTPUT:
FULL ADDER:
LOGIC DIAGRAM:
TRUTH – TABLE:
INPUT OUTPUT
cin b a s cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
PROGRAM:
module fulladder (cout,s,a,b,cin);
output cout,s;
input a,b,cin;
wire x1,x2,x3;
xor x0(s,a,b,cin);
and a1(x1,a,b);
and a2(x2,b,cin);
and a3(x3,cin,a);
or o1(cout,x1,x2,x3);
endmodule
OUTPUT:
RESULT:
Thus the universal gates and combinational circuits are designed by using
gate level modeling and the functionality is verified.

Ex.No:5
Date : 19-03-2016
Design and Simulation of Switch-level modeling
AIM:
To design the combinational circuits using switch-level modeling and verify
the functionality.
SOFTWARE REQUIRED:
Simulation tool – Active HDL 8.1SP2
ALGORITHM:
1. Create a working library
 File → New → Workspace
2. Create a design
 File → New → Design
3. Create a file
 File → New → Verilog Source
4. Compile the design

 Design → Compile
5. Load the design

 Simulation → Initialize Simulation
6. Run the Simulation

 Simulation → Run For
PMOS:
SYMBOL:
TRUTH – TABLE:
INPUT OUTPUT
ctrl in out
0 0 0
0 1 1
1 0 z
1 1 z
PROGRAM:
module pmos1 ( out, in ,ctrl );
output out ;
input in, ctrl ;
pmos(out,in,ctrl);
endmodule
OUTPUT:
NMOS:
SYMBOL:
TRUTH – TABLE:
INPUT OUTPUT
ctrl in out
0 0 z
0 1 z
1 0 0
1 1 1
PROGRAM:
module nmos1 ( out,in,ctrl );
output out ;
input in, ctrl ;
nmos(out,in,ctrl);
endmodule
OUTPUT:
NAND GATE:
LOGIC DIAGRAM:
TRUTH – TABLE:
INPUT OUTPUT
a b y
0 0 1
0 1 1
1 0 1
1 1 0
PROGRAM:
module nand2 ( y, a, b );
output y ;
input a, b ;
wire x;
supply1 pwr;
supply0 gnd;
pmos p1(y,pwr,a);
pmos p2(y,pwr,b);
nmos n1(y,x,a);
nmos n2(x,gnd,b);
endmodule
OUTPUT:
NOR GATE:
LOGIC DIAGRAM:
TRUTH – TABLE:
INPUT OUTPUT
a b y
0 0 1
0 1 0
1 0 0
1 1 0
PROGRAM:
module nor2 ( y, a, b );
output y ;
input a, b ;
wire x;
supply1 pwr;
supply0 gnd;
pmos p1(x,pwr,a);
pmos p2(y,x,b);
nmos n1(y,gnd,a);
nmos n2(y,gnd,b);
endmodule
OUTPUT:
INVERTER:
LOGIC DIAGRAM:
TRUTH – TABLE:
INPUT OUTPUT
in out
0 1
1 0
PROGRAM:
module inverter ( out, in );
output out ;
input in ;
supply1 pwr;
supply0 gnd;
pmos (out, pwr, in);
nmos (out, gnd, in);
endmodule
OUTPUT:
CMOS:
LOGIC DIAGRAM:
TRUTH-TABLE:
INPUT OUTPUT
in pctrl nctrl out
0 0 0 0
0 0 1 0
0 1 0 z
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 Z
1 1 1 1
PROGRAM:
module cmos2 (out, in, nctrl, pctrl );
output out ;
input in, pctrl, nctrl ;
cmos(out, in, nctrl, pctrl);
endmodule
OUTPUT:
RESULT:
Thus the combinational circuits are designed by using switch level modeling
and the functionality is verified.

Ex.No:6
Date : 31-03-2016
Modeling and Synthesis of ASAP scheduling Algorithm

AIM:
To design the ASAP (As Soon As Possible) scheduling algorithm and
implement it in FPGA using Xilinx ISE tool.
SOFTWARE REQUIRED:
1. Simulation tool – Active HDL 8.1SP2
2. Synthesis tool – Xilinx ISE 12.1
MODEL:
Example TI C6000 DSP Processor assembly code
MV .L1 A0,A1
MV .L2 B0,B1
MPY .M1 A1,A2,A3
MPY .M2 B1,B2,B3
MPY .M1 A3,A6,A7
MPY .M2 B3,B6,B7
ADD .L1 A7,B7,A8
ADD .L1 A4,A8,A9
CYCLIC DIRECTIONAL FLOWGRAPH:
A0 B0
A2 A1 B1 B2
A6 × × B6
A3 B3
× ×
A7 B7
+ A4
A8
A9
PROGRAM FOR SIMULATION:
module scheduling_algorithm (clk,clear,A0,B0,A2,B2,A4,A6,A9,B6);
reg [7:0]B1,A1;
reg [16:0]B3,A3;
reg [31:0]B7,A7,A8;
output [31:0]A9;
reg [31:0]A9;
input [7:0]A0,B0,A2,B2,A4,A6,B6;
input clk;
input clear;
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4,s5=3'd5;
reg [2:0]state;
always @(posedge clk)
begin
if(clear)
A9<=0;
else
case(state)
s0:
begin
B1 <= B0;
A1 <= A0;
state = s1;
end
s1:
begin
B3 <= B1[7:0] * B2[7:0];
A3 <= A1[7:0] * A2[7:0];
state = s2;
end
s2:
begin
B7 <= B3[16:0] * B6[7:0];
A7 <= A3[16:0] * A6[7:0];
state= s3;
end
s3:
begin
A8 <= A7 + B7;
state = s4;
end
s4:
begin
A9 <= A4 + A8;
state = s5;
end
default: state=s0;
endcase
end
endmodule
OUTPUT:
PROGRAM FOR FPGA IMPLEMENTATION:

module scheduling_algorithm (clk,clear,A9/*,A0,B0,A2,B2,A4,A6,B6*/);
reg [7:0]B1,A1;
reg [16:0]B3,A3;
reg [31:0]B7,A7,A8;
output [31:0]A9;
reg [31:0]A9;
wire [7:0]A0,B0,A2,B2,A4,A6,B6;
assign A0=8'b11000011;
assign B0=8'b10111100;
assign A2=8'b01110111;
assign B2=8'b10111111;
assign A4=8'b11111111;
assign A6=8'b01000100;
assign B6=8'b11001100;
input clk;
input clear;
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4,s5=3'd5;
reg [2:0]state;
always @(posedge clk)
begin
if(clear)
A9<=0;
else
case(state)
s0:
begin
B1 <= B0;
A1 <= A0;
state = s1;
end
s1:
begin
B3 <= B1[7:0] * B2[7:0];
A3 <= A1[7:0] * A2[7:0];
state = s2;
end
s2:
begin
B7 <= B3[16:0] * B6[7:0];
A7 <= A3[16:0] * A6[7:0];
state= s3;
end
s3:
begin
A8 <= A7 + B7;
state = s4;
end
s4:
begin
A9 <= A4 + A8;
state = s5;
end
default: state=s0;
endcase
end
endmodule
UCF FILE:
NET "clk" LOC = P79;
NET "clear" LOC = P21;
NET "A9<0>" LOC = P132;
NET "A9<1>" LOC = P130;
NET "A9<2>" LOC = P124;
NET "A9<3>" LOC = P122;
NET "A9<4>" LOC = P119;
NET "A9<5>" LOC = P116;
NET "A9<6>" LOC = P114;
NET "A9<7>" LOC = P111;
NET "A9<8>" LOC = P106;
NET "A9<9>" LOC = P101;
NET "A9<10>" LOC = P95;
NET "A9<11>" LOC = P93;
NET "A9<12>" LOC = P87;
NET "A9<13>" LOC = P85;
NET "A9<14>" LOC = P81;
NET "A9<15>" LOC = P78;
NET "A9<16>" LOC = P72;
NET "A9<17>" LOC = P68;
NET "A9<18>" LOC = P65;
NET "A9<19>" LOC = P63;
NET "A9<20>" LOC = P61;
NET "A9<21>" LOC = P57;
NET "A9<22>" LOC = P51;
NET "A9<23>" LOC = P46;
NET "A9<24>" LOC = P44;
NET "A9<25>" LOC = P42;
NET "A9<26>" LOC = P39;
NET "A9<27>" LOC = P36;
NET "A9<28>" LOC = P34;
NET "A9<29>" LOC = P28;
NET "A9<30>" LOC = P26;
NET "A9<31>" LOC = P20;
OUTPUT:
Output of this implementation is displayed in FPGA Board output LED’s. For
the given input, the output is 00000000100001111101101100000011.
RESULT:
Thus the ASAP (As Soon As Possible) scheduling algorithm was designed and
it is implemented in FPGA using Xilinx ISE tool.

Ex.No:7
Date : 03-03-2016
Study of various routing techniques
AIM:
To study the various routing techniques – local routing, channel routing and
global routing.
LOCAL ROUTING:
Local routing is the process of determining theexact patterns that
interconnect sets of terminalsin a given routingarea.
Local routing is opposed to global routing, theprocess of determining through
which routingareas a connection will run without fixing thewiring patterns within
the routing areas.
Local routing is characterized by a number of parameters (each parameter
setting defines a distinct problem type):
* The number of wiring layers,
* The orientation of wire segments in a layer: horizontal, vertical, diagonal or
some combination of these,
* Gridded or gridless routing,
* Presence or absence of obstacles in routing area,
* Stretchable or fixed routing area,
* The constraints on the positions of the terminals: two parallel lines, along a
rectangle, arbitrarily in an area, etc.
* Terminals with a fixed or floating position.
The Lee algorithm is a classical routing technique;it is the basis of many routing
programs.Theone-layer version is presented.
Main points:
* The routing area is a grid of squares.
* A square available for routing is white, onethat is an obstacle is black.
* The goal is to connect all nets.
* A two-point connection is realized by propagating a wave frontfrom the
source terminal outwards until the target terminal is reached.
* The shortest-connection is found by back-tracking from the target to the
source.
* In the case of multi-terminal nets: first two terminals are connected, this
connection is the target for the wave propagation from the third terminal, etc.
* A routed net is an obstacle for the next nets.
Evaluation:
* The algorithm always finds a connection if aconnection exists.
*For two-terminal nets, this connection is theshortest possible; for
multiterminal nets theconnection need not be the shortest
possible(remember: the ‘‘minimal rectilinear Steinertree’’ problem is NP-
complete).
* It can be generalized for multiple layers:wave front expansion in three
dimensions.
* Its time complexity and space complexity isO(n2).
* The quality of its result strongly depends onthe ordering of the nets.
CHANNEL ROUTING:
A channel, also called a two-shore channel, is a routing region boundedby
twoparallel boundaries. For a horizontal channel, fixed terminals are located on
theupper and lower boundaries and floating terminals are allowed on the left and
right(open) ends. The left end may also contain fixed terminals. Thechannel
routingproblem (CRP)is to route a specified net list between two rows of
terminalsacross a two-layer channel. The task of a channel router is to route all the
netssuccessfully in the minimum possible area. Each row ina channel is called a
track. The number of tracks is called the channel width w of the channel. When the
channel length is fixed, the area goal is to minimizechannel width wthe
channelwidth, thechannel width minimization problem.
This section describes channel width minimization problems for
theManhattanrouting model. In order to ensure that two distinct nets are not
shorted,it isnecessary to ensure that no vertical segments overlap and, similarly, no
horizontal segments overlap.
(a) An instance of shift right -1 (b) Its solution using t=s-1+2n/s=7

(c) Its solution using minimum tracks, t=5.
GLOBAL ROUTING:
The purpose of a global router is to decompose a large routing problem into
smalland manageable subproblems (detailed routing). This decomposition is
carriedout by finding a rough path for each net (i.e., sequence of subregions it
passesthrough) in order to reduce chip size, shorten wire length, and evenly
distributethe congestion over routing area. The definition of subregion depends on
whetherthe global router is performed after floorplanning or placement.
In a global routing(i.e., output of a global router), let d(i, j) denote the number
of nets crossingthe border of regions Ri and Rj. Let c(i, j) denote the capacity of the
border ofregions Ri, and Rj (i.e., the maximum number of nets that can cross this
border).An instance of global routing is specified by a collection of regions, a set η
ofmultiterminal nets, and a capacity function C. A k-terminal net is said to
havemultiplicity k . Multiplicity of η is the maximum number of terminals per net,
over all nets in η. The global routing problem (GRP) of an arbitrary instance (η, C) is
tofind a global routing with d(i,j) ≤ c(i, j) for every two adjacent regions Ri, and Rj.
RESULT:
Thus the various routing techniques - local routing, channel routing and
global routing was studied.

Ex.No: 8
Date : 06-04-2016
Simulation of Power Estimation

AIM:
To estimate the power of the SRAM cell (6T) using Tanner EDA tool.
SOFTWARE REQUIRED:

2) Create a cell
3) Add the Library
5) Load the Library
analysis
CIRCUIT DIAGRAM:
Figure-16T CMOS SRAM cell
Figure – 2: SCHEMATIC DIAGRAM OF CMOS SRAM CELL

THEORY:
An SRAM cell is the key SRAM component storingbinary information. A
typical SRAM cell uses twocross-coupled inverters forming a latch and
accesstransistors. Access transistors enable access to the cellduring read and write
operations and provide cellisolation during the not-accessed state. An SRAM cell
isdesigned to provide non-destructive read access, writecapability and data storage
(or data retention) for as longas cell is powered. We will discuss design and
analysisof two different SRAM cells: a six-transistor (6T)CMOS SRAM cell and a
SRAM cell with transmissiongates. We will compare them with respect to power.
Ingeneral, the cell design must strike a balance betweencell area, robustness, speed,
leakage and yield. Powerreduction is one of the most important design
objectives.However, the power cannot be reduced indefinitelywithout
compromising the other parameters. Forinstance, low-power can compromise the
cell area alsospeed of operation. The mainstream six-transistor (6T)CMOS SRAM cell
is shown in Figure-1, fourtransistors (Q1-Q4) comprise cross-coupled
CMOSinverters and two NMOS transistors Q5 and Q6 provideread and write access
to the cell. A 6T CMOS SRAMcell is the most popular SRAM cell due to its superior
robustness, low power and low-voltage operation.
Read Operation:
Prior to initiating a read operation, the bit lines areprecharged to VDD. The
read operation is initiated byenabling the word line (WL) and connecting
theprecharged bit lines, BL and BLB, to the internal nodesof the cell. Upon read
access, the bitline voltage VBL remains at the precharge level. Thecomplementary
bit line voltage VBLB is dischargedthrough transistors Q1 and Q5 connected in
series.Effectively, transistors Q1 and Q5 form a voltagedivider whose output is now
no longer at zero volt and isconnected to the input of inverter Q2-Q4 (Figure -
1).Sizing of Q1 and Q5 should ensure that inverter Q2-Q4do not switch causing a
destructive read.
Write Operation:
During write operation one of the bit lines, BL is driven from precharged
value (VDD) to theground potential by a write driver through transistor Q6.If
transistors Q4 and Q6 are properly sized, then the cellis flipped and its data is
effectively overwritten. Astatistical measure of SRAM cell writeability is definedas
write margin. Write margin is defined as theminimum bit line voltage required to
flip the state of anSRAM cell. The write margin value and variation is afunction of the
cell design, SRAM array size andprocess variation. A cell is considered not writeable
ifthe worst-case write margin becomes lower than theground potential. Note that
the write operation is appliedto the node storing a “ ”. This is necessitated by
thenon-destructive read constraint that ensures that a “0”node does not exceed the
switching threshold of inverterQ2-Q4. The function of the pull-up transistors is only
tomaintain the high level on the “ ” storage node andprevent its discharge by the
off-state leakage current ofthe driver transistor during data retention and to
providethe low-to-high transition during overwriting.
OUTPUT:
POWER CONSUMPTION:
VV1 from time 0 to 1e-006
Average power consumed : 7.850260e-007 watts (0.78uW)
Max power : 1.833361e-004 at time 1.13645e-008 (0.18mW)
Min power : 2.924260e-011 at time 1e-009 (29pW)
RESULT:
Thus the conventional SRAM cell (6T) power was estimated using Tanner
EDA tool.

Ex.No:9
Date : 04-04-2016
Reduction of Power consumption in memories
AIM:
To design and reduce the power consumption of the SRAM cell using Tanner
EDA tool.
SOFTWARE REQUIRED:

2) Create a cell
3) Add the Library
5) Load the Library
analysis
CIRCUIT DIAGRAM:
Figure – 1: LOW POWER SRAM CELL
Figure – 2: SCHEMATIC DIAGRAM OF LOW POWER SRAM CELL

THEORY:
The SRAM cell is shown in Figure-1, itconsists of two transmission gates in
place of pass(access) transistors as shown in Ex. No. 7 Figure -1, this is due tothe fact
that the transmission gates have low voltagedrop compare to pass transistors, also
in the given cellwe have an additional NMOS which acts as a switch andalso it is
necessary to restrict a short circuit currentwhen the data is written in the
elementary cell.However, the read and write operations of given circuitis same as
that of conventional 6T CMOS SRAM cell.
OUTPUT:
VV1 from time 0 to 1e-007
Average power consumed : 5.967543e-008 watts (0.06uW)
Max power : 1.817252e-005 at time 2.05e-008 (0.01mW)
Min power : 1.637509e-011 at time 1e-008 (16.37pW)
COMPARISION TABLE FOR POWER CONSUMPTION REDUCTION:
CONVENTIONAL LOW POWER

Sl.No. PARAMETER
6T SRAM CELL SRAM CELL
1 Average power consumed 0.78uW 0.06uW
2 Max power 0.18mW 0.01mW
3 Min power 29pW 16.37pW
RESULT:
Thus the low power SRAM cell was designed and its power consumption was
compared with the conventional 6T SRAM cell using Tanner EDA tool.

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Ex.

Frequency response and Noise analysis of Source follower

STEPS TO CREATE A SCHEMATIC AND RUN SIMULATION:

Total output noise voltage = 26.9907a Sq V/Hz

**** Noise Analysis Temperature = 25.0 Deg. C Tnom = 25.0 Deg. C

MARKS AWARDED SIGNATURE OF THE FACULTY

STEPS TO CREATE A SCHEMATIC AND RUN SIMULATION:

or 199MHz. Thus, P3, is not of concern in this design because P3>>10GB.

gm1= GB. CC; 5

Using VDS5 calculate (W/L)5 from the saturation relationship.

7) For 60° phase margin, we know that

gm6 ≥ 0gm1 ≥ 2.5µS

8) Calculate I6 using the small-signal gm expression:

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Design and Simulation Cascode Current Mirror

STEPS TO CREATE A SCHEMATIC AND RUN SIMULATION:

The output impedance is given by

To find the minimum output voltage, we first need to determine Veff:

Thus, the minimum output voltage is determined to be 2Veff + Vtn=0.98V.

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4. Compile the design

5. Load the design

6. Run the Simulation

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4. Compile the design

5. Load the design

6. Run the Simulation

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Modeling and Synthesis of ASAP scheduling Algorithm

PROGRAM FOR FPGA IMPLEMENTATION:

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(a) An instance of shift right -1 (b) Its solution using t=s-1+2n/s=7

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Simulation of Power Estimation

STEPS TO CREATE A SCHEMATIC AND RUN SIMULATION:

Figure-16T CMOS SRAM cell

Figure – 2: SCHEMATIC DIAGRAM OF CMOS SRAM CELL

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STEPS TO CREATE A SCHEMATIC AND RUN SIMULATION:

Figure – 1: LOW POWER SRAM CELL

Figure – 2: SCHEMATIC DIAGRAM OF LOW POWER SRAM CELL

COMPARISION TABLE FOR POWER CONSUMPTION REDUCTION:

CONVENTIONAL LOW POWER

1 Average power consumed 0.78uW 0.06uW

2 Max power 0.18mW 0.01mW

3 Min power 29pW 16.37pW

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