Computer Architecture and

Organization:
L06: Instruction Cycle

By: A. H. Abdul Hafez

Abdul.hafez@hku.edu.tr, ah.abdulhafez@gmail.com

1 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 4, 2016

Outlines
1. Fetch and decode
2. Determine the Type of Instruction
3. Instruction set in details
4. End

2 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 4, 2016

Instruction Cycle
 A program residing in the memory unit of the computer
consists of a sequence of instructions.
 The program is executed in the computer by going
through a cycle for each instruction.
 Each instruction cycle in turn is subdivided into a
sequence of subcycles or phases:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if indirect
4. Execute the instruction

3 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 4, 2016

Fetch and Decode
 Initially PC is loaded with the address of the first instruction in the
program
 SC is cleared to 0, providing T0 timing signal.
 The microoperations for the fetch and decode phases are:
T0 : AR  PC
T1 : IR M[AR], PC  PC +1
T2 : D0, ...,D7  decode IR(12-14), ARIR(0-11), IIR(15)
 Since only AR is connected to the address inputs of memory, it is necessary to
transfer the address from PC to AR during the clock transition associated with T0.
 The instruction read from memory is then placed in the IR with the clock
transition of T1
 At the same time PC is incremented by one to prepare it for the address of the
next instruction of the program. At T2, the Opcode in IR is decoded, I bit is
transferred to Flip Flop I, and IR part (0-11) is transferred into AR.

4 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 4, 2016

Fetch and Decode T0 : AR  PC

 To provide the data path for the transfer of PC to AR, we must

apply timing signal T0 to achieve the following connection:

1. Place the content of PC onto the bus by making the bus selection inputs
S2S1S0 equal to 010
2. Transfer the content of the bus to AR by enabling the LD input of AR

 The next clock transition initiates the transfer from PC to AR since

T0=1. (See Mano figure 5.8)

5 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 4, 2016

Fetch and Decode T1 : IR M[AR], PC  PC +1

 For the second statemet, it is necessary to use timing

signal T1 to provide the following conditions in the bus
system
 Enable the read input of memory
 Place the content of memory onto the bus by making S2S1S0= 111
 Transfer the content of the bus to IR by enabling the LD input of IR
 Increment PC by enabling the INR input of PC
 The next clock transition initiates the read and increment
operations since T2=1 (See Mano Fig 5.8)

6 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 4, 2016

 T0: AR←PC
T1: IR←M[AR], PC←PC+1
T2: D7….D0←Decode IR(12-14), AR←IR(0-11), IIR(15)
T1 10
010
S2
0 1
T0 1 S1
BUS
10
S0

Memory Unit 7

1 Read Address

AR 1
1 LD
1 0 010 01 ……………0
……………0
T0 T1 ………… T15
PC 2
1 INR
Decoder

0 0 10 01
IR 3
Sequence Counter
1 LD Clock

Clock Common Bus

7
Determine the Type of Instruction
 The timing signal that is active after decoding is T3.

 During time T3, the control unit determines the type of instruction
that was just read from memory.

 See flowchart (at Mano Fig. 5.9) next slide.

8 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 4, 2016

 Instruction Types
The basic computer has three instruction code formats :
15 14 12 11 0
(a) Memory reference instruction format I opcode address

(Opcode = 000 through 110)

15 14 12 11 0
(b) Register reference instruction format 0 111 Register operation

(Opcode = 111)

15 14 12 11 0
(c) Input-output instruction format 1 111 I/O operation

(Opcode = 111)

9
 Start
SC  0 T0
AR  PC
T1
IR  M[AR], PC  PC+1
T2
Decode operation code in IR (12-14)
AR  IR(0-11), I  IR(15)

(Register or I/O) =1 =0 (Memory-reference)

D7

( I/O ) =1 =0 (register) (indirect ) =1 =0 (direct )

I I

D7 I T3 T3 D7 I T3 T3 D7 I T3 T3 D7 I T3 T3
Execute Execute AR  M[AR] Nothing
input-output Register-refernce
Instruction Instruction Execute
SC  0 SC  0 Memory-reference Instruction
SC  0

Flowchart for instruction cycle (initial configuration) 10

Register-Reference Instructions
Register ref instructions are identified when D7=1 and I=0
Execution is started with timing signal T3 and takes one clock cycle.
Register ref instruction is specified by bits (0-11) of IR which also transfer to AR during
time T2. D7 I T3 = r (common for all register-refernce instructions)
IR( I ) = Bi [bit in IR (0-11) that specifies the operation]
r: SC ← 0 Clear SC
CLA rB11: AC ← 0 Clear AC

CLE rB10: E ← 0 Clear E

CMA rB9: AC ← AC Complement AC
CME rB8: E ← E Complement E
CIR rB7: AC ← shr AC, AC(15) ← E, E← AC (0) Circulate right
HLT instruction clears a start-
stop flip-flop S and stops the CIL rB6: AC ← shl AC, AC(0) ← E, E← AC (15) Circulate left
SC from counting. To restore INC rB5: AC ← AC+1 Increment AC
the operation of the computer,
SPA rB4: If (AC (15)=0) then (PC← PC+1) Skip if positive
the start-stop flip-flop must be
set manually. SNA rB3: If (AC (15)=1) then (PC← PC+1) Skip if negative
SZA rB2: If (AC =0) then (PC← PC+1) Skip if AC zero
SZE rB1: If (E=0) then (PC← PC+1) Skip if E zero
HLT rB0: S← 0 (S is a start-stop flip-flop) Halt11computer
 Start
SC  0 T0
AR  PC
T1
IR  M[AR], PC  PC+1
T2
Decode operation code in IR (12-14)
AR  IR(0-11), I  IR(15)

(Register or I/O) =1 =0 (Memory-reference)

D7

( I/O ) =1 =0 (register) (indirect ) =1 =0 (direct )

I I

D7 I T3 T3 D7 I T3 T3 D7 I T3 T3 D7 I T3 T3
Execute Execute AR  M[AR] Nothing
input-output Register-refernce
Instruction Instruction Execute
SC  0 SC  0 Memory-reference Instruction
SC  0

Flowchart for instruction cycle (initial configuration) 12

Memory-Reference Instructions
 Memory ref instructions are identified when D7=0.
 The effective address of the instruction is in AR and was placed there during
timing signal T2 for direct instruction and during T3 for the indirect instruction.
 The execution of all Memory instructions starts from timing signal T4.

Symbol Operation Symbolic description

decoder
AND D0 AC← AC ^ M[AR]

ADD D1 AC← AC + M[AR], E ← Cout

LDA D2 AC← M[AR]
STA D3 M[AR]← AC
BUN D4 PC← AR
BSA D5 M[AR] ← PC, PC ← AR+1
ISZ D6 M[AR] ← M[AR]+1,
if M[AR]+1=0 then PC ← PC + 1
13 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 4, 2016
 Memory-Reference Instructions
AND to AC
D0T4: DR ← M[AR] read operand from memory and store it in DR
D0T5: AC← AC ^ DR, SC ← 0 And AC with DR and save the result in AC

ADD to AC
D1T4: DR ← M[AR] read operand from memory and store it in DR
D1T5: AC← AC + DR, E ← Cout, SC ← 0 add AC with DR and save the result in AC.

LDA: Load to AC
D2T4: DR ← M[AR] read operand from memory and store it in DR
D2T5: AC ← DR, SC ← 0 transferee DR to AC.

STA: Store AC
D3T4: M[AR] ← AC , SC ← 0 save content of AC in memory.

14 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 4, 2016

BUN: Branch Unconditionally This instruction transfers the program to the
instruction specified by the effective address in AR.
D4T4: PC ← AR, SC ← 0 transfer the address of the next instruction from AR
to PC.
Note: remember that PC holds the address of the next instruction.

address instruction

100 BUN 135

101 SPA

…….
……..
……..

135 CLA

15 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 4, 2016

BSA: Branch &save Address This instruction is useful for branching to a portion of
the program called subroutine. When the subroutine is
finished, the computer returns back to the next instruction
after BSA instruction..
D5T4: M[AR] ← PC, AR←AR+1
D5T5: PC ← AR, SC ← 0

16 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 4, 2016

 Example of BSA instruction execution

Memory Memory

020 0 BSA 135 020 0 BSA 135

PC=021 Next instruction 021 Next instruction

….. …..
Jump
….. …..
Return

AR=135 Save the next 135 021

instruction
136 Subroutine address Subroutine
PC=136

1 BUN 135 1 BUN 135

Indirect
(a) Memory, PC, and AR branch (b) Memory, PC, and AR
at time T4 after17
execution.
ISZ: Increment and skip if Zero This instruction increments the word specified by the
effective address, and if the incremented value is zero,
PC is incremented by 1 in order to skip the next
instruction. Since it is not possible to increment a word
inside the memory, it is necessary to read the word into
DR, increment DR, and store the word back into
memory. D5T4: M[AR] ← PC, AR←AR+1
D6T4: DR ← M[AR]
D6T5: DR ← DR+1
D6T6: M[AR] ← DR, if (DR=0) then (PC ← PC+1), SC ← 0.

18 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 4, 2016

Flowchart for memory-reference instructions
AND ADD LAD

D0 T4 D1 T4 D2 T4
DR  M[AR] DR  M[AR] DR  M[AR]

D0 T5 D1 T5 D2 T5
AC  AC ∧ DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

19
Flowchart for memory-reference instructions

STA BUN BSA ISZ

D3 T4 D4 T4 D5 T4 D6 T4
M[AR]  AC PC  AR M[AR]  PC DR  M[AR]
SC  0 SC  0 AR AR+1

D5 T5 D6 T5
PC  AR DR  DR+1
SC  0

D6 T6
M[AR]  DR
IF (DR=0)
Then
(PC←PC+1)
SC  0

20 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 4, 2016

 Start
SC  0 T0
AR  PC
T1
IR  M[AR], PC  PC+1
T2
Decode operation code in IR (12-14)
AR  IR(0-11), I  IR(15)

(Register or I/O) =1 =0 (Memory-reference)

D7

( I/O ) =1 =0 (register) (indirect ) =1 =0 (direct )

I I

D7 I T3 T3 D7 I T3 T3 D7 I T3 T3 D7 I T3 T3
Execute Execute AR  M[AR] Nothing
input-output Register-refernce
Instruction Instruction Execute
SC  0 SC  0 Memory-reference Instruction
SC  0

CAO, by Dr.for
Flowchart A.H. Abdul Hafez,
instruction CE Dept.
cycle (initial HKU
configuration) November
21 4, 2016
Input-Output Configuration

• The terminal devices send and receive serial information.

• The INPR and OUTR communicate serially with terminals and

in parallel with the AC.

• FGI and FGO are two single bit flip-flops needed to

synchronize the timing rate difference between the terminals
and the computer.

22
 Input operation

Initially, FGI is cleared to 0. When a key is struck in the keyboard, an 8-bit code
is shifted into INPR and the input flag FGI IS SET TO 1. As long as the flag
FGI=1, the content of INPR cannot be changed with a new code. The computer
checks the FGI flag, if it is 1, the information in INPR is transferred into AC in
parallel and the FGI is cleared to 0. Once the flag is cleared, new information
code can be shifted into INPR by striking another key.
FGO

Receiver
Printer OUTR
interface

AC

Transmitter
Keyboard interface INPR
00110110
01110111
FGI 01

23
 Output operation

Initially, FGO is set to 1. The computer checks the flag bit, if it is 1, the
information from AC is transferred in parallel into OUTR and FGO is cleared to 0.
The output device accepts the coded information, prints the corresponding
character, and when the operation is completed, it sets FGO to 1. As long as the
flag FGO is cleared, the computer does not load a new character code into OUTR.

FGO 10

Receiver
Printer OUTR
interface

AC
00110110

Transmitter
Keyboard interface INPR

FGI 0

November 4, 2016 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU 24

Input-Output Instructions
• Input-output instructions are needed for transferring information to and from
AC register, for checking the input and output flags and for controlling the
interrupt facility.
• Input-output instructions have op-code 1111 and are recognized when D7=1
and I=1.
• The execution of all input-output instructions is done during timing signal T3.
D7 I T3 =p (common for all input-output instructions)
IR( I ) = Bi [bit in IR (6-11) that specifies the instructions]

p: SC ← 0 Clear SC

INP pB11: AC(0-7) ←INPR, FGI ← 0 Input character

OUT pB10: OUTR ←AC (0-7), FGO ← 0 Output character

SKI pB9: if (FGI=1) then (PC ←PC + 1) Skip on input flag

SKO pB8: if (FGO=1) then (PC ←PC + 1) Skip on output flag

ION pB7: IEN ← 1 Interrupt enable ON

IOF pB6: IEN ←0 Interrupt enable OFF

25
The end of the Lecture
 Thanks for your time
 Questions are welcome

26 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU November 4, 2016