724 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 16, NO.

4, OCTOBER 2001

Benchmark Systems for Digital Computer

Simulation of a Static Transfer Switch
IEEE PES TF on Simulation of FACTS and Custom Power Controllers
of
IEEE PES WG on Modeling and Analysis of System Transients Using Digital Systems

Abstract—This paper presents two benchmark systems for

time-domain simulation of a thyristor based Static Transfer
Switch (STS). The objectives are 1) to provide guidelines for
digital simulation of STS systems, 2) to provide a basis for perfor-
mance evaluation of simulation programs used for STS analysis
and 3) to benchmark performance of various detection/control
strategies adopted for STS systems. Each benchmark system is
composed of 1) supply system, 2) STS, and 3) sensitive load. The
two benchmark systems are referred to as STS-1 and STS-2.
Simulated performances of the two systems, based on the use
of PSCAD/EMTDC software package are provided. Simulation
results corresponding to STS-2 are also compared with the
corresponding measurement results.
Index Terms—Custom power, digital simulation, FACTS, static
transfer switch.

I. INTRODUCTION

T HE STS has been widely used in low-voltages applica-

tions. Availability of reliable semiconductor switches
and stringent voltage quality requirements of sensitive loads
Fig. 1. STS system structure.

II. PRINCIPLES OF OPERATION OF STS

have led to medium-voltage applications of STSs during the
last few years [1]–[5]. Design and performance evaluation of
a STS system require detailed analysis of the supply system,
STS and sensitive load. Such studies are best carried out by
means of digital time-domain simulation tools. This paper is to
provide: 1) general guidelines for simulation of STS systems,
2) a benchmark for performance evaluation of various digital
time-domain software programs for simulation of STS systems,
and 3) a benchmark for evaluation of various detection/control
approaches and strategies for STS systems.
Section II briefly describes principles of operation of a STS
[6], [7]. Sections III and IV introduce two benchmark systems
STS-1 and STS-2. STS-1 is a medium-voltage system in which
the sensitive load is composed of a passive and a motor load.
STS-2 is a low voltage system with a passive sensitive load.
The PSCAD/EMTDC is used to simulate performance of both
systems. The simulation results corresponding to STS-2 are also
compared with experimental results. A discussion of the studies
is reported in Section V.
Manuscript received December 27, 1999.
Task force members: M. R. Iravani (Co-Chair), K. Sen (Co-Chair), A. Gole,
G. Irwin, B. Johnson, A. Keri, P. Lehn, J. Mahseredjin, J. A. Martinez, H.
Mokhtari, M. Sedighy, and D. A. Woodford
Contributors: H. Mokhtari, M. R. Iravani, S. B. Dewan, P. Lehn, and J. A.
Martinez
Publisher Item Identifier S 0885-8977(01)08505-3.
0885–8977/01$10.00 © 2001 IEEE
The basic structure of a STS system is shown in Fig. 1. The
system is composed of:
• a load which is sensitive to variations of utility supply,
• two independent sources one of which is the preferred one
and the other is the alternate one,
• two thyristor blocks and which connect the load to
the power sources, and
• a control logic to monitor voltage quality of both sources,
detect voltage fluctuations in the system (detection
process), compare the two sources, and perform a load
transfer from one source to the other one if needed
(transfer process).
STS blocks and each contain three thyristor modules cor-
responding to the three phases of the system. Each thyristor
module includes two anti-parallel thyristor switches (
and ).
Under normal operating conditions, i.e., when the preferred
source meets load voltage requirements, the control logic trig-
gers only the thyristors of . If the preferred source cannot meet
voltage requirements, the control logic will transfer the load to
the alternate source if it is in a better condition than the preferred
one. This is achieved by removing gating signals from thyris-
tors and triggering thyristors. In case of voltage recovery, the
load is transferred back to the preferred source. Input signals in
Fig. 1 are those required for controlling the STS operation.
TASKFORCE ON SIMULATION OF FACTS AND CUSTOM POWER CONTROLLERS: BENCHMARK SYSTEMS FOR DIGITAL COMPUTER SIMULATION
Fig. 2. Power circuit of STS-1 benchmark system.
Fig. 3. Block diagram of the voltage detection scheme.
To offer ride-through capability, the load must be transferred
within the shortest possible time. Therefore, the STS must meet
the following requirements:
• It must detect voltage fluctuations in the system as fast as
possible.
• In case the preferred source fails, it must perform a fast
load transfer to the alternate source.
• The gating strategy, which controls the transfer process,
must prevent paralleling the two sources.
• Detection and transfer logic must function properly for all
possible operating conditions.
• Detection scheme must not be sensitive to temporary
voltage transients, e.g., capacitor switchings.
III. STS-1 BENCHMARK SYSTEM
Fig. 2 shows a schematic diagram of STS-1 benchmark
system which is composed of a power circuit and a control
logic.
A. Power Circuit
Power circuit of STS-1 benchmark system is composed of
two 12 kV distribution feeders as preferred (p) and alternate (a)
sources. The sources are represented by ideal voltage sources in
series with lumped resistances and inductances. The combina-
tion of the load and load transformer is connected to the sources
through thyristor blocks and .
B. Control Logic
Control logic of STS-1 is composed of a voltage detection
and a gating strategy section.
1) Voltage Detection: Fig. 3 depicts a block diagram of the
voltage detection scheme. The logic is based on transforming ac
725
voltages into a synchronously rotating frame ( -to- ) based
on (1):
(1)
where:
and:
where
, , and preferred-source line voltages;
, , and components of the preferred-
source voltages in the rotating frame;
angular frequency of the rotating frame;
initial value of .
The peak value of and is calculated as:
(2)
The output of the transformation block, i.e., , is compared to
a dc reference, i.e., . The error is passed through a first-
order low-pass filter which attenuates impact of voltage tran-
sients. The filter introduces a delay to the error signal which is
determined by the filter cut-off frequency ( ). The filter output
is then compared to a voltage-change tolerance limit ( ).
Output of the comparator is a transfer signal which initiates a
transfer process if the preferred source fails.
2) Gating Strategy: The gating strategy is composed of
three identical sets of logic for the three phases of the system.
It provides selective gating patterns to thyristor switches which
results in a fast load transfer process and prevents source paral-
leling. The selective gating strategy is based on the direction of
line current flow. Fig. 4 shows the gating logic structure which
is composed of the following blocks:
1) Current direction and zero-crossing detection logic
is responsible for detecting the status of the thyristor
switches, i.e., on/off state, and selecting the right switch
to trigger to prevent source paralleling during the transfer
process. To avoid multiple zero-crossing detection, line
currents are passed through a smoothing first-order
low-pass filter. Output of the filter is an input to a hys-
teresis comparator which detects the direction of current
flow. The hysteresis comparator is used to make sure that
current direction can be detected and the transfer process
can begin for all possible loading conditions. The hys-
teresis comparator compares its input to a zero-current
threshold limit ( ) and preserves its output status as
long as the line current is within .
726 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 16, NO. 4, OCTOBER 2001

Fig. 5. Load transformer magnetizing curve.

Fig. 4. Gating logic structure.

2) Gating-pattern generation logic generates selective

gating signals for both and thyristor switches
according to the direction of current flow. For example,
if (outgoing switch) is conducting at the time a
disturbance is detected, the transfer process begins with
triggering (incoming switch). The other thyristor,
i.e., , will be gated when both and are
turned off. During the transfer operation, two scenarios
may occur in each phase. The first scenario is when
commutation begins as soon as the incoming thyristor,
e.g., , is gated. In this case, is triggered when the
preferred-source current drops below, and the alternate-
source current exceeds, the zero-current threshold limit
. The second scenario occurs when commutation
fails between the incoming and outgoing thyristors. In
this case, the outgoing thyristors continue conducting
until a zero crossing is reached and commutation begins.
A turn-off time is also considered before gating to
make sure that the outgoing thyristors have regained their
blocking capability.
3) Line voltage to phase voltage conversion and
zero-voltage back-up transfer logic transfers the
load at the zero crossing of the phase voltage if the
change of current direction and current zero-crossing Fig. 6. RL Load, 35% three-phase under voltage disturbance.
cannot be detected. This may occur for low values of line
currents, e.g., no load conditions, when the line current is • Each pair of thyristor valves has a snubber circuit com-
within . The zero-voltage back-up transfer circuit posed of M and F (Impact of
optimizes transfer time if the transfer process based on snubber circuit on the STS system is insignificant).
current direction does not succeed. • Load system is composed of a three-phase RL load in par-
allel with an induction motor. The series RL load has the
C. Parameters of STS-1 Benchmark System
following parameters:
With respect to Fig. 2, parameters of STS-1 benchmark ,
system are as follows: The motor load is rated at:
• Preferred and alternate source systems: 480 V, 500 kVA, 60 Hz, 3528 rpm
12 kV, 60 Hz Other parameters of the motor are:
, Inertia Constant H 1 s
• Three-phase load transformer stator resistance 0.33 p.u.
12 kV/480 V, 1 MVA, 60 Hz first cage resistance 0.2 p.u.
Leakage Reactance = 12% second cage resistance 0.018 p.u.
Resistance representing winding losses = 1.5%, stator unsaturated leakage reactance 0.098 p.u.
Resistance representing core losses = 0.5% mutual unsaturated reactance 3.1 p.u.
Transformer magnetizing curve is shown in Fig. 5. rotor unsaturated mutual reactance 0.1 p.u.
TASKFORCE ON SIMULATION OF FACTS AND CUSTOM POWER CONTROLLERS: BENCHMARK SYSTEMS FOR DIGITAL COMPUTER SIMULATION 727

Fig. 7. RL load, single-phase-to-ground fault. Fig. 8. RL + motor load, 35% three-phase under voltage disturbance.

second cage unsaturated reactance 0.105 p.u.
mechanical damping 0.008 p.u.
• Control circuit parameters:
kV
voltage-change tolerance limit % ms [Fig. 6(b)] which results in a detection time of
filter cut-off frequency Hz
line current smoothing filter cut-off frequency 1 kHz
zero-current threshold limit A At , phase-a current direction is positive and, therefore,
thyristor turn-off time 1 ms
sampling rate 6660 Hz.
D. Case Studies
Figs. 6–11 show simulated performance of STS-1 benchmark
system. The simulations are performed by PSCAD/EMTDC
package. Under voltage disturbances are created by reducing
the amplitude of the preferred source voltage. Faults are created
at the preferred source terminals. Fault resistance of 0.01
is considered. Definitions of detection, transfer and total
load-transfer times are as follows:
detection time: The difference between the time at which
a disturbance occurs and the time it is detected.
transfer time: The difference between the time at which a
disturbance is detected and the time at which the last faulty
phase is transferred.
total load-transfer time: The sum of detection time and
transfer time.
Case 1: RL Load, Three-Phase Under Voltage: Fig. 6 shows
a case in which a 35% three-phase under voltage occurs in
the system at ms when phase-a voltage angle is
( ). The disturbance is detected at
1.39 ms. Commutation in phase-b and phase-c is completed
with no delay [Fig. 6(d) and (e)] but fails in phase-a [Fig. 6(c)].
is
gated. However, the voltage drop across the incoming thyristor
is negative and it cannot be turned on. The disturbance
instant is such that the detection occurs at the zero crossing
of phase-a voltage ( ) which results in maximum transfer
time. The control logic allows phase-a current to cross zero
by re-gating . After 1 ms, i.e., at 8.49 ms, is forward
biased and gated to successfully transfer phase-a to the alternate
source. The maximum transfer time, which occurs in phase-a, is
3.05 ms. The total load-transfer time is 4.44 ms. Load voltages
are shown in Fig. 6(a).
Case 2: RL Load, Single-Phase-To-Ground Fault: Case 2
presents the simulation results when phase-a of the preferred
source is subjected to a single-phase-to-ground fault. The wave-
forms are shown in Fig. 7. The fault occurs at ms
( ) and is detected after 4.38 ms, i.e., at ms
[Fig. 7(c)]. At this time, phase-a line current is negative, and
the incoming thyristor is positively biased. Therefore, the
transfer process in this faulty phase is completed with almost
no delay [Fig. 7(d)]. The transfer time is only the commutation
728
Fig. 9. RL + motor load, 80% three-phase under voltage disturbance.
time which is negligible, and the total load-transfer time is equal
to the detection time, i.e., 4.38 ms.
Case 3: RL Motor Load, 35% Three-Phase Under
Voltage: In this case, the preferred source is subjected to a
35% three-phase under voltage disturbance when the load is
a combination of an RL load and a motor load. The system
behavior is shown in Fig. 8. This disturbance scenario is
similar to Case 1 where only an RL load was employed. The
disturbance occurs at ms ( ) and is detected at
ms (detection time of 1.39 ms). Phase-b and phase-c
are transferred to the alternate source as soon as the fault is
detected. Phase-a has to wait for the current zero-crossing
which is reached at ms (including thyristor turn-off
time). The transfer time and the total load-transfer time are
3.25 ms and 4.64 ms, respectively.
Case 4: RL Motor Load, 80% Three-Phase Under
Voltage: Fig. 9 shows the system behavior for a condition
where the load becomes regenerative. The system is subjected
to a disturbance which results in a three-phase 80% under
voltage. The load is the same as that of Case 3. The distur-
bance occurs at ms ( ) and is detected at
ms corresponding to a detection time of 0.46 ms.
Commutation in phase-a and phase-c begins as soon as the
fault is detected, and these two phases are transferred to the
alternate source with no delays. However, in phase-b, due to
the opposite signs of line current direction and phase voltage
polarity, the incoming thyristor is negatively biased and
IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 16, NO. 4, OCTOBER 2001
Fig. 10. RL + motor load, phase-to-phase fault.
cannot conduct. Commutation in phase-b fails, and the load
becomes regenerative feeding the preferred source through .
Commutation cannot begin until the incoming thyristor is
positively biased. This occurs at the zero crossing of phase-b
voltage. The transfer is completed at 11.41 ms. Therefore, the
maximum transfer time (8.23 ms) occurs in phase-b. The total
load-transfer time is 8.69 ms.
Case 5: RL Motor Load, Phase-To-Phase Fault: Fig. 10
shows the STS performance for the same regenerative load
when a phase-to-phase fault occurs at ms between
phase-a and phase-b of the preferred source. It is detected
at ms. The detection time is 2.85 ms. Commu-
tation in both faulty phases fails. The transfer is completed
at ms when both incoming thyristors ( for
phase-a and for phase-b) are positively biased. The transfer
time and total load-transfer time are 5.83 ms and 8.68 ms,
respectively.
Case 6: RL+Motor Load, Cross Current Phenomenon: The
cross current phenomenon may occur when current direction
is not correctly detected. This is due to the inaccuracy of cur-
rent measurement devices when line currents are within .
Fig. 11 shows the impact of the cross current phenomenon on
the STS performance. The zero-current threshold limit is
set to 1% of the load nominal current, i.e. 4.8 A. Therefore, if
the line current is within 4.8 A, the detected current directions
may not be correct. Fig. 11(a) shows a phase-to-phase fault be-
tween phase-a and phase-b at ms. As Fig. 11(c) shows,
TASKFORCE ON SIMULATION OF FACTS AND CUSTOM POWER CONTROLLERS: BENCHMARK SYSTEMS FOR DIGITAL COMPUTER SIMULATION 729

Fig. 11. RL + motor load, cross current phenomenon. Fig. 13. 35% three-phase under voltage disturbance (STS-2).

Therefore, resistor is inserted in the preferred feeder path to

practically decouple the two feeders. Variac compensates for
voltage drop across . The fault circuit is composed of a fault
resistance which is used for creating under voltage distur-
bances. Switch is also used to bypass for creating faults
to ground. Thyristor switch is employed to create timed fault.

A. Parameters of STS-2 Benchmark System

Parameters for STS-2 benchmark system are as follows:
Fig. 12. Single-line diagram of STS-2 benchmark system. • Main source: 120 V, 60 Hz, ,
• Decoupling resistance
in phase-a, the wrong incoming thyristor is gated at the time the
• Thyristor switches , , and : 50 A, 500 V snubber
fault is detected resulting in a cross current.
resistance , snubber capacitance F
• Load Transformer:
IV. STS-2 BENCHMARK SYSTEM , 4 kVA, 220 V/120 V, ,
Fig. 12 shows a single-line diagram of the three-phase STS-2 HV and LV sides are connected to the system and load,
benchmark system. An experimental set-up corresponding to respectively.
the system of Fig. 12 is developed and the simulation and ex- • Load: ,
perimental results corresponding to the STS behavior are pro- • Fault resistance
vided. A digital control system including voltage detection and • Variac: represented by an ideal lossless transformer
transfer logic, is adopted for STS-2 benchmark system. The con- • Control circuit parameters:
trol system is realized based on a UHP40 platform [8] which sampling frequency 6660 Hz
utilizes a floating-point TMS320C40 digital signal processor. V
The control system is analogous to the one used for the STS-1 voltage-change tolerance limit %
benchmark system. filter cut-off frequency Hz
Due to limitations in the laboratory, the preferred and al- line current smoothing filter cut-off frequency 1 kHz
ternate feeders are output feeders of a single transformer. The zero-current threshold limit A
preferred and alternate feeders are not completely independent. thyristor turn-off time 1 ms
730
Fig. 14. Single-phase-to-ground fault (STS-2).
B. Case Studies
Figs. 13–15 show performance of STS-2 benchmark system
under different operating conditions and compare corre-
sponding simulation and experimental results.
Case 1: RL Load, Three-Phase Under Voltage: This case
studies the STS performance when the preferred source is sub-
jected to a 35% three-phase under voltage disturbance. The dis-
turbance is created by gating fault thyristor at 14.5 ms (
open). Fig. 13(a) and (c) show load voltages obtained from ex-
periment and simulation respectively. The maximum transfer
time occurs in phase-a. Phase-b and phase-c are transferred to
the alternate source immediately after fault detection. Fig. 13(b)
and (d) show line current in phase-a. From the simulation wave-
forms, the detection and transfer times are 1.4 ms and 2.9 ms, re-
spectively. The experimental waveforms show a detection time
of 1.65 ms and a transfer time of 3.3 ms. The total load-transfer
time is 4.3 for the simulation and 4.95 ms for the experiment.
Case 2: RL Load, Single-Phase-To-Ground-
Fault: Fig. 14(a)–(d) provide the simulation and experimental
waveforms in the case of a single-phase-to-ground fault in
phase-a of the preferred source at ms ( ).
Fig. 14(a) and (c) show detection times of 4.65 ms and 4.45 ms
for the experiment and simulation, respectively. Fig. 14(b)
and (d) show that the transfer time is negligible for the given
disturbance. Therefore, the total load-transfer time is almost
equal to the detection time.
IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 16, NO. 4, OCTOBER 2001
Fig. 15. Phase-to-phase fault (STS-2).
TABLE I
STUDY RESULTS SUMMARY—STS-1 BENCHMARK SYSTEM
Case 3: RL Load, Phase-To-Phase Fault: Case 3 studies
the performance of STS-2 benchmark system when a
phase-to-phase fault, at ms ( ), occurs be-
tween phase-a and phase-b of the preferred source. The results
are shown in Fig. 15. Load voltages are shown in Fig. 15(a)
and (c). Phase-a line current is shown in Fig. 15(b) and (d).
Fig. 15(a) and (b) indicate detection and transfer times of 4.4
and 3.6 ms for the experiment. Fig. 15(c) and (d) show detection
and transfer times of 4.45 and 3.35 ms for the simulation. The
total load-transfer time is 7.8 and 8.00 ms for the simulation
and experiment, respectively.
V. DISCUSSION OF RESULTS
A. Performance of Control Strategy
Tables I and II summarize the study results for STS-1 and
STS-2 benchmark systems respectively. Characteristics, e.g.,
fault type and fault instant, as well as the detection logic. The
TASKFORCE ON SIMULATION OF FACTS AND CUSTOM POWER CONTROLLERS: BENCHMARK SYSTEMS FOR DIGITAL COMPUTER SIMULATION
TABLE II
STUDY RESULTS SUMMARY—STS-2 BENCHMARK SYSTEM
detection time is shorter for a more severe fault. The response
of the voltage detection logic is mainly determined by the filter
cut-off frequency . The higher the , the faster the detection
circuit and the shorter the detection time. However, increasing
makes the logic more sensitive to voltage transients, e.g.,
capacitor switchings. Therefore, a trade-off needs to be made
between the speed of the detection logic and its sensitivity to
voltage transients.
The transfer time is determined by gating strategy, load type,
fault type, fault instant and system configuration. Each phase
has its own transfer time, and the maximum transfer time occurs
in the phase for which the commutation process fails. Commu-
tation fails when the voltage drop across the incoming thyristor
is negative. The worst case scenarios occur for a regenerative
load when the load feeds the fault through thyristors, and the
transfer cannot be completed until the polarity of voltage drop
across the incoming thyristor changes.
Since the selective gating strategy is based on detecting line
current direction, the structure of the direction detection logic
plays an important role in the performance of STS. The more
accurate the current direction detection circuit, the better the
performance of STS. Erroneous current direction detection may
result in a cross current between the two sources.
B. Comparison of Simulation and Experimental Results
Table II shows that the simulation and experimental results
are in close agreement for STS-2 benchmark system. The slight
differences are due to the following reasons:
• In the experimental set-up, the sources are not ideal and
decoupled by a decoupling resistor. Therefore, the sources
731
are not completely independent, and in some cases due to
line impedances, they become slightly out of phase. This
affects the commutation process which in turn impacts the
transfer time.
• Thyristors that are used for the STS and the fault circuit in
the experimental set-up and the load transformer are not
ideal components.
• The voltage and current sensors in the experimental set-up
are not ideal.
• In the simulation studies, the system voltages are assumed
to be clean 60 Hz sinusoidal signals. However, as the ex-
perimental waveforms show, the real voltage waveforms
have noticeable harmonic contents.
VI. CONCLUSION
This paper introduces two benchmark systems for time-
domain simulation of the Static Transfer Switch (STS). The
first system, STS-1, is a medium-voltage system in which
the sensitive load is composed of a passive component and a
motor load. The second system, STS-2, is a low voltage system
with a passive sensitive load. The PSCAD/EMTDC is used to
simulate performance of both systems. Experimental results
corresponding to STS-2 are also verified.
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