Scaling CMOS:
materials & devices
The scaling of silicon integrated circuits to smaller
physical dimensions became a primary activity of
advanced device development almost as soon as the
basic technology was established. The importance
and persistence of this activity is rooted in the
confluence of two of the strongest drives governing
the business; the push for greater device
performance, measured in terms of switching speed,
and the desire for greater manufacturing profitability,
dependent upon reduced cost per good device built.
International SEMATECH,
2706 Montopolis Drive,
Austin, TX 78741, USA
E-mail: George.Brown@sematech.org
20 January 2004
by G. A. Brown, P. M. Zeitzoff, G. Bersuker, and H. R. Huff
Perhaps the earliest figure of merit for metal-oxide-
semiconductor (MOS) device switching speed held
that this parameter increased as the inverse square of
the MOS transistor physical channel length,
encouraging the shrinking of this dimension. The
basic idea is that the output or drive current of a
device available to switch its load devices increases
linearly as its physical channel length decreases,
while the current required by the load devices to
achieve switching decreases as their gate area and,
hence, their physical channel length decreases. Thus,
there is a twofold benefit in device dimension
reduction. Since the drive current requirement to
switch the load devices depends, to some extent,
upon the total load capacitance and area, there is a
strong motivation to reduce the size of the complete
device, not only its physical channel length.
The economic case may be stated even more simply. As a
general rule, semiconductor devices are manufactured by the
batch, or by single-wafer processes, while they are sold by
the individual device. Hence, the more devices one can pack
onto each wafer, the higher the potential economic return.
This is more conventionally described in terms of functional
cost, expressed as dollars per transistor, shown in Fig. 1.
Maintaining a continuously falling functional cost with time
is seen as a key factor in driving an ongoing demand for
electronics and semiconductor products. To meet this
demand in the face of achievable increases in revenue and
capital investment, the industry is forced to maintain an
ISSN:1369 7021 © Elsevier Ltd 2004

essentially flat manufacturing cost per square centimeter of
Si wafer area while expanding the total number of transistors
built, or the number of transistors per chip, also known as
Moore’s Law1. Over the last half-century of MOS device
development, we have seen Si wafer diameters increase from
about 20 mm to 300 mm, providing more than a factor of
200 increase in available device area per wafer and a
shrinkage of the critical dimensions of devices from
10-20 µm to the 0.1 µm range, and even below.
Fairly early on, it was recognized that this scaling down of
device dimensions could not be done randomly. The
pioneering work of Dennard and colleagues2 at IBM pointed
the way to a unified theory of constant electric field scaling,
indicating the interrelationship of device parameters for
optimum results, but the emphasis at this stage was
primarily upon device dimensions and not materials or
material properties. It did, however, show that the physical
thickness of films, as well as lateral dimensions, must be
scaled together. Later on, the National and then
International Technology Roadmap for Semiconductors
(ITRS)3 provided a considerably more detailed guide to
device scaling requirements to keep the industry on the
Moore’s Law curve that has guided the integrated circuit (IC)
industry’s growth1.
The point is that, until quite recently, the burden of
producing ever-faster switching devices in higher quantities
has fallen most heavily upon photolithographic technology,
which has been driven to develop new techniques in order to
pattern these smaller structures. In the last decade, it has
Fig. 1 Functional form of key semiconductor industry business trends (Tx = transistor).
REVIEW FEATURE
been realized that, after this long period of geometric scaling,
we have arrived at a point where the concomitant scaling of
the thickness of the silicon dioxide (SiO2) gate dielectric has
left it only a few atomic layers thick, beyond which the
material no longer possesses its inherent physical
characteristics. This has brought about the search, described
in the companion article by Bersuker et al.4, for new gate
dielectric materials with higher dielectric constants (k) to
provide larger values of channel charge for transistor drive
current at greater physical thickness values.
Other required materials changes in the basic Si IC
technology are following close behind the replacement of the
gate dielectric. Polysilicon gate electrodes, used as
replacements for the metal gates of the earliest devices, are
now being found to be no longer adequate compared to
metals, and transistor physical channel length, the original
target of scaling, is reaching a point where doping levels can
no longer be increased sufficiently to support the electrical
potential profile required for advanced device operation. This
is encouraging an investigation of novel device structures
with the potential of providing the desired improvement in
operating characteristics within the framework of physical
realizability5. An overview of this activity is provided at the
end of this article. We shall initially address the gate
electrode situation.
Gate electrodes
While scaling is driving us to abandon SiO2 and the oxide-
silicon interface, which have been the cornerstones of the
industry for a half-century and described as unique in the
physical world, a proposed move to metal gate electrodes
represents a return to the technology used at the very
beginning of MOS device development. The first MOS devices
truly had metal gate electrodes; Au, Cr, or Al. Because of its
ease of deposition and etching, its adherence to SiO2 and Si
surfaces, and its freedom from corrosion, Al became the
standard metal gate electrode for early MOS devices. Some
shortcomings like electromigration and spiking into shallow
junctions were overcome by alloying with Cu or Si. The death
knell rang for Al, however, with the need for vertical
integration of circuits; that is, the addition of multiple levels
of metal interconnections. Al cannot withstand the higher
temperatures needed for deposition and annealing of the
interlevel dielectric films because of its low melting and
alloying temperatures.
January 2004 21
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Logically, the first considerations for replacement gate
electrodes were higher-temperature metal systems, so-called
refractory metals. Materials including Mo, W, and Pt, mostly
deposited by physical vapor deposition (PVD), were evaluated
and found wanting in the areas of deposition damage to the
underlying gate oxide, process compatibility, or etching
difficulties. The adoption of polysilicon for this application
was perhaps the first major change in MOS process
technology, implemented in the early 1970s in many IC
houses. The great good fortune of this choice became clear
with the advent of complementary-MOS (CMOS) technology,
where the ability to tailor the work function of the gate
electrode for negative- and positive-channel MOS (NMOS
and PMOS, respectively) devices by doping the polysilicon
with P or B, respectively, became apparent (as well as the
ability of the doped polysilicon to getter metallics in the SiO2
film). Up until this time, the work function of the gate
electrode had not commanded significant attention, because
the threshold voltage, Vt, depended on many other
parameters of at least equal importance; substrate doping,
gate oxide charge, and thickness. In addition, operating
voltages were high, and the role of the gate electrode in
setting Vt was not seen as critically important.
As scaling drove the operating voltages lower, however,
the need for controlled, low, and equal (but opposite polarity)
threshold voltages for NMOS and PMOS transistors in circuits
became clear. To balance and minimize these threshold
voltages, it was recognized that having the ability to tailor
the work functions of the polysilicon gate electrodes by
changing their doping from heavy n-type to heavy p-type
was perhaps the greatest advantage in the use of polysilicon
for this application. Transistors work by introducing mobile
carriers into the minority carrier band of the device substrate;
the conduction band in p-type Si for NMOS, and the valence
band in n-type Si for PMOS. Since thermal equilibrium
requires a uniform Fermi level throughout the MOS system,
applying a relatively low work function gate electrode will
cause a downward bending of the energy bands in the p-type
Si substrate of the NMOS device so that the minority carrier
conduction band can readily accept conduction electrons with
a minimum of additional applied gate voltage. A similar
situation applies to the use of a relatively high work function
gate electrode on the n-type substrate of PMOS devices,
permitting the valence band to accept additional holes easily
to form the p-type channel. These conditions can be obtained
22 January 2004
by doping the polysilicon gates of NMOS devices n-type and
those of PMOS devices p-type, as noted earlier. As further
scaling has reduced the thickness of the gate oxide, the
dependence upon the gate electrode work function to set
the device Vt has increased, as the effect on the device Vt of
other parameters, such as oxide/interface charge density and
oxide thickness, decreases linearly with the oxide thickness.
It has been this continuing decrease in gate dielectric
thickness that has revealed shortcomings in the use of
polysilicon for gate electrodes. As noted above, setting
device Vt by doping the polysilicon results in the polysilicon
gate electrode being of opposite conductivity type to the Si
substrate. Thus, when the device is biased into substrate
inversion for operation, there is a tendency for the gate
electrode to deplete and invert as well. Any depletion of the
polysilicon surface adjacent to the gate oxide appears as an
additional dielectric region, increasing the equivalent oxide
thickness (EOT) of the gate dielectric. Typically, this effect
will add 0.4-0.6 nm to the EOT of the gate dielectric, an
amount that was negligible when gate oxides were 10 nm
thick, tolerable at 5 nm, but unacceptable as we push toward
1.0 nm EOT gate dielectrics. In addition, the B dopant used
to create the heavily doped p-type polysilicon gates for the
PMOS devices diffuses more easily through the gate
dielectrics than does the n-type dopant used for NMOS.
The drive to add more B to the gate to minimize depletion,
together with the thinning of the gate dielectric, results in
increased B diffusion through the gate dielectric into the
channel of the PMOS device, altering its Vt in an
uncontrollable and undesirable way. Thus, polysilicon
depletion and B penetration have been the two primary
reasons to return to metal gate electrodes for future
technology generations.
Over the years, the use of polysilicon gate electrodes has
become nearly as deeply rooted in Si device technology as
has the SiO2-Si interface. The necessity of finding new gate
electrode materials and processes at the same time as
implementing new high-k gate dielectrics has caused great
concern in the industry, which has tried to maintain a
baseline of familiar, controllable processes in the face of
continued scaling challenges. Therefore, the first impulse in
searching for a metal gate replacement for polysilicon was to
try to find a single metal that would work for both NMOS
and PMOS devices in a circuit by selecting one with a Fermi
level aligned near the midgap position between the valence

and conduction bands in the Si substrate. This would
maintain the nearly equal but opposite polarity NMOS and
PMOS Vt values required for circuit operation, although these
would be higher than those for dual-doped polysilicon gates
because of the need to overcome the approximate 0.5 V of
band bending (half the band gap; the energy difference
between the midgap and band edges) required to charge the
minority carrier bands. It was thought that this might be
ameliorated to some extent by channel doping of the devices.
But, in view of device performance and scaling requirements,
it was soon recognized that this was not a viable alternative
and a dual-metal gate strategy would be needed for bulk
CMOS devices.
This led to a re-examination of the periodic table, so
recently visited to find thermally stable replacement
dielectrics for SiO2, to search for metallic materials with
suitable work functions that might be compatible with Si
process technology. Some relatively unfamiliar candidates
such as Nb, Ir, Os, Ru and its oxide have been uncovered,
along with more commonly used materials like Ta, TaN, and
TiN, and those considered 30 years ago when polysilicon was
adopted, Mo, W, and Pt. The real challenge is that a suitable
work function is a necessary first requirement for a dual-
metal technology, but it is only one of many equally
important requirements such as thermal stability and
compatibility with the many other materials and processing
ambients and temperatures used in Si technology.
The straightforward, brute force approach to a dual-metal
gate technology would entail sequential deposition and
selective etching of both metals after the gate dielectric is
deposited. Since NMOS and PMOS devices within a chip are
intermixed randomly, and metal deposition processes coat
the entire surface of the wafer uniformly, one cannot easily
deposit the desired metal upon the appropriate devices alone.
In a sequential dual-metal process, the etching of the first
metal from those devices requiring the second metal would
expose their gate dielectrics to the etchant and potential
damage, particularly during the over-etching required to
assure complete removal of the first metal layer. Given the
extreme thinness of the gate dielectric and its requirement of
high reliability, such exposures are deemed unacceptable.
To avoid exposure of the gate dielectric while still
depositing electrodes of differing work function, several
approaches have been proposed to modify or ‘tune’ the work
function of metal gate systems. In general, these approaches
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depend upon the specific properties of the materials chosen.
For example, one approach6 begins with the application of a
metal layer with a work function appropriate for one of the
devices, the NMOS for instance, followed immediately by
deposition of a second metal chosen to form an alloy or
mixture with a work function, after a thermal treatment,
appropriate for the PMOS device. Prior to the thermal
treatment, the second metal film is etched off the NMOS
devices, leaving the first metal film in place. The subsequent
heat treatment leaves the gate work function unchanged. The
specific materials proposed in this approach are Ti for the
first metal layer and Ni for the second film. In this case, it
was found that interdiffusion of the Ni and Ti resulted in
segregation of the former at the gate electrode/dielectric
interface, where it sets the work function of the system. This
process also requires an extra photolithographic level.
Another approach7 depends upon the fact that compounds of
some metals, for example their nitrides, can have metallic
properties with work functions different from that of the
parent material. With this process, after deposition of the
parent metal layer, appropriate devices are masked
photolithographically so that those remaining exposed can be
implanted with N2. The nitride is then formed by annealing.
There have been attempts in the case of high-k dielectric
development to maintain some of the beneficial properties of
the SiO2-Si system by employing silicates of Hf and Zr, which
may be thought of as metal-doped SiO2. A similar philosophy
may be applied to the case of dual-work function gate
electrodes by using fully silicided metal gates (FUSI)8. Here,
silicidation of a polysilicon film down to the gate
electrode/dielectric interface minimizes the polysilicon
depletion effect, while retaining the beneficial process
integration properties of the material. More recently, it has
been shown that the tunability of the work functions of these
systems may be enhanced by As or B doping of the silicides9.
For more advanced devices, such as dual-gate or ‘fin’ field-
effect transistors (FinFETs)10, it is found that only limited
tuning of the work function near the midgap value is
required. Both pure metal systems11, such as W, and FUSI
structures12 have been proposed for this application.
Complications have been found in the development of
metal gate systems for high-k dielectrics involving the
interaction of the electrode with the surface of the high-k
film. Early high-k work was directed at finding a film that
would be a direct replacement of SiO2 within the framework
January 2004 23
 REVIEW FEATURE
of a polysilicon gate system. ZrO2, an early leading candidate,
was discarded largely because of its interaction with
polysilicon13. Unexpected Vt control issues, particularly in
PMOS devices using the P+ polysilicon-HfO2 system, have
been related to a polysilicon-HfO2 interaction resulting in the
pinning of the Fermi level at the interface at a value different
from that predicted by the doping of the polysilicon gate14.
Such Fermi level pinning effects have also been predicted and
described for metal gates in conjunction with high-k
dielectrics15. This rather general effect may result in the need
to identify metal gate candidates with work functions even
smaller for NMOS devices and larger for PMOS devices than
those required for a SiO2 gate dielectric.
Novel device structures
Beyond the 65 nm technology generation (in 2007), it is
expected that the current mainstream IC technology – planar
bulk CMOS – will become increasingly difficult to scale
effectively, even with the utilization of high-k gate dielectrics,
metal gate electrodes, elevated source-drains, strained Si, and
other potential material and process solutions being
developed5,16,17. Particular challenges are expected in
attaining acceptable control of short channel effects while
achieving adequate drive current and acceptably low leakage
current. Nonclassical CMOS structures, such as ultra-thin
body (UTB) fully-depleted silicon-on-insulator (FDSOI)
initially and later some type of multiple-gate UTB MOSFET,
are expected to be utilized beyond 2007 to deal with the
difficulties discussed above.
Fig. 2 Simplified cross-section of an ultra-thin body fully-depleted SOI (UTB FDSOI) MOSFET.
24 January 2004
A schematic cross-section of an UTB FDSOI structure is
shown in Fig. 2, and two diagrams of a FinFET, one type of
UTB multiple-gate structure, are shown in Fig. 3. Modern SOI
devices have a SiO2 layer (the buried oxide or BOX) on top of
the substrate and a film of single-crystal Si on top of the
BOX. The device is fabricated in the top Si layer. The top Si
layer of the UTB SOI device is ultra-thin, and is fully depleted
electrically when the device is turned on. Multiple-gate
devices are usually built on SOI substrates and have two or
more surfaces along which an inversion layer is formed and
current flows. The FinFET, shown in Fig. 3, has thin fins of Si
etched into the top Si layer and gate electrodes that are
deposited and patterned on the sides of each fin. The
inversion layer is formed on the vertical edge of each fin, and
the current flows from source to drain along these edges. In
some cases, a third electrode is also utilized on top of the fin,
yielding the so-called tri-gate structure18.
High-k gate dielectrics will presumably be used for UTB
FDSOI and multiple-gate devices. The deposition techniques,
processing, and other issues are built upon those for planar
bulk CMOS. The main exception is for multiple-gate devices,
where high-k dielectric deposition will need to be done
conformally, so that the dielectric forms a uniform layer
along the sides, as well as the top, of the device. Metal gate
electrodes will be used for UTB FDSOI and multiple-gate
MOSFETs. However, for UTB SOI and multiple-gate MOSFETs,
the threshold voltage, Vt, is typically set by controlling the
work function of the metal gate electrode. As mentioned
above, to set Vt to the desired value of several tenths of a

(a)
(b)
Fig. 3 The FinFET, an example of a nonclassical CMOS structure. (a) Shows a perspective view of a FinFET, where the fin is colored yellow. (b) Top view of a FinFET.
volt for NMOSFETs and similar negative values for
PMOSFETs, the gate electrode work function must be near-
midgap, e.g. several tenths of a volt above the Si midgap
position for NMOSFETs and several tenths of a volt below it
for PMOSFETs. For multiple-gate structures, furthermore, the
metal gate electrode material will need to be deposited
conformally to produce a uniform layer along the sides, as
well as the top, of the device. Finally, doping, patterning, and
etching such electrodes uniformly and completely along both
the top and edges of the fins are expected to present
significant challenges beyond those involved in patterning
and etching the gate electrode in planar bulk technologies.
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Conclusion
The scaling of Si ICs, a process as old as the technology itself,
has now moved well beyond geometrical shrinking, leading to
the need for significant new materials and device research to
replace the components and structures that have been used
in the technology from its outset. In this and the companion
article on page 26, we have discussed various aspects of
current research in high-k gate dielectrics, metal gate
electrodes, and some aspects of novel, nonclassical CMOS
device design. The ability of the industry to maintain its
growth along the Moore’s Law projection depends upon the
success of the ongoing research in these areas. MT
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January 2004 25