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Altera Quartus II Tutorial

Part II
ECE 465 (Digital Systems Design)
ECE Department, UIC, Spring 2013
Instructor: Prof. Shantanu Dutt
TA: Soroush Khaleghi

The first part of Quartus® II tutorial illustrates schematic diagram based entry for the desired
circuit. This second part of Quartus® II tutorial is aimed at introducing hierarchical schematic
based design entry method. In hierarchical based design approach, commonly used logic
elements (i.e. 1-bit full adder) are compiled and synthesized separately and later, these
smaller logic elements are integrated in a larger module (e.g., 4-bit ripple carry adder). As a
result, a higher-level design file becomes more readable. Using this approach, not only a 2-
level hierarchical design can be created, but greater than 2-level hierarchies can be created.
For example, after designing a ripple-carry adder (RCA) using a 2-level hierarchical design
process, a multiplier design can be created using an RCA and probably other smaller
components. In this case, the multiplier has a 3-level hierarchy.

In this tutorial, a 1-bit full adder (FA) will be compiled and synthesized using schematic
based design entry and then it will be used to create a 4-bit ripple carry adder.

This tutorial will also introduce two types of simulations, namely, functional simulation and
timing simulation, to assess the behavior and performance of the desired design.

Please note that this tutorial is based on Altera Quartus® II 13.0 web edition version.


1. Hierarchical Based Design

2. Functional Simulation

3. Timing Simulation
1. Hierarchical Based Design
In this section, a new Quartus® II project will be created to design a 4-bit ripple carry adder,
the top-level module. Please follow the steps shown in part I of this tutorial to create a new
project using New Project Wizard in Quartus® II.

Choose “RCA_4b” as the name for both the project and the top-level entity. It is important to
notice that the name of the top-level entity must match the entity name in the design file.

We will start by designing a 1-bit FA using schematic editor. Figure 1 illustrates a 1-bit full

Figure 1. schematic diagram for a 1-bit Full Adder

After saving this file as “FA_1b” we will run the following command for checking any
design error: Processing > Analyzing Current File.

If the design is free of errors, then we will create a symbol for this 1-bit FA block for later use
in a 4-bit ripple carry adder. This is done so by selecting File > Create/Update > Create
Symbol File for Current File.

At this point we are ready to design our top-level module, a 4-bit ripple carry adder (RCA),
by cascading 4(four) 1- bit FAs. To do so, first create a new schematic file. This file will be
our top-level design entity. Therefore, you must save it as “RCA_4b”.

Now, we need to import 1-bit FA symbol in the new schematic file. The symbol file for 1-bit
FA block is added to the libraries of the project. To access the library, double-click on the
blank space inside the Block Editor display to open the window in Figure 2 (another way to
open this window is by clicking on the AND gate symbol in the toolbar). Make sure the
“Repeat-insert mode” is checked.

Figure 3 shows the schematic diagram for a 4-bit RCA consisting of cascaded 1-bit FAs. This
top-level design file name must be the same as Quartus® II project name (in our example

There are two 4-bit inputs in our design (A and B). The four bits of input A are named as
follows: A[0], A[1], A[2], and A[3]. This is also how we assign the names for four bits of
input B. By following this assignment, we are basically defining two 4-bit buses A and B.
This assignment will help us to define our test vectors in the simulation section much more
easily. However, we do not follow this pattern (using brackets) for output signals S0, S1, S2,
and S3. In the simulation section, we will show how we can group these nodes together.
Figure 2. Importing 1-bit FA symbol in 4-bit RCA

Figure 3. Schematic diagram for 4-bit RCA

After saving the above schematic file, we will again run the following command for checking
any design error: Processing > Analyzing Current File.

Now, we must click on “Start Compilation” button to compile the design (See part I of the
tutorial for more details)

Having completed our design without any errors, we are now ready to see the functional
correctness and timing analysis of the synthesized circuit. We need to create a vector
waveform file (*.vwf) to simulate the design. Please follow the steps shown in part I of this
tutorial for creating such a file.

2. Functional Simulation
Functional simulation verifies the correctness of logic operation of the synthesized circuits. It
does not take timing issue into consideration.

After creating the vector waveform file, we want to include the input and output nodes of the
circuit to be simulated. First, open the “Node Finder” window and list all the nodes
(explained in Part I). Choose “Selected Nodes” as it is shown in Figure 4. By selecting A and
B as “Input Group”, the internal signals are selected automatically.

Click on OK for two times to return to the Waveform Editor.

Figure 4. Node Finder

Now, we need to put all the output lines (C, S3, S2, S1, and S0) into a group. Remember that
in order to make a group of nodes, we first need to arrange them in such a way that the Most
Significant Bit (in this case, C) becomes the first bit on the group and the Least Significant
Bit (in this case, S0) becomes the last one. To do so, you can simply click the mouse on any
node and then drag the mouse to the new place.

After sorting all the output nodes from the MSB to the LSB, select all of them. Then, right
click on one of them and Choose Grouping > Group. This can be seen in Figure 5. You will
be asked to provide a name for you group. We will name this group as “Sum”. You can also
specify the radix of your group. The default representation format of the group is Binary. You
can also change it to other formats like “Hexadecimal” or “Unsigned Decimal”. We will use
the default format (Binary) for now.

Figure 5. Making a group of several nodes

Next, we want to set the end time of our simulation. Go to “Edit” menu and select “Set End
Time”. Set the end time to be 80 ns. The final Simulation Waveform Editor is shown in
Figure 6.

Figure 6. Waveform Editor after forming a group of nodes (S) and setting the end time (80 ns)
Before drawing the input waveforms, we must notice that since the timing issues are not
considered for the purpose of the Functional Simulation, there is no need to calculate and
consider the critical path delay of our circuit. However, the critical path delay must be
considered in the Timing Simulation. We will discuss it in the next section.

Now, we are ready to draw the input waveforms. Input waveforms (test vectors) can be drawn
in different ways. The most straightforward way is to indicate a specific time range and
specify the value of a signal. To illustrate this approach, click the mouse on the A waveform
near the 0-ns point and then drag the mouse to the 20-ns point. The selected time interval will
be highlighted in blue, as depicted in Figure 7. You can change the value of 4-bit input A by
double-clicking on the highlighted blue part and changing the “Numeric or named value” box,
as shown in Figure 7. You can enter the desired input in any format (e.g., Binary,
Hexadecimal, Unsigned Decimal, etc.) by changing the value of the “Radix”.

Figure 7. Changing the waveform of an input bus

You must repeat this process to complete the input waveforms. A sample result is depicted in
Figure 8.

Figure 8. The completed input waveform

Now that we have created the input vector waveform, we can simulate the circuit. Select
Simulation > Run Functional Simulation, or click on the icon . A pop-up window will
show the progress of the simulation, then automatically close when it is complete. A second
Simulation Waveform Editor window then opens the output waveform, as depicted in Figure
9. The output waveform is read-only, so any changes in simulation have to be done by
modifying the first Waveform Editor window (the one we have been working on so far) and
re-simulating the circuit. Observe that the output Sum is equal to the summation of A and B.

To observe the values of the individual outputs throughout the simulation, you can click on
the small triangle symbol on the left side of Sum. This will show the values of all nodes in the
group separately. Furthermore, in order to verify the correctness of the design, we can change
the Binary format of the inputs and outputs to the Decimal format. Select A, B, and Sum, then
right-click on one of them, choose Radix > Unsigned Decimal. The result is shown in Figure

Figure 9. Result of the Functional Simulation

Figure 10. Result of the Functional Simulation in the Decimal format

3. Timing Simulation
Having verified the logical correctness of the design file, it is necessary to determine whether
the synthesized circuit meets the delay constraint. Timing simulation verifies both the logical
correctness and timing. We will also be able to observe the propagation delay along various
paths in the synthesized circuits.

Before conducting the Timing Simulation, we need to make sure that the time interval chosen
for each test vector is greater than the critical path delay of the circuit. In other words, before
changing the values of the inputs, we must make sure that all the nodes in the circuit
(especially the outputs) have steady state values.

“TimeQuest Timing Analyzer” tool will provide propagation delays along all the paths in the
circuit, including the critical path propagation delay. After compiling the circuit (see part I of
the tutorial for details), this tool can be accessed by clicking on “Tools” and choosing
“TimeQuest Timing Analyzer”. To observe the propagation delays of the circuit, you must
double-click on “Report-Datasheet” option under “Tasks” pane. This is shown in Figure 11.

Figure 11. Propagation delays of the circuit shown in the Timing Analyzer tool

Please note that the propagation delays depend on the device chosen for the simulation. This
tutorial uses MAX II family for simulation purpose.
Another way to look at the propagation delays is by looking at the “Compilation Report”,
generated after compiling the design, as shown in Figure 12.

Figure 12. Propagation delays of the circuit shown in the Compilation Report

As can be seen in Figure 12 (or Figure 11) the critical path in our design is the path from
input line A[1] to output C. This path has the highest propagation delay of 8.295 ns.

Knowing that the critical path delay of the circuit is 8.295 ns, we must select the input change
interval that is an integer that is at least a little more than this value. We will use the 20 ns
intervals used for the Functional Simulation in the previous section.

To perform a timing simulation, select Simulation > Run Timing Simulation, or click on
the icon . A pop-up window will show the progress of the simulation, then automatically
close when it is complete. A second Simulation Waveform Editor window then opens the
output waveform. The output waveform is read-only, so any changes in simulation have to be
done by modifying the Waveform Editor window (the one we have been working on so far)
and re-simulating the circuit. Figure 13 shows the output waveforms.
Figure 13. Result of the Timing Simulation

The timing simulation shows that there are delays when signals change from one value to
another. You can use the “Zoom Tool” to zoom in or zoom out in the waveform display. Left
clicking zooms into the display and right clicking zooms out.


1) Altera Quartus II tutorial part II, Sajjad Rahaman, Spring 2009

2) Introduction to Simulation of VHDL Design, ALTERA Corporation, University Program,
February. 2013