Faculty Member: _____________ Date: ___________

.
Semester: _______________ Section: __________ .

EE221 – Digital Logic Design Grp No.

Assessment Rubrics for Lab 5: Design of 2-out-of-5 to BCD Code Converter with Display
(CLO4, P4)
S. No. Student Name Reg. No. Total Marks
S1
S2
S3
S4
Method: Viva, Lab report and instructor evaluation and observation during lab session.
Outcome Assessed:
a. Ability to conduct experiments, as well as to analyze and interpret data (P).
b. Ability to function in a team (A).
c. Ability to use the techniques, skills and modern engineering tools necessary for engineering
practice (P).
Does not meet Marks
Exceeds expectation Meets expectation
Performance expectation
(10--9)/(5) (8--5)/(4-3)
(4--1)/(2--1) S1 S2 S3 S4
Selects relevant equipment
Needs guidance to select Incapable of selecting relevant
1. Realization to the experiment, develops
relevant equipment to the equipment to conduct the
Of setup diagrams of
experiment and to develop experiment, equipment
Experiment [c] equipment connections or
equipment connection or connection or wiring diagrams
10 wiring.
wiring diagrams. are unrecognizable.
Actively engages and
2. Teamwork Cooperates with other Distracts or discourages other
cooperates with other group
[b] group members in a group members from
members in an effective
5 reasonable manner. conducting the experiment.
manner.
Does proper calibration of
Calibrates equipment,
3. Conducting equipment, carefully Unable to calibrate appropriate
examines equipment and
Experiment [a] examines equipment and equipment and wiring, and
wiring of components and
5 wiring components, and equipment operation is
operates the equipment
ensures smooth operation substantially wrong.
with minor error.
and process.
4. Laboratory Respectfully and carefully Observes safety rules and
Disregards safety rules and
Safety Rules [a] observes safety rules and procedures With minor
procedures.
5 procedures. deviation.
Plans data collection to Plans data collection to Does not know how to Plan
5. Data achieve experimental achieve experimental data collection to achieve
Collection [a] objectives, and conducts an objectives, and collects experimental goals; data
10 orderly and a complete data complete data with minor collected is incomplete and
collection. error. contain errors.

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 Lab 6: Design of 2-out-of-5 to BCD Code Converter with Display

Lab 6: Part (a): Hardware implementation of 2-out-of-5 to BCD Code

Converter with Display

Lab6: Part (b): Gate-level Modeling in Verilog

This Lab Activity has been designed to familiarize the student with design and working of a 2-out-
of-5 to BCD Code Converter and numeric Display

Objectives:

 Simplification of Boolean functions using Five-Variable map

 Design of Code Converter block using Two-Level NAND gates.
 System integration with BCD-to-Seven-Segment Decoder and Numeric readout for display.
 Understanding the difference between common cathode and common anode displays

Lab Instructions

 This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva
session.
 The lab report will be uploaded on LMS three days before scheduled lab date. The
students will get hard copy of lab report, complete the Pre-lab task before coming to
the lab and deposit it with teacher/lab engineer for necessary evaluation.
 The students will start lab task and demonstrate design steps separately for step-wise
evaluation( course instructor/lab engineer will sign each step after ascertaining
functional verification)
 Remember that a neat logic diagram with pins numbered coupled with nicely patched
circuit will simplify trouble-shooting process.
 After the lab, students are expected to unwire the circuit and deposit back components
before leaving.
 The Total duration for the lab is 3 hrs. After lab duration, a deduction of 5 marks
per day will be done for late submission.
 A lab with in-complete lab tasks will not be accepted.
 The students will complete lab task and submit complete report to Lab Engineer before
leaving lab.
 There are related questions at the end of this activity. Give complete answers.

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Pre-Lab Tasks: (4 marks)

1. What do you mean by non-weighted codes? Explain with Examples.

2. 7-Segment LED Displays are commonly used for displaying decimal Numbers (0 to 9). It can
also be used for displaying alphabets. A 7-Segment LED Displays essentially consist of
7 LEDs configured as shown below to display numbers. It comes in two configurations.
Common Cathode and Common Anode. Draw the diagram showing connections to drivers
and power source and ground for both configurations and highlight differences between
the two. Also give signal logic level required to light up the LEDs in the segment in each
configuration:

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3. Complete the following table.

Inputs (2-out-of-5) Output(BCD)

A B C D E w x y z

4. Simplify the output functions w, x, y, and z using map method. Try to take maximum
advantage of don’t care conditions.

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5. Draw logic diagram of the simplified expression

6. Draw logic diagram of the simplified expression (using NAND gates only)

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Lab Tasks: (6 marks)

Lab Task 1

1. Implement the above circuit in hardware using minimum number of NAND gates at Two-
Levels and show the results to Teacher/Lab-Instructor.
2. Give complete schematics for your design including BCD-to-Seven-Segment driver IC and
read out. A Schematic is a logic diagram with pin numbering and IC Labeling on each gate.

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3. Mention which configuration of 7-Segment Display did you use in Lab? If you were to use
the other configuration what change would you need in your circuit?

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Lab Task 2:

4. Design and simulate the gate-level model of the circuit you patched. Give the code in the
space provided below.

module GR5(a,b,c,d,e,w,x,y,z);

input a,b,c,d,e;

output w,x,y,z;

wire w1,w2,w3,w4,w5,w6,w7,w8,w9,n1;

nand(w1,a,c);

nand(w2,a,d);

nand(w,w1,w2);

not(n1,a);

nand(w3,n1,b);

nand(w4,a,e);

nand(x,w3,w4);

nand(w5,n1,c);

nand(w6,a,e);

nand(y,w5,w6);

nand(w7,n1,d);

nand(w8,a,e);

nand(w9,a,c);

nand(z,w7,w8,w9);

endmodule

module testgr5();

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reg A,B,C,D,E;

wire W,X,Y,Z;

GR5 testgr5(A,B,C,D,E,W,X,Y,Z);

initial

begin

A=1'b1;B=1'b1;C=1'b0;D=1'b0;E=1'b0;

#10 A=1'b0;B=1'b0;C=1'b0;D=1'b1;E=1'b1;

#10 A=1'b0;B=1'b0;C=1'b1;D=1'b0;E=1'b1;

#10 A=1'b0;B=1'b0;C=1'b1;D=1'b1;E=1'b0;

#10 A=1'b0;B=1'b1;C=1'b0;D=1'b0;E=1'b1;

#10 A=1'b0;B=1'b1;C=1'b0;D=1'b1;E=1'b0;

#10 A=1'b0;B=1'b1;C=1'b1;D=1'b0;E=1'b0;

#10 A=1'b1;B=1'b0;C=1'b0;D=1'b0;E=1'b1;

#10 A=1'b1;B=1'b0;C=1'b0;D=1'b1;E=1'b0;

#10 A=1'b1;B=1'b0;C=1'b1;D=1'b0;E=1'b0;

end

endmodule

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Comments/Observations

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