9/22/2017 Hardware Modeling Using Verilog - - Unit 2 - Week 1

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Unit 2 - Week 1

Course
outline Week 1 Assignment
The due date for submitting this assignment has passed.
How to access Due on 2017-09-01, 23:59 IST.
the portal Submitted assignment

Week 1 1) What does Moore’s law specify? 1 point

Lecture 1: The number of transistors in a VLSI chip will increase linearly with time.
Introduction The number of transistors in a VLSI chip will increase exponentially with time.
Lecture 2 : The power consumption in a VLSI chip will increase linearly with time.
Design None of the above.
Representation
2) Which of the following does not represent a behavioral representation for the function 1 point
Lecture 3 :
Getting
f = A . B + C?
Started with
Verilog
The truth table of the function with output column (01010111)
A Verilog specification: assign f = (A & B) | C;
Lecture 4:
VLSI Design A netlist consisting of one 2-input AND and one 2-input OR gate
Styles (Part 1) None of the above
Lecture 5 : 3) Given a gate-level netlist represented by a graph, which of the following is not true for 1 point
VLSI Design
4-input LUT mapping in a typical FPGA?
Styles (Part 2)

Week 1 The 4-input LUT is typically realized using a 16x1 SRAM unit.
Lecture Any circuit subgraph with up to 4 input edges and 1 output edge can be mapped to a LUT
Material irrespective of the number of vertices included therein.
Icarus In SRAM-based LUTs, the function of the LUT can be changed by downloading
Installation appropriate bit patterns in the associated RAM locations.
Guide
None of the above
Quiz : Week 1
Assignment 4) For which design style, the following statement is true? 1 point
“The fabrication cost of a chip is C = C1 + C2, where C1 represents a cost
Feedback for
Week 1
that is shared among several customers,
while C2 represents a cost that is to be separately borne by every customer.”
Week 1
Assignment Gate array
Solution
FPGA
Week 2 Standard cell

https://onlinecourses.nptel.ac.in/noc17_cs21/unit?unit=6&assessment=14 1/3
9/22/2017 Hardware Modeling Using Verilog - - Unit 2 - Week 1

Week 3 Full custom

5) Which of the following is not true for standard cell based design? 1 point
Week 4
i. The heights of the cells are fixed but the widths can be different.
Week 5 ii. Any number of cells can be placed in a row.
iii. The number of cells that can be placed in a row is fixed.
iv. It requires more design effort as compared to full custom design.

ii. and iii.

ii. only
iii. and iv.
iii. only

6) Which of the following represents the correct ordering with respect to speed of circuits 1 point
(fastest to slowest)?

Full custom, Gate array, Standard cell, FPGA

Full custom, Standard cell, FPGA, Gate array
Full custom, Gate array, FPGA, Standard cell
None of the above

7) Which of the following are true for structural design representation? 1 point

The design is represented as a netlist of gates.

The design is represented as a netlist of functional level modules.
The input-output functional behavior will be specified.
The “assign” statement in Verilog can be used to specify the design.

8) Which of the following statements are not true? 1 point

A test bench is required when we want to simulate a design.

When we map the design to an application specific integrated circuit, we do not need a
test bench.
When we map the design to a field programmable gate array, we need a test bench.
Simulation means generation of a gate level netlist from a behavioral specification.

9) What function do the following Verilog module implement? 1 point

module guess (f, a, b, c);

input a,b,c;
output f;
wire t1, t2;
nand #1 G1 (t1,a,b);
or #1 G2 (t2,b,c);
and #1 G3 (f,t1,t2);
endmodule

f = a’.b + a’.c + b’.c

f = a’.b + b’.c + c’.a
f = a.b + b.c + c.a
None of the above

10)What function do the following Verilog module implement? 1 point

module guess
https://onlinecourses.nptel.ac.in/noc17_cs21/unit?unit=6&assessment=14 (f, a, b, c); 2/3
9/22/2017 Hardware Modeling Using Verilog - - Unit 2 - Week 1
module guess (f, a, b, c);
input a,b,c;
output f;
wire t;
assign t = (a & b) | c;
assign f = a ^ t;
endmodule

f = a’.b + a’.b’.c
f = a’.c + a.b’.c’
f = a’.c + a’.b.c’
None of the above

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