Sie sind auf Seite 1von 3

Expt.

10 Phase Locked Loop


1. Objective :
To study working of Phase locked loop and to verify Capture and Lock range
To implement Frequency multiplier using PLL
2. Hardware required :
 Dual variable regulated low voltage DC source
 CRO, AFO, DMM (Digital Multimeter)
 Resistors, capacitors, NPN transistor (2N2222)
 565 PLL
3. Experimentation :
Design of Lock range and capture range :
1.2
f OUT =
4R 1C1
8f
f L = ± OUT
V
fL 1/2
f C = ±[ ]
2π(3.6)(10 )C 2
3

For f OUT = 2.5KHz C1 = 0.01μF


R 1 = 12KΩ
For V = 24V
f L = 833.3Hz
For C 2 = 10μF
f C =  61Hz
Circuit Diagram: +V=+ 10 V

R1 C2
12 KΩ C3 10 μF

10 8 0.001μF
Input 2 7 Demodulated Output

6 Reference Output

3 NE565 4 VCO Output

9 1

C1= 0.01μF

-V=-10V

Fig. 1 Circuit diagram of PLL to capture and lock Input


Procedure :

1. First theoretically calculate the free running frequency of PLL, Lock range and
capture range
2. Without giving any input to the PLL measure the free running frequency of PLL
through PIN 4.
3. Measure the output through PIN9 and compare the frequency of square wave and
triangular wave.
4. Note the amplitude of both triangular wave and square wave.
5. Set the function generator at 4V (pk-pk) square wave at free running frequency and
give it to PIN2.
6. Note the phase difference between input and output frequency.
7. Note the multimeter reading through PIN 7.
8. Constantly monitor the output through PIN 4 when you change the input frequency
through PIN 2 [see PIN 2 and PIN 4 output in dual mode].
9. Note how phase changes between input and output frequency when the input
frequency varies within the lock range.
10. Determine the lock range and capture range.

PLL application as Frequency Multiplier:

+V=+ 10 V

R1 C2
12 KΩ C3 10 μF

10 8 0.001μF
fin 2 7 Demodulated Output

6 Reference Output

3 NE565 4 VCO Output fout=5fin

5 VCC= +5V 5 R2

9 1 1 4.7KΩ

C1= 0.01μF 11 7490 R3

-V=-10V 10KΩ

2 3 6 7 10

Procedure:

1. Rigup the circuit as shown in the circuit diagram.


2. Adjust the VCO output to middle of the lock range
3. Apply an input signal with frequency fin = fout/5 where fout is the lock range frequency.
4. Vary input frequency fin so that output frequency is within lock range and note that
output frequency fout=5fin

Conclusion : Lock range and capture range of PLL found and frequency multiplier
implemented using PLL