IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 27, NO.
1, JANUARY 2012
Steady-State Model and Power-Flow Analysis of
Single-Phase Electronically Coupled Distributed
Energy Resources
Mohamed Zakaria Kamh, Member, IEEE, and Reza Iravani, Fellow, IEEE
Abstract—This paper develops and presents the steady-state,
fundamental-frequency model of the single-phase distributed
energy resource (DER) unit which utilizes a single-phase
voltage-sourced converter (VSC) as the interface medium.
The model represents: 1) different operating and control modes
and 2) the operational constraints and limits of the VSC and
the host grid. The model is included in a sequential power-flow
analysis method using: 1) a backward-forward sweep algorithm
for single-phase laterals and 2) a sequence-components frame
solver for three-phase networks. The interface-VSC operating
limits are accommodated in the power-flow algorithm as an inter-
leaved step to increase computational efficiency of the power-flow
analysis tool. Case studies are conducted to evaluate and verify
1) the accuracy of the proposed model and 2) the computational
efficiency of the power-flow algorithm.
Index Terms—Distributed energy resources, electric vehicles,
single-phase voltage-sourced converter (VSC), power-flow
analysis.
I. INTRODUCTION
T HE increasing demand for the clean and renewable energy
resources and the governmental policies (e.g., the feed-in
tariff (FIT) and microFIT programs [1], [2]) are the main driving
forces to the wide-spread penetration of the distributed genera-
tion (DG) units into the medium- and low-voltage distribution
grids. The expected presence of the plug-in hybrid electric ve-
hicle (PHEV) [3] and the electric vehicle (EV) [4] will also im-
pact the distribution grids due to the additional load of charging
the vehicle batteries. Moreover, EVs with the vehicle-to-grid
(V2 G) power-transfer capability can inject power into the dis-
tribution network, thus also act as DG units [5]–[8].
The single-phase ac–dc voltage-sourced converter (VSC) is
the most widely-adopted interface medium for small scale DER
units [9]–[12]. The single-phase VSC is efficient, compact,
expandable, bidirectional, and can be connected to single-
and three-phase distribution networks [13], [14]. As such,
an array of dynamic and steady-state models of single-phase
VSC-coupled DER units, incorporated in the power system
software tools, is essential to analyze, plan, and control the
active distribution systems. Among these software tools, the
Manuscript received January 02, 2011; revised May 27, 2011; accepted
September 25, 2011. Date of publication November 29, 2011; date of current
version December 23, 2011. Paper no. TPWRD-00003-2011.
The authors are with the Department of Electrical and Computer En-
gineering, University of Toronto, Toronto, ON M5S 3G4 Canada (e-mail:
mohamed.kamh@ieee.org; iravani@ecf.utoronto.ca).
Digital Object Identifier 10.1109/TPWRD.2011.2172640
0885-8977/$26.00 © 2011 IEEE
131
steady-state power-flow analysis tool is the focus of this paper.
Accurate power-flow analysis is not only to determine the
system steady-state operating point, but also to accurately and
efficiently initialize dynamic analysis tools (e.g., the electro-
magnetic transients analysis tools [15]).
The steady-state models of the three-phase VSC have been
extensively reported and incorporated in different three-phase
power-flow analysis algorithms for the three-phase distribu-
tion grid [16]–[20]. However, the steady-state model of the
single-phase VSC-based DER units, including the operating
constraints of the VSC and the host grid, has not been reported.
This paper: 1) develops a steady-state, fundamental frequency
model of the single-phase VSC-coupled DER unit and 2) incor-
porate the model into a power-flow algorithm. The developed
VSC-coupled DER model presents:
• the VSC operational and control modes (e.g., bidirectional
power exchange, constant power-factor, reactive power
support [13]);
• the VSC operational limits and constraints (e.g., max-
imum current, maximum modulation index, and maximum
voltage) at the point of common coupling (PCC).
The sequential power-flow method, presented in [17]–[20]
is deployed to incorporate the single-phase VSC-coupled DER
model in a three-phase power-flow algorithm. Based on the se-
quential approach, the VSC terminal conditions are evaluated.
Then, if any of the interface-VSC or host DER unit constraints
are violated, the real and reactive reference setpoints of the
VSC controllers are updated to guarantee compliance with the
operational constraints of the DER unit and its interface-VSC
[17]. Finally, the VSC terminal voltage is specified prior to pro-
ceeding to the following power-flow iteration. The sequential
power-flow algorithm is easy to implement and readily permits
integration of various control functions and operating limits of
the interface VSC [21].
The proposed VSC model is incorporated into two different
algorithms within the sequential power-flow method, namely:
1) the single-phase backward-forward sweep algorithm (BFSA)
[22], [23] for power-flow analysis of single-phase laterals, and
2) the three-phase sequence-components frame power-flow
solver (SFPS) [17] for the analysis of three-phase networks.
The details of the BFSA, the SFPS, and models of power lines,
loads, transformers, and other apparatus have been reported in
the technical literature [16]–[18], [22]–[25] and are not reiter-
ated in this paper. Several case studies are conducted to validate
the proposed VSC model and demonstrate the computational
efficiency of the sequential power-flow technique.
132
Fig. 1. Schematic diagram of a dual-stage single-phase VSC-coupled DER
unit.
II. STEADY-STATE MODEL OF SINGLE-PHASE
VSC-COUPLED DER UNITS
A. Control Objectives of Single-Phase VSC
The power-electronic converters used to interface small-scale
DER units to the host grid, according to their configurations,
are classified into 1) single stage and 2) dual stage [10]. In the
single-stage configuration, a single-phase full-bridge VSC is di-
rectly connected to the primary source of the DER unit, and is
equipped with 1) a maximum power point tracking (MPPT) con-
troller and 2) a grid-current controller to inject sinusoidal cur-
rents into the grid [13]. However, the single-stage configuration
is not the preferred choice for DER applications [10].
The dual-stage converter configuration is widely deployed as
the interface for the small-scale DER applications where bidi-
rectional power exchange is desired (e.g., 1) integrating resi-
dential PV systems, energy storage, and PHEV [9], [11] and 2)
EV with the V2G power transfer capability [5]–[8]. In this con-
figuration, a dc–dc converter is located between the front-end
VSC and the primary source of the DER unit to perform the
MPPT function. The front-end VSC: 1) regulates the real power
transfer with the grid, and 2) can provide additional ancillary
services, such as reactive power compensation and power factor
correction [10], [13]. Fig. 1 shows a schematic diagram of a
DER unit coupled to the host grid, at the PCC bus, via a dual-
stage single-phase VSC. The dc–dc converter is confined in a
dashed box to highlight that it is an optional block and if re-
moved, the single-stage converter is realized.
B. Assumptions
The VSC model presented in this paper corresponds to the
dual-stage VSC system. However, the model can be also tailored
to represent the less common, single-stage converter configura-
tions. Assumptions are made as follows.
• The DER primary source is not directly represented in
the model since the controllers of the interface-VSC are
assumed to perfectly regulate the dc-link voltage under
steady-state conditions.
• Only the fundamental-frequency model of the interface
VSC is considered (i.e., the model does not represent the
possible active harmonic filtering function of the single-
phase VSC [12], [26]).
• Per different codes and standards, the single-phase VSC is
not permitted to regulate the system voltage [10] (i.e., the
VSC is not equipped with voltage controllers). The VSC
is only allowed to regulate the real and reactive power ex-
change with the grid [13].
IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 27, NO. 1, JANUARY 2012
Fig. 2. Steady-state, fundamental-frequency model of a single-phase
VSC-coupled DER unit for the BFSA.
C. Steady-State Model of Dual-Stage Single-Phase VSC
Under steady-state conditions, the interface VSC exchanges
constant real and reactive power with the grid. The power
setpoints and dictate the VSC reference current
setpoints of the current controllers [9], [12], [13]. Based on
the power-flow algorithm into which the VSC model is in-
corporated, the following two VSC-coupled DER models are
developed.
1) VSC Model for the Single-Phase BFSA: Fig. 2 shows the
steady-state, fundamental frequency model of a single-phase
VSC-coupled DER unit, tailored for the single-phase BFSA.
The BFSA equations are developed based on the bus current
injection rather than power injection. Thus, the VSC is modeled
as a current source given by
(1)
where is the complex conjugate of a phasor quantity. In
(1), and are the phase-frame PCC voltage and the
DER current injection prior to the th BFSA iteration. It is worth
stating that the value of depends on the VSC control
mode as follows:
• In the power factor correction mode, is given by
(2)
where is a constant power factor greater than or equal
to 0.9, as specified by the codes and standards [10].
• In the reactive power support mode, the interface VSC sup-
plies the reactive power requirements of the local load [13].
In this case is a pre-specified value.
2) VSC Model for the Three-Phase SFPS: The single-phase
VSC-coupled DER units also can be directly connected to
the three-phase trunk of a distribution grid. In this case,
the VSC model should represent the unbalanced power ex-
change between the single-phase DER unit and the three-phase
power-flow of the grid.
The SFPS is a fast and accurate three-phase power-flow al-
gorithm, developed in the sequence-components frame, to ana-
lyze the three-phase power-flow of the distribution grid with a
high-depth of DER penetration [16], [17]. The steady-state, fun-
damental-frequency SFPS-based model of a single-phase VSC-
coupled DER unit is illustrated in Fig. 3. The positive-sequence
SFPS-based VSC model, Fig. 3(a), is a constant power source
whose real and reactive power components are
(3)
KAMH AND IRAVANI: STEADY-STATE MODEL AND POWER-FLOW ANALYSIS 133

Fig. 4. Equivalent circuit of the single-phase VSC-coupled DER unit to calcu-

Fig. 3. Steady-state, fundamental-frequency model of a single-phase
VSC-coupled DER unit for the three-phase SFPS algorithm, (a) positive-se-
quence model, (b) zero- and negative-sequence models.
late the converter internal parameters.
parameters. The equivalent impedance of the VSC series filter
of Fig. 4 is

where is the positive-sequence component of a three-phase (6)

quantity, prior to conducting the th SFPS iteration. The zero-
and negative-sequence SFPS-based models of the single-phase where , and are identified on Fig. 1.
VSC, Fig. 3(b), are constant current sources whose current
injections are updated prior to each power-flow it- A. VSC Phase Current Calculation
eration. The positive-, negative-, and zero-sequence current The VSC phase current is decomposed into: in-phase
components, Fig. 3, are with and perpendicular to the PCC voltage
phasor . Subsequent to the th power-flow iteration, the
current components are evaluated using

(7)

(4) (8)

where is where is the phasor magnitude. The net VSC current is

(9)
DER unit connected to Phase-A
DER unit connected to Phase-B
DER unit connected to Phase-C. B. VSC Modulation Index Calculation
(5)
Analogous to the discussion in Section III-A, the VSC mod-
ulation index is decomposed into two orthogonal components,
The phase-frame DER current for (4), , is given by (1). It namely and , such that
should be noted that, for an energy storage device, the value
of the real power exchange in (1) and (3) depends on
(10)
the current and previous states of the charge and the initial and
maximum stored energy [27], [28]. However, in this work, the
where is the modulation index subsequent to the th
values of these attributes, and consequently the storage device
power-flow iteration, and related to the VSC terminal voltage
real power exchange, are assumed to be specified and calculated
by
prior to conducting the power-flow analysis.

(11)
III. EVALUATING THE INTERFACE-VSC
INTERNAL PARAMETERS where is the converter constant and determined based on
the adopted modulation strategy [29]. For single-phase VSC, the
To incorporate the operating constraints of the interface-VSC
widely deployed modulation technique is the 3-level, naturally
in the power-flow algorithm, its internal parameters, i.e., mod-
sampled, sinusoidal PWM (SPWM), for which .
ulation index and phase current, must be determined in the
is given by (12). From (11) and (12)
phase-frame. Regardless of the type of the power-flow algo-
rithm (SFPS or BFSA), subsequent to each iteration, the PCC
terminal voltage is evaluated in the phase-frame and used to
calculate the VSC modulation index and the DER current
. Fig. 4 shows the equivalent circuit of the single-phase
VSC-interfaced DER unit used to determine the converter (12)
134 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 27, NO. 1, JANUARY 2012

(13) B. Modulation Index Limit

(14) Prior to proceeding to the th power-flow iteration, if
(evaluated by (11)–(15)) is greater than (which is 1 for
The coefficients in (13) and (14) are the SPWM [29]), then and are updated using

(19)

The updated power setpoints, satisfying the modulation index

(15) limit, are evaluated by substituting from (19) into (13) and
(14), and solving for and . This procedure yields

(20)
IV. VSC OPERATIONAL LIMITS
To deduce a feasible power-flow solution, none of the inter- (21)
face VSC internal parameters should exceed their corresponding
limits. In addition, the single-phase DER operation (generation
Suffix in (20) and (21) refers to the reference setpoints ful-
or storage) should be specified such that the corresponding PCC
filling the modulation index constraint.
bus voltage does not exceed the maximum value dictated by the
utility system . C. PCC Bus Voltage Limit
The sequential technique [17] imposes these constraints sub-
sequent to each power-flow iteration by (i) calculating the VSC The high-depth penetration of single-phase DER units can re-
internal parameters as discussed in Section III and (ii) modi- sult in excessive voltage rise at different buses of the system. It
fying the reference power setpoints and of the is the utility common practice to adjust the system voltage via
VSC controllers to meet the constraints, in case of contraven- three-phase voltage regulators. However, these regulators are
tion. This section presents a systematic approach to update the much slower compared to the DER response and do not provide
VSC power setpoints to satisfy all the operational limits of the the desired solution to the overvoltage problem. Instead, one or
interface VSC and the host grid, i.e., more of the following items can address the overvoltage issue:
• phase current limit ; • A (relatively large) storage unit is connected to the substa-
• modulation index limit ; tion bus. The storage unit is controlled to absorb the ex-
• PCC bus voltage limit . cessive DER power causing the overvoltage phenomenon.
This solution requires communication between the system
buses and the central energy management of the distribu-
A. Phase Current Limit
tion grid.
A heavily loaded distribution network is often characterized • The real and reactive power setpoints of the single-phase
by low-bus voltages, including the head busses of single-phase DER units, located at the violated busses, are reduced until
laterals. Consequently, the DER units connected to single-phase all of the system buses comply with the maximum voltage
laterals need to inject higher currents to meet their real and limit.
reactive power requirements. However, to obtain a feasible The latter solution is adopted in this paper and implemented
power-flow solution, each DER current should be within the in the sequential power-flow algorithm as follows. Subsequent
acceptable limits. to the th power-flow iteration, all the phase-frame bus voltages
Subsequent to the th power-flow iteration, if the VSC are evaluated. If the three-phase voltage at a PCC bus, to which
phase-frame current (calculated by (7)–(9)) exceeds than a single-phase DER unit is connected, exceeds the maximum
, then and are re-calculate using allowable value, the DER power setpoints are updated by using

(16) (22)

Substituting for from (16) into (7) and (8), and where is the magnitude of the
solving for and , yields the power setpoints used maximum violating PCC phase voltage, and is the
in the iteration. The updated power setpoints are given utility upper limit of the phase voltage magnitude at any bus.
by For example, based on the Canadian standards, the maximum
voltage in the medium-voltage (MV) networks (1 to 50 kV)
(17) should not exceed 1.06 p.u. [30]. As such, is set to
1.06 p.u. in this paper. In (22), suffix refers to the reference
setpoints satisfying the PCC voltage constraint.
(18)
It should be noted that unlike (17)–(21), which are based on
mathematical closed forms, (22) is heuristically developed since
Suffix in (17) and (18) refers to the setpoints that satisfy the deducing a closed-form expression that relates phase voltages at
DER phase current limit. different busses to a specific DER contribution practically is not
KAMH AND IRAVANI: STEADY-STATE MODEL AND POWER-FLOW ANALYSIS 135

feasible. In addition, since updating the real and reactive power

setpoints of the DER units at the violating buses is not based on
a mathematical closed form, fulfilling the bus voltage constraint
is expected to be the most computationally demanding part of
the power-flow algorithm, as will be detailed in Section V.

D. VSC Reference Power Setpoints Update

The power setpoints, selected prior to the th
power-flow iteration, must satisfy the aforementioned three
operating constraints. As such, the real power setpoint
is selected based on

(23)

The same logic is deployed to select . Fig. 5. Single-line diagram of the CIGRE single-phase radial test feeder.

E. Sequential Power-Flow Algorithm

TABLE I
Subsequent to evaluating the phase-frame internal parameters PARAMETERS OF G1, G2, AND G3 OF FIG. 5
of each single-phase VSC-coupled DER unit, the corresponding (V = 7.2 kV AND S = 100 kVA)

operating limits are checked to ensure no violations occur. The

steps to determine the internal parameters, evaluate the oper-
ating limits, and update the phase-frame reference power set-
points are conducted sequentially after each power-flow itera-
tion. Therefore, the term “sequential” is used to describe the
proposed power-flow algorithm [17].

V. VALIDATIONS
To verify the accuracy and evaluate the computational effi-
TABLE II
ciency of the single-phase BFSA and the three-phase SFPS, in- POWER-FLOW RESULTS OF CASE-1: THE MAXIMUM
cluding the VSC model of Section II and the power setpoint PHASE CURRENT LIMIT IS RELAXED
updating criteria described in Section IV, two benchmark ra-
dial feeders are used as test systems. The first feeder is the
single-phase radial feeder of the CIGRE MV benchmark dis-
tribution network [31], and is used to evaluate the performance
of the single-phase sequential-BFSA. The computational effi-
ciency of the three-phase sequential-SFPS is evaluated based on
the IEEE 34-bus feeder [32].

A. Sequential Single-Phase BFSA

The single-line diagram of the CIGRE MV single-phase
radial feeder is depicted in Fig. 5. The feeder is a 7.2-kV
single-phase lateral with an R/X ratio of 1.56. The total system
load is 248.75 kW and 90.16 kVAr. The feeder of Fig. 5 is
equipped with three identical single-phase VSC-coupled DER
units, namely G1, G2, and G3, connected to Bus-6, Bus-11, and
Bus-12, respectively. Each DER unit is controlled to inject 0.6
p.u. power at a 0.9 power factor. The system loads and parame- are given in Table II. The DER violated parameters are shown
ters are given in [31]. The DER parameters are extracted from in boldface.
[13], and given in Table I. The sequential BFSA power-flow As indicated in Table II, the phase currents of the three DER
algorithm, including the proposed DER model, is implemented units exceed the maximum corresponding limit (0.66
in the MATLAB® platform and the following two case studies p.u.) and indicate that the power-flow solution is not feasible.
are conducted. If the DER current constraint of Section IV-A is imposed,
1) Case-1: Maximum Phase Current Limit Violation: In then once the violation is detected subsequent to the first
Case-1, the head node (Bus-1) voltage is 0.9 p.u. The corre- power-flow iteration, the real and reactive power reference
sponding power-flow solution and the DER internal parameters, setpoints of the three DG units are updated based on (17) and
associated with relaxing the DER maximum phase current limit, (18), respectively. The new real and reactive power reference
136
TABLE III
CASE-1: UPDATED REAL AND REACTIVE POWER SET
POINTS OF THE THREE DER UNITS
TABLE IV
POWER-FLOW RESULTS OF CASE-1: MAXIMUM
PHASE CURRENT LIMIT IS IMPOSED
TABLE V
POWER-FLOW RESULTS OF CASE-2: MAXIMUM
MODULATION INDEX LIMIT IS RELAXED
setpoints of the three DER units are given in Table III. The
corresponding power-flow solution, the DER currents, and the
modulation indices are shown in Table IV.
Table IV shows that the constraints of the DER units are
satisfied. The sequential power-flow algorithm adjusts the real
and reactive power of G1, G2, and G3 to
, and p.u., respectively. The
results of Tables III and IV demonstrate the validity and accu-
racy of (17) and (18).
2) Case-2: Violating the Maximum Modulation Index Limit:
In Case-2, the head node (Bus-1) voltage is 1.0 p.u. The corre-
sponding power-flow solution and the DER internal parameters,
associated with relaxing the DER maximum modulation index
limit, are given in Table V. The violated DER parameters are
shown in boldface.
IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 27, NO. 1, JANUARY 2012
TABLE VI
CASE-2: UPDATED REAL AND REACTIVE POWER
SETPOINTS OF THE THREE DER UNITS
TABLE VII
POWER-FLOW RESULTS OF CASE-2: THE MAXIMUM
MODULATION INDEX LIMIT IS IMPOSED
Table V shows that the modulation indices of the three DER
units exceed their maximum allowable limits. As such, this
power-flow solution is not acceptable. However, adjusting the
real and reactive power setpoints of the three DER units to the
values given in Table VI guarantees that the modulation indices
of the three DER units are bounded to 1.0 as required. The values
in Table VI are evaluated by (20) and (21). The corresponding
power-flow solution and the DER internal parameters are shown
in Table VII. The results of Tables VI and VII demonstrate the
accuracy and validity of the model given by (20) and (21).
Although the violation in both Case-1 and Case-2 is less than
1% of the corresponding limit value, the proposed closed forms
of (16)(21) accurately update the real and reactive power set-
points of the DER units once the violation is detected within
the sequential power-flow algorithm. In fact, the numerical ac-
curacy of the formulae of Sections IV-A and IV-B, when sub-
jected to minute violations, emphasizes that the proposed se-
quential power-flow algorithm can handle larger violations with
the same performance.
As shown in Tables II and V, all of the bus voltages are below
the maximum operating limit of 1.06 p.u. Consequently, up-
dating the power setpoints according to Section IV-C is neither
required nor addressed in Case-1 and Case-2. The accuracy and
validity of (22) are presented in Section V-B.
B. Sequential Three-Phase SFPS
The IEEE 34-bus system [32] is a 24.9 kV, three-phase, multi-
grounded radial feeder. The system has three-phase untrans-
posed power lines and unbalanced loads. The total system load
is kVA on phase-A, kVA on phase-B, and
kVA on phase-C. To validate the computational ef-
ficiency of the three-phase sequential-SFPS, including the pro-
posed single-phase VSC model of Fig. 3, the system power flow
is investigated based on the following assumptions:
KAMH AND IRAVANI: STEADY-STATE MODEL AND POWER-FLOW ANALYSIS
Fig. 6. Single-line diagram of the modified three-phase IEEE 34-bus radial
feeder.
TABLE VIII
CASE-3: DER PHASE DISTRIBUTION*
• All loads are represented by constant power loads.
• The distributed loads are lumped and equally divided be-
tween the sending and receiving buses of the corresponding
line segment.
• All of the single-phase laterals and their loads are merged
into their corresponding head nodes. The equivalent single-
phase lumped load is calculated by using the coincidence
factor method [16].
• The 4.16 kV three-phase lateral (Buses 888 and 890), in-
cluding its associated loads, is lumped into node 832 as a
three-phase constant power load.
• No voltage regulator is considered.
To investigate the overvoltage phenomenon associated with
the DER penetration: 1) the substation bus voltage (bus 800)
is adjusted to 1.05 p.u., as recommended in [32], and 2) the
feeder is equipped with multiple single-phase VSC-coupled
DER units. The SFPS is augmented with the DER model of
Fig. 3 and implemented in the MATLAB platform, and the
following case studies are conducted.
1) Case-3: Maximum PCC Voltage Limit Violation: In
Case-3, the system of Fig. 6 is equipped with 23 single-phase
DER units, one unit at each bus except at Bus-800. Each DER
unit is controlled to inject 0.12 p.u. power (1 MVA base value)
at 0.9 power-factor according to Table VIII. It should be noted
that the present utility practice does not permit such excessive
DER penetration. However, the future operational practices of
the distribution grids are envisioned to allow the distribution
network operator (DNO) to control and coordinate large DER
penetration so that the distribution grid, or parts of it, provides
prespecified voltage and power profiles with respect to the rest
of the power system (i.e., it mimics a virtual power plant (VPP)
with respect to the utility bus) [33], [34].
First, the maximum bus voltage constraint of Section IV-C is
relaxed, and the SFPS is used to determine the power-flow solu-
tion. The corresponding three-phase voltage profile is reported
in Table IX. Phase voltages exceeding 1.06 p.u. are shown in
boldface.
137
TABLE IX
CASE-3: THREE-PHASE VOLTAGE PROFILE WITHOUT CONSIDERING
THE MAXIMUM BUS VOLTAGE CONSTRAINT
TABLE X
CASE-3: UPDATED REAL AND REACTIVE POWER
SETPOINTS OF THE DER UNITS. S =
1 MVA
According to Table IX, all of the bus voltages, except those
of buses 800, 802, 806, 808, and 812, exceed the voltage limit
of 1.06 p.u. Therefore, the power-flow solution is not feasible.
When the maximum voltage constraint is considered, the real
and reactive power setpoints of the DER units at the violated
buses are updated, according to (22), to address the overvoltage
condition. The updated DER power setpoints and the resulting
three-phase voltage profile are given in Tables X and XI,
respectively.
Table X shows that the power setpoints of the DER units
connected to buses 802, 806, 808, and 812 remain at the orig-
inal value ( p.u.). The reason is that the up-
dating criterion (22) does not affect the power contribution of
the DER units at the nonviolated buses. In addition, the three-
phase voltage profile given in Table XI complies with the im-
posed maximum voltage constraint, which demonstrates the ac-
curacy and validity of (22).
2) Case-4: No DER Unit Connected to the Violated Bus: In
Case-3, all of the violated buses of Table IX are connected to
DER units. However, there might be a scenario where a bus
experiences overvoltage due to DER units connected to other
buses. To investigate this scenario and verify the effectiveness
of the criterion of (22) in mitigating the corresponding overvolt-
ages, Case-4 is conducted.
In Case-4, the DER units at buses 814 and 846 are removed.
In addition, the power setpoints of the remaining DER units are
raised to p.u., compared to
138
TABLE XI
CASE-3: THREE-PHASE VOLTAGE PROFILE AFTER
ADJUSTING THE DER POWER SETPOINTS USING (22)
TABLE XII
CASE-4: THREE-PHASE VOLTAGE PROFILE WITHOUT CONSIDERING
THE MAXIMUM BUS VOLTAGE CONSTRAINT
p.u. for Case-3. The corresponding three-phase voltage profile,
calculated by the SFPS when the maximum voltage constraint is
relaxed, is given in Table XII. The voltages at the violated buses
are shown in boldface.
In addition to the voltages at buses 850, 816, 824, 828, 830,
and 854, where a DER unit is connected to each bus, Table XII
shows that the voltage at bus 814 (not connected to a DER unit)
exceeds 1.06 p.u. Thus, the power-flow solution of Table XII is
not acceptable.
To be effective and valid, the updating criterion of Sec-
tion IV-C should address the overvoltage at all busses, and not
only at those with DER connections. The three-phase voltage
profile of Table XIII verifies this fact. The voltage violation at
all of the busses, including those without DER units, is resolved
by updating the power setpoints of the DER units at buses 850,
816, 824, 828, 830, and 854. The updated real and reactive
power setpoints of the six DER units of the violated buses are
given in Table XIV.
C. Computational Efficiency of the Sequential Algorithms
An Intel Core2Duo, 3.16 GHz processor is used to conduct
the reported four case studies. In Case-1 and Case-2, the se-
quential power-flow algorithm converges in two iterations and
IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 27, NO. 1, JANUARY 2012
TABLE XIII
CASE-4: THREE-PHASE VOLTAGE PROFILE AFTER ADJUSTING
THE DER POWER SETPOINTS USING (22)
TABLE XIV
CASE-4: UPDATED REAL AND REACTIVE POWER SETPOINTS OF
THE DER UNITS AT THE VIOLATING BUSES. S =
1 MVA
the computational times for the solutions (i.e., Tables IV and
VII, are 0.023 and 0.026 s, respectively). This demonstrates the
computational efficiency of the proposed algorithm.
When the voltage constraint of the three-phase SFPS is re-
laxed, the algorithm converges to the solution of either Case-3
or Case-4, given in Tables IX and XII, respectively, in 0.094
s. However, if the voltage constraint is imposed, the computa-
tional time increases to 1.216 and 0.896 s for Case-3 and Case-4,
respectively. As discussed in Section IV-C, satisfying the max-
imum voltage constraint, using the heuristic expression of (22),
is expected to be the most time demanding part of the algorithm
since it is not based on a mathematical closed form. This com-
putational time can be reduced by using a fast parallel program-
ming technique for the SFPS implementation [35].
VI. CONCLUSION
This paper presents a steady-state, fundamental frequency
model of the single-phase small-size DER unit interfaced by a
single-phase VSC to the distribution grid. The proposed model
addresses the converter’s different 1) operational modes (e.g.,
bidirectional power transfer, constant power-factor, and reactive
power compensation, and 2) operational constraints (i.e., max-
imum modulation index, maximum current, and maximum bus
voltage). The developed model is incorporated in single-phase
(BFSA) and three-phase (SFPS) power-flow software packages.
In contrast to the existing methods, the developed model uti-
lizes a sequential iterative process with respect to the network
and the VSC solutions to guarantee that the power-flow solution
adheres to the network and the VSC constraints and operating
limits. The proposed model and the developed sequential
power-flow solvers are implemented in MATLAB and applied
KAMH AND IRAVANI: STEADY-STATE MODEL AND POWER-FLOW ANALYSIS
to single-phase and three-phase radial benchmark networks.
Four case studies are conducted, and the power-flow results
demonstrate: 1) the validity of the proposed VSC model and
2) the computational efficiency of the sequential power-flow
algorithms.
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Mohamed Zakaria Kamh (M’11) received the
B.Sc. (Hons.) and M.Sc. degrees in electrical power
and machines engineering from Ain Shams Univer-
sity, Cairo, Egypt, in 2003 and 2007, respectively,
and the Ph.D. degree in electrical engineering from
the University of Toronto, Toronto, ON, Canada, in
2011.
Currently, he is a Visiting Scientist at the Center for
Applied Power Electronics (CAPE) at the University
of Toronto. He was a Power System Consultant and
Network Design Engineer from 2003 to 2007. His re-
search interests include power electronics and their applications in smart grids
and virtual power plants.
Reza Iravani (F’03) received the B.Sc. degree
in electrical engineering from Tehran Polytechnic
University, Tehran, Iran, in 1976, and the M.Sc.
and Ph.D. degrees in electrical engineering from the
University of Manitoba, Winnipeg, MB, Canada, in
1981 and 1985, respectively.
Currently, he is a Professor at the University of
Toronto, Toronto, ON, Canada. His research interests
include power electronics and applications of power
electronics in power systems.