School of Electronics

Lecture 5
Designing Combinational Logic Circuits
Circuit Design

• Logic circuits whose outputs are determined solely by their inputs are known as combinational logic.
• Combinational logic circuits do not involve feedback loops or timing delays.
• Design method is as follows:
(i) Statement of problem
(ii) Construction of truth table
(iii) Extraction of logic expression
(iv) Simplification of logic expression
(v) Implement circuit using logic gates.

Extraction of Logic Expression from the Truth Table

• Assume that the problem has been expressed as a truth

table showing the relationship between all inputs and A B C Y
all outputs. ( the actual values don’t matter) 0 0 0 0
• The Boolean expression can be extracted as follows: 0 0 1 1
• Write an AND term for each row of the truth table 0 1 0 1 A BC
where the output is a logic ‘1’ 0 1 1 0
• Each AND term contains each input variable in either 1 0 0 0 ABC
inverted or non-inverted form (complemented or 1 0 1 0
un-complemented) 1 1 0 1
• If ‘1’ write as un-complemented: if ‘0’ write as 1 1 1 0
complemented.
• All the AND terms are then ORed together to produce
AB C
an expression for the output.
• Simplification of logic expression can be achieved
using either Boolean Algebra or Karnaugh Maps.
Y =A BC +ABC +AB C
Boolean Algebra

• Mathematical means of expressing and manipulating logic expressions.

• Most of the normal rules of algebra apply, but there are some important exceptions.
• AND function denoted by a full stop (.) OR function denoted by + NOT expression denoted by a bar over
the expression.

Single Variables
AND Variables OR Variables
X.0 = 0 X+0 = X
X.1 = X X+1 = 1
X.+
X X=
X =0
1 X+X = X
X.X = X
Multi-Variables

X+Y = Y+X
X.Y = Y.X
X+(Y+Z) = (X+Y)+Z = X+Y+Z
X.(Y.Z) = (X.Y).Z = X.Y.Z.
X.(Y+Z) = X.Y+X.Z
(W+X).(Y+Z) = WY+XY+WZ+XZ
X+X.Y = X(1+Y) = X
X +XY = X +Y

Electronics 1 – Outline Lecture Notes 18

School of Electronics

• Redundancy Theorem. A+A.B+A.B.C+A.B.C.D….etc. = A

• Race Hazard Theorem. Add a redundant term to make simplification easier. If a variable occurs in both
inverted and non-inverted form, other variables ANDed with them is a redundant term. e.g.
XY +XZ = XY +XZ +YZ
in this case YZ is the redundant term.
• De Morgan’s Theorem – to find the inverse of a Boolean expression, invert all the variables and replace the
(.) with (+) and the (+) with (.)
B
Karnaugh Maps 0 1
A
• Graphical way of representing a truth table.
• Suitable for up to four variables. Above this number 0 AB AB
other methods easier.
• Expression to be simplified must be in ‘min term’
format (sum of products). AB
1 AB
• Expression involving two variables A and B can be
represented on a map with 22 squares. Three variables
need 23 squares and four variables 24 squares. AB
• Each square has a unique address.
• Cells side by side horizontally or vertically (but not diagonally) C 00 01 11 10
are said to be adjacent.
• The cell addresses of adjacent cells may only differ by 1. 0 A BC
• The map is continuous top to bottom and side to side.
• The top and bottom rows are thus adjacent. Similarly the columns 1 A BC
at each end are adjacent.
• Each group of variables making up the Boolean equation
to be simplified is mapped.
• Once the function has been mapped, it can be simplified AB
by grouping adjacent cells.
CD 00 01 11 10
Rules for Minimisation using K-Maps
00
• Group cells in the largest binary groups. i.e. 16, 8, 4, 2
• Only group cells that are adjacent.
• One cell may be included in more than one group, but 01 A BCD
only to ensure that another single cell is grouped.
• If a variable occurs within a group in both complemented
and un-complemented form it is eliminated. 11 ABCD
• Note that in a four variable expression, a group of 8 cells
represents a singe variable (say A), a group of 4 cells a double
10
variable (say AB), a group of 2 cells a triple variable (say ABC)
and a single cell a quad. variable (say ABCD).
• Finally, form the OR sum of all the expressions generated by each loop.

‘Don’t Care’ States

• Sometimes there are ‘don’t care’ states. These are redundant logic variables that do not affect the outcome
of the Boolean expression.
• These may be marked on the Karnaugh map with an X.
• They may be used to complete a loop if required, but not used if this is unnecessary.

Electronics 1 – Outline Lecture Notes 19