Sie sind auf Seite 1von 6

UNIVERSITY OF GLAMORGAN

Prifysgol Morgannwg
Examinations:
MAIN ASSESSMENT SESSION 2006/07

Validated Module Validated Module Title:


Code:EE2S06 Digital Electronics

Date Time Duration:


3 hours

Open/Closed Book And Rubric checked

Duration checked And Questions checked

Attachments checked And Amendments checked

I confirm that the attached paper is accurate, complete and appropriate for use in the
examination room, includes all necessary attachments relevant to the examination and
that all attached papers and documents are of a quality ready for photocopying.

Module Print Name: Signature:


Leader: Dr. Ali Roula

Admin Print Name: Signature:


Check:

Contact
Number:

FOR ADMINISTRATIVE CHECK ONLY

0
UNIVERSITY OF GLAMORGAN
Prifysgol Morgannwg

Examinations:
MAIN ASSESSMENT SESSION 2006/07

Validated Module Validated Module Title:


Code:EE2S06 Digital Electronics

Date (Student Registry use only) Time (Student Registry use only) Duration:
3 hours

The following items are provided:

Examination book (inc 2 sheets graph paper)

Instructions to Candidates:

This examination paper is a CLOSED book examination.

This paper contains a total of … 8 examination questions.

Answer 5 out of 8 questions

Page 1 of 5 Please turn over …


SECTION A

QUESTION 1

a) Design a logic circuit (using logic gates) for the one-to-two demultiplexer shown in
Figure Q1.
4 marks

A
Input DEMUX Outputs
X
B

Control
‘0’ selects A
‘1’ selects B

Figure Q1
b) A (4 to 10) decoder is able to accept a 4 bit binary input corresponding to the
binary representation of decimal numbers between numbers 0 to 9. The output
gives a logic ‘1’on on the output line corresponding to the decimal number.
E.g. if the input is (0000) the first output will be switched to 1. If the input is
(0001), the second output is switched to 1 etc. Design the required logic
circuit.
8marks
c) Draw a diagram to show how four D-type flip-flops can be used to construct a four
stage shift register.
4 marks
d) Using the multiplexing principle, add a new control signal S to your shift register to
allow data to be input in parallel (S=1) or in series (S=0).
4 marks

Total Marks for Question 1 =20

QUESTION 2

a) What are hardware description languages (HDL) and how are they different
from computer programming languages such as C? Also, mention two widely
used HDLs.
5 marks
b) What are the 4 levels of abstraction in digital circuit design?
5 marks

c) Write a simple VHDL program that implements a 2 by 2 bit half adder.


5 marks
d) Extend your program to a full adder.
5 marks
Total Marks for Question 2 =20

Page 2 of 5 Please turn over …


QUESTION 3

a) Draw the truth tables and logic symbols for:

(i) S-R flip-flop (ii) J-K flip-flop (iii) D-type flip-flop (iv) T-type
flip-flop.
5 marks
b) Design an asynchronous binary counter using D flip-flops which will count to 15
and then reset.
5 marks
c) Design an asynchronous binary coded decimal counter (BCD) using D-type flip-
flops which will count to 9 and then reset.
5 marks
d) Extend your design to make a ‘hundreds’, ‘tens’ and ‘units’ BCD counter. Explain
how the circuit works.
5 marks

Total Marks for Question 3 =20

QUESTION 4

a) Name two types of digital to analog (DAC) converters. Explain the relationship
between DAC resolution and the voltage range
5 marks

b) With the help of a schematic, explain the principle of operation of a flash analog to
digital converter (ADC).
5 marks

c) A digital ramp (ADC) has a bit-resolution of 4 bits and a voltage resolution of


100mV. The ADC is fed with a voltage of 10 Volts.
Using a Voltage graph, explain the functioning of the ADC and determine its binary
output.

5 marks

d) Draw the voltage graph if we were to use a successive approximation ADC instead.

5 marks

Total Marks for Question 4 = 20

Page 3 of 5 Please turn over …


QUESTION 5

a) Give a diode based implementation or the logic gates “AND” and “OR”.
5 marks

b) Explain the difference between TTL and CMOS technologies in terms of


design, power consumption, commutation speed and target applications.
5 marks

c) Using a diagram, illustrate the main components of the Van Newmann computer
machine. Explain the role of each part.
5 marks

d) What is the predication made by Moore’s law with regards to the evolution of
semiconductor integration? What are the limits of this evolution? What are the
possible new technologies that could in the future replace the current semiconductor
based computing machines.

5 marks

Total Marks for Question 5 = 20


QUESTION 6

a) What is the difference between Moore and Mealy diagrams?


5 marks

b) Explain the different steps involved in designing Synchronous counters


5 marks

c) Using JK flip-flops, design a synchronous counter that will count the following
number sequences:
5 marks

0 1 3 2 7 0 1 3 2 7 0 1 3 2 7 etc.

d) Using the state machine diagram design methodology, Design a pattern recognition
system that will detect the following pattern in a stream of bits:101

5 marks

Total Marks for Question 6 = 20

Page 4 of 5 Please turn over …


QUESTION 7

A circuit has 4-bit binary input ranging from 0000 to 1111 . The circuit detects
even numbers from odd numbers i.e. Output is high when the input is
0,2,4,8….,14. and low when input is: 1,3,5,7….15.

a- Provide the truth table for this circuit.


5 marks
b- Simplify the logic expressions using Karnaugh maps.
5 marks
c- Provide a possible design for this circuit using logic gates.
5 marks

Total Marks for Question 7 = 20

QUESTION 8

a) Draw the truth table for a full adder.

A Cout
Full Adder
B
Cin S

Figure Q8

From the truth table, obtain Boolean expressions for both the sum S and the
carry Cout.
5 marks

b) Hence design a 1 bit full adder using a minimal number of logic gates.
7 marks

c) Design a 4 bit sequential adder based on the design obtained in question b.


The two 4 bit operands arrive sequentially i.e. first A then B.
8 marks

Total Marks for Question 8 = 20

END OF PAPER

Page 5 of 5 Please turn over …