1.

DESIGN A SYNCHRONOUS COUNTER TO SEQUENCE 0-1-4-6-7-5-0 USING

POSITIVE EDGE TRIGGERED JK FLIP-FLOPS WITH MINIMAL COMBINATIONAL
GATING.

Solution : There are 6 distinct states and hence it is a mod-6 counter which requires three JK
flip-flops.

000

101 001

111 100

110

Fig :State diagram

The excitation table for implementing this counter using JK flipflop

Cell Present Next state Flip-flop inputs
.No state
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 1 0 - 0 - 1 -
1 0 0 1 1 0 0 1 - 0 - - 1
2 0 1 0 - - - - - - - - -
3 0 1 1 - - - - - - - - -
4 1 0 0 1 1 0 - 0 1 - 0 -
5 1 0 1 0 0 0 - 1 0 - - 1
6 1 1 0 1 1 1 - 0 - 0 1 -
7 1 1 1 1 0 1 - 0 - 1 - 0

Fig: Excitation table

Q1Q0 Q1Q0
00 01 11 10 00 01 11 10
0 - - - -
0 1 - -
1 - - - - 0 1 0 0

J2=Q0 K2=Q1’Q0
 Q1Q0 Q1Q0
00 01 11 10 00 01 11 10
0 0 0 - - - - - -
1 1 0 - - - - 1 0

J1=Q2Q0’ K1=Q0

00 01 11 10 00 01 11 10
1 - - - - 1 - -
0 - - 1 - 1 - -
J0=Q2’+Q1 K0=Q1’

Fig: K-map
2.DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN
COUNTER

AIM:
To design and implement 3 bit synchronous up/down counter.

COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 -2 no’s

2. 3 I/P AND GATE IC 7411 - 1
3. OR GATE IC 7432 - 1
4. XOR GATE IC 7486 - 1
5. NOT GATE IC 7404 - 1
6. IC TRAINER KIT - 1
7. WIRES - AS REQUIRED

PROCEDURE

1. Connections are given as per circuit diagram.

2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.
Result :
3.Write an ALP to check number of ones and zeroes in the given data.
DATA SEGMENT
X DB 0AAH
ONE DB ?
ZERO DB ?
DATA ENDS
CODE SEGMENT
ASSUME CS: CODE, DS: DATA
START: MOV AX, DATA
MOV DS, AX
MOV AH, X
MOV BL, 8 ; Initialize BL to 8.
MOV CL, 1 ; Initialize CL to 1.
UP: ROR AH, CL ; Perform the single bit rotate operation
; With respect to right.
JNC DOWN ; if no carry go to DOWN label.
INC ONE ; Increment one.
JMP DOWN1 ; Jump to DOWN1
DOWN: INC ZERO ; Increment ZERO.
DOWN1: DEC BL ; Decrement the BL.
JNZ UP ; If no zero go to UP label
MOV AH, 4CH
INT 21H
CODE ENDS
END START

Output: Ones--------04
Zeros--------04
4.Write an ALP to find the GCD of two 16 bit unsigned integers.
DATA SEGMENT
NUM1 DW 000AH
NUM2 DW 0004H
GCD DW ?
DATA ENDS
CODE SEGMENT
ASSUME CS: CODE, DS: DATA
START: MOV AX, DATA ; Load the Data to AX.
MOV DS, AX ; Move the Data AX to DS.
MOV AX, NUM1 ; Move the first number to AX.
MOV BX, NUM2 ; Move the second number to BX.
UP: CMP AX, BX ; compare the two numbers.
JE EXIT ; If equal, go to EXIT label.
JB EXCG ; If first number is below than second,
; go to EXCG label.
UP1: MOV DX, 0H ; Initialize the DX.
DIV BX ; Divide the first number by second
; number.
CMP DX, 0 ; Compare remainder is zero or not.
JE EXIT ; If zero, jump to EXIT label.
MOV AX, DX ; If non-zero, move remainder to AX.
JMP UP ; Jump to UP label.
EXCG: XCHG AX, BX ; Exchange the remainder and quotient.
JMP UP1 ; Jump to UP1.
EXIT: MOV GCD,BX ; Store the result in GCD.
MOV AH, 4CH
INT 21H
CODE ENDS
END START

Input: 0A,04
Output: 02
 DIGITAL ELECTRONICS AND MICROPROCESSOR LAB
ASSIGNMENT QUESTIONS

1. DESIGN A SYNCHRONOUS COUNTER TO SEQUENCE 0-1-4-6-7-5-0 USING

POSITIVE EDGE TRIGGERED JK FLIP-FLOPS WITH MINIMAL
COMBINATIONAL GATING.
2. DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN
COUNTER.
3. WRITE AN ALP TO CHECK NUMBER OF ONES AND ZEROES IN THE GIVEN
DATA.
4. WRITE AN ALP TO FIND THE GCD OF TWO 16 BIT UNSIGNED INTEGERS.