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Digital System Design

■ Realization of a specification subject to the


optimization of
• Area (Chip, PCB)
* Lower manufacturing cost
* Increase manufacturing yield
* Reduce packaging cost
* Performance
* Propagation delay {combinational circuits)
• Cycle time and latency (sequential circuits)
* Throughput (pipelined circuits)
• Power dissipation
• Testability
* Earlier detection of manufacturing defects lowers overall cost
* Design time (time-to-market)
• Cost reduction
• Be competitive
Digital System Design Cycle

Design Idea -> System Specification


Behavioral (Functional) Design Pseudo Code , Ffow Charts
. Bus & Register Structure
Architecture Design

Logic Design NetUst (Gate & Wire Lists)

Circuit Design Transistor List


I
VLSI / PCB Layout
Physical Design

Fabrication & Packaging


Architecture Design
Control
Data Path Path
Design Automation & CAD Tools
■ Design Entry (Description) Tools
• Schematic Capture
• Hardware Description Language (HDL)
■ Simulation (Design Verification) Tools
• Simulators (Logic level, Transistor Level, High Level
Language “HLL")
■ Synthesis Tools
■ Formal Verification Tools
■ Design for Testability Tools
■ Test Vector Generation Tools
Hardware Description Languages
■ HDLs are used to describe the hardware for the
purpose of modeling, simulation, testing, design, and
documentation.
• Modeling: behavior, flow of data, structure
• Simulation: verification and test
• Design: synthesis
■ Two widely-used HDLs today
• VHDL: VHSIC (Very High Speed Integrated Circuit )
Hardware Description Language {IEEE standard)
• Verilog {from Cadence, now IEEE standard)
Hardware simulation
Simulation is an act of exercising a model of an actual component for
analyzing its conduct under a given condition and stimuli.

Requires
• Model of object
• Stimuli
Process
Details of results depend on level of details of model.
Simulation may be used to verify the results of any design stage.

Stimuli+ Repetition
Results/
of design
HDL code waveforms
stage
Simulation Process
Design Itlcti

SIMULATION TOOLS
Checks functionality
Behavioral Design Behavioral SirnulaU -i
Quick simulation
-+ÿ Flow Graph, Pseudo Code,

about timing and functionality


Provides detailed information
Data Path Design Dataflow Simmlatr r

Slower simulation
-+ÿ Bus &, Register Srmeture.

Logie Design -<— Gate Level Simulat >r

->ÿ Gate Wirelist, Netlist.

Physical Design Device simulator

->ÿ Transistor List* Layout ....

Manufacturing Final Testing


Product Sample- V

Chip or Board
1-47
Simulation
Types of simulation

1. Oblivious simulation
2. Event driven simulation

Oblivious simulation
Each circuit component is simulated at fixed time point.

Event driven simulation


Component is evaluated only when one of its input changes.
Simulation Types
■ Oblivious and Event-driven simulation

.L

b
Oblivious Simulation
■ Need a tabular netlist for oblivious simulation
■ Simulate fixed time intervals
■ Update table values at each interval

GATE FUNCTION' INPUT 1 INPUT Z VALUE

Input a 0
1 Input b - G
3
4
NOT
NOT
Z
1
-- 1
1
5 AND 1 3 0
6 AND 4 2 0
7 OR 5 6 0

Sequential computation of all output values continues until a single pass without any
changes
Event-Driven Simulation
■ Evaluate circuit only when events occur
■ Offers a faster simulation for digital systems
■ VHDL
Complex an event
isand efficient
driven simulation
Parallel processing, uses linked list structure
l 3 5

Lcccnd
Ini In2 Fnr. Out [nl ' fniiut 1; In2 Fnr. Function; Cw Output VSILLP;
Abstractions
■ An Abstraction is a simplified model of some Entity
which hides certain amount of the Internal details of
this Entity
■ Lower Level abstractions give more details of the
modeled Entity.
■ Several levels of abstractions (details) are commonly
used:
• System Level
• Chip Level More Details
■ Register Level
• Gate Level (Less Abstract)
• Circuit {Transistor) Level
• Layout (Geometric) Level
Design Domains &
Levels of Abstraction

Designs can be expressed / viewed in one of three possible domains


1. Behavioral Domain (Behavioral View)
2. Data flow
3. Structural/Component Domain (Structural View)

•Physical Domain (Physical View)


A design modeled in a given domain can be represented at several levels
of abstraction (Details).
Behavioral level of abstraction/ description
Most abstract
Functionality is described in software like procedure
Appropriate for
fast simulation
checking design ideas
modeling with standard cells

Data flow level of abstraction/ description :


Representation of movement and control of data
Imply unique hardware
Slower simulation than behavioral level abstraction

Structural description:
Lowest and most detailed level
Simplest to synthesize
Includes list of concurrently active components and their interconnections
Design vs. Synthesis
■ Synthesis
• Process of transforming H/W from one level of abstraction to
a lower one.
■ Synthesis may occur at many different levels of
abstraction
• Behavioral or High-level synthesis
• Logic synthesis
• Layout synthesis
■ Design
• A Sequence of synthesis steps down to a level of abstraction
which is manufacturable.
Synthesis Process

Behavioral Structural
Domain Domain

System - Gate

Chip — —
— Circuit

Register -> —*- Layout

Logic ►
Synthesis
Synthesis process
FPGA synthesis tools are available from FPGA vendors,
Such tools concentrate on
1. Resource sharing
2. Logic optimization
3. Binding

Resource sharing:
Logic units performing RTL operations are resources that can be shared between multiple
instances of same operation.

Types of resource sharing:


1. Directed by the synthesis tool through synthesis directives
2. Decided by the tool based on input description
c <= a + b; c <= a + b;
d <= a + b; c <= x + y;

Sharing without and with extra overhead


Silicon Compiler

Tool generates layout from netlist.


Optimizes chip area
Objectives of VHDL
■ Provide a unified notation to describe Electronic Systems (digital
hardware) at various levels of abstractions.
■ Standardization of documentation
* To support the communication of design data
■ System design time and cost
* reduced ambiguity in specification of design interfaces and design
functions
* reusability of existing designs
■ Open-system CAE tools
* can change CAE system without losing use of existing designs
* elimination of language translators
■ Improved integration of multi-vendor designs
* shared design databases become possible
* standard cells, behavioral models
VHDL Requirements
■ Support for design hierarchy
■ Library support
■ Sequential statement Overall system remains concurrent
■ Generic design
■ Type declaration and usage
■ Use of subprograms
■ Timing control
■ Structural specification
VHDL Requirements
· General Features
Documentation, High level design, Simulation,
Synthesis, Test, Automatic hardware
· Design Hierarchy
Multi-level description
Partitioning
· Library Support
Standard Packages
Cell based design
· Sequential Statements
Behavioral software-like constructs
· Generic Design
Binding to specific libraries
· Type Declaration
Strongly typed language
· Subprograms
· Timing
Delays, concurrency
· Structural Specification
Wiring components
History of VHDL
■ Created by DoD to document military designs for
portability
■ IEEE standard 1076 (VHDL) in 1987
■ Revised IEEE standard 1076 (VHDL) in 1993
■ IEEE standard 1164 (object types standard) in 1993
■ IEEE standard 1076.3 (synthesis standard) in 1996
· 1981 DoD Woods Hole MA : Workshop on HDLs ITAR restrictions

· 1983 DoD : Requirements were established Contract was awarded to


IBM, TI, Intermetrics and ITAR restrictions removed from
language

· 1984 IBM, TI, Intermetrics : VHDL 2.0 was defined

· December 1984 : VHDL 6.0 was released Software development started

· 1985 : VHDL 7.2 was released to IEEE ITAR removed from software

· May 1985 : Standard VHDL 1076/A

· December 1987 : VHDL 1076-1987 became IEEE standard

· 1993 : VHDL 1076-1993 was approved


VHDL Advantages
■ Modular
■ Hierarchical, allows design description:
* TOP-DOWN
• BOTTOM - UP
■ Portable
■ Can describe the Same design Entity using more than one view
(Domain):
• The Behavioral View { e.g. as an algorithm, Register-Transfer
(Data Flow), Input-Output Relations, etc)
• The Structural View.
■ This allows investigation of design alternatives of the same
Entity,
■ It also allows delayed detailed Implementations.
■ Can model systems at various levels of abstraction (System, chip
RTL, Logic (Gate))
■ VHDL can be made to simulate timing at reasonable accuracy,
Styles in VHDL
■ Behavioral
* High level, algorithmic, sequential execution
• Hard to synthesize well
• Easy to write and understand (like high-level language code)
■ Dataflow
• Medium level, register-to-register transfers, concurrent
execution
* Easy to synthesize well
• Harder to write and understand {like assembly code)
■ Structural
* Low level, netlist, component instantiations and wiring
* Trivial to synthesize
* Hardest to write and understand {very detailed and low level)
VHDL
Simulator

Layout
-> Synthesizer >

Netlist
Synthesizer

Other Tools

Analyzer
Converts vhdl code into intermediate form
Performs lexical analysis and syntax check
Library system
holds the library
Library management
Provides editing capability.
ELEMENTS OF VHDL Describing Components

Entity:
interface description
Generic characteristics

Architecture:
Functionality
Component declaration
Words Behavioral, Data flow, Structural are not the part of language.

Packages
■ Packages are used to encapsulate information that is
to be shared among multiple design units.
■ A package is used by the USE clause
• e.g. Use work.package_rame.all
Package package_name IS
component declarations
sub-program parameters
END package_name;

Package Body package_name IS


type definitions
sub-programs
END package_name;
Package Examples
■ Standard Package
• Defines phmitive types, subtypes, and functions.
• e.g. Type Boolean IS (false, true);
• e.g. Type Bit is (f0\ T);
■ TEXTIO Package
• Defines types, procedures, and functions for standard text I/O
from ASCII files.
Design Libraries...
■ VHDL supports the use of design libraries for
categorizing components or utilities.
■ Applications of libraries include
• Sharing of components between designers
• Grouping components of standard logic families
• Categorizing special-purpose utilities such as subprograms or
types
■ Exiting libraries
• STD Library
* Contains the STANDARD and TEXTIO packages
* Contains all the standard types & utilities
* Visible to all designs
• WORK library
* Root library for the user
...Design Libraries
■ IEEE library
• Contains VHDL-related standards
_
• Contains the stdjogic 1164 (IEEE 1164.1) package
• Defines a nine values logic system
■ To make a library visible to a design
• LIBRARY libname;
■ The following statement is assumed by all designs
•LIBRARY WORK;
■ To use the std_logic_1 1 64 package
•LIBRARY IEEE
•USE IEEE.std_logic_1164.ALL
Design Binding
■ Using Configuration, VHDL allows
* Binding of Entities and Architectures.
* binding of subcomponents of a design to elements of various
libraries.
Top-Down Design
■ Top-down design process uses a divide-and-conquer
strategy
■ Top-down design involves recursive partitioning of a
system into subcomponents until
• all subcomponents are manageable design parts
■ Design of a component is manageable if the
component is
• Available as part of a library
• Can be implemented by modifying an already available part
• Can be described for a synthesis program or an automatic
hardware generator.
Recursive Partitioning Procedure

Parition (system)
IF HardwareMappingOf(system) is done Then
SaveHardwareof(system)
ELSE
FOR EVERY Functionally-Distinct Part_l of System
Partition (Part_l)
END FOR;
END IF;
END Parition;

■ Mapping to hardware, depends on target technology,


available libraries, and available tools.

ex: for full custom design powerful synthesizer


and routing and placement program is
required
Top-Down Design, Bottom-Up
Implementation _

)esign

Impfementation SSC: system sub-component 2-11

output of top-down design process:= partition tree and hardware implementation


of terminals.

after top down design process=> bottom up implementation process= components


with hardware description are wired together to form it's parent component in the
tree until sud is implemented.
Design Verification
■ Initially, a behavioral description of system under
design (SUD) must be simulated to verify design.
■ After first level of partitioning
• A behavioral description of each of the subcomponents must
be developed
• A structural hardware model of the SUD is formed by wiring
subcomponents behavioral descriptions
• Simulating the new model and comparing it with original SUD
description verifies correctness of first level of partitioning

Behavioraf Model
Verifying Hardware Implementation of
SSC1 and SSC2
Behavioral Model

Mixed Level Model


Hardware implementation models of ssc1 and ssc2 are compared with the behavior of
ssc1 and ssc2

functionality should match

hardware models also have information regarding physical characteristics: time delay,
power consumption, temperature dependencies.
Verifying the Final Design
Behavioral Model

Hardware Level Model

verification of final design: sud is expressed as interconnections os terminal


components of partitions tree

and compared with behavioural model of sud


Verifying Hardware Implementation of
SSC3
Behavioral Model

Hardware Level Model

if the design is complex then final verification would be complex


for this : 1. partition tree is divided into subtrees
2.each subtree will be individually verified.
3. subtrees which are not having hardware descriptions at terminal nodes, behavioral models
of those nodes will be used instead.
Top Down Design of Serial Adder
■ Serial data is synchronized with clock and appear on a
and b inputs
■ Valid data bits on a and b appear after a synchronous
pulse on start
■ After eight clock pulses, the addition of a and b will
appear on result
■ The ready output is set to 1 to indicate that the result of
addition is ready and remains one until another start
pulse is applied
a
b
start
Serial Adder t result
ready
clock
Design Assumptions
■ Synthesis tools:
• Capable of synthesizing logic expressions to combinational
logic blocks
■ Design Library:
• A 2x1 multiplexer with active high inputs and outputs
• A synchronous D-FF with synchronous active high reset input
* VHDL models of library elements are provided
with active high logic
with timing details
and hardware level
characteristics
VHDL Model of 2x1 Multiplexer
Entity mux2_1 IS
Generic {dz delay: TIME := 6 NS);
PORT (sel, datal , dataO: IN BIT; z: OUT BIT);
END mux2_1;

Architecture dataflow OF mux2_1 IS


Begin
z <= datal AFTER dz_delay WHEN sel=T ELSE
dataO AFTER dz_delay;
END dataflow;
S1
datal 1D z z
dataO OD
VHDL Model of D-FF
Entity flop IS
Generic [tdreset, tdin: TIME := 8 NS);
PORT (reset, din, elk: IN BIT; qout: OUT BIT :=‘0’);
END flop;
Architecture behavioral OF flop IS qout
Begin reset -
1R Q
Process(elk)
Begin
din 1D
IF (elk = ‘0s AND clkTEvent ) Then 1C
_ _
IF reset = ‘Y Then
qout <= ‘0T AFTER td reset ;
ELSE elk
qout <= din AFTER td in ;
END IF;
END IF;
END process;
2-21
END behavioral ;
Divide-by-8 Counter
Entity counter IS
Generic (td_cnt: TIME := 0 NS);
PORT (reset, elk: IN BIT; counting: OUT BIT :ÿ0');
Constant limit: INTEGER :=8;
END counter ;
Architecture behavioral OF counter IS
Begin
Process(clk)
Variable count: INTEGER := limit;
Begin
IF (elk = 40' AND dk'Event ) THEN
-
IF reset (1' THEN count := 0 ;
ELSE LF count < limit THEN count:- count+1; END IF;
END IF;
-
IF count limit Then counting <- AFTER td_cnt;
ELSE counting <= AFTER td_cnt;
END IF;
END IF;
END process;
END behaviorai ;
variable assignment has no timing details associatÿt22
Serial Adder First Level of Partitioning

Can be synthesized Avaiiable in library


& previous designs
General Layout of Serial Adder

clock
Full-Adder VHDL Description
Entity fulladder IS
port (a, b, cin: IN bit; sum, cout: OUT bit);
END fulladder;

Architecture behavioral OF fulladder IS


Begin
sum <= a xor a xor cin;
cout <= (a and b) or (b and cin) or (a and cin);
END behavioral ;
Shifter VHDL Description
Entity shifter IS
port (sin, reset, enable, elk: IN bit;
parout: BUFFER Bit_Vector(7 downto 0));
END shifter;

Architecture dataflow OF shifter IS


Begin
sh: BLOCK (clk='0T AND NOT clk’STABLE)
Begin
parout <= GUARDED “00000000” WHEN reset=‘1s
ELSE sin & parout(7 downto 1} WHEN enableÿ V

ELSE parout; - -could use here UNAFFECTED (VHDL’93)


END BLOCK;
END dataflow ;
Structural Description of Serial Adder ...
Entity serialadder 15
PORT (ar b, start, clock: IN BIT; ready: OUT BIT;
result: OUT Bit_Vector (7 downto 0));
END serial_adder ;
Architecture structural OF serial_adder 15
Component counter IS
Generic (td_cnt: TIME := 8 NS);
PORT (reset, elk: IN BIT; counting: OUT BIT :=‘0S);
END component ;
Component shifter IS
port (sir. reset, enable, elk: IN bit; parout: BUFFER Bit_Vector(7 downto 0));
END component ;
Component fulladder IS
port (a, b. cin: IN bit; sum, cout: OUT bit);
END component ;
Component flop IS
Generic (td_reset, tdjn: TIME 8 NS);
PORT (reset, din, elk: IN BIT: qout: Buffer BIT :=‘0S);
END component ;
... Structural Description of Serial Adder

SIGNAL sum, carry_in, carry out, counting: BIT;


Begin
u1: fulladder port map (a, b, carryin, sum, carry _out);
u2: flop port map (start, carry_out, clock, carryjn);
u3: counter port map (start, clock, counting);
u4: shifter port map (sum, start, counting, clock,
result);
u5: ready <= NOT counting;
END structural ;
Second Level of Partitioning:
Partitioning Shifter _

■ Shifter needs eight flip-flops with synchronous reset


and clock enabling (derjFlop)
■ der_flop cannot be directly implemented with given
tools and library
Behavioral Model of der_flop
Entity der_flop IS
PORT (din, reset, enable, elk: IN BIT; qout: Buffer BIT :=‘0’);
END der_flop;
Architecture behavioral OF der_flop IS
Begin
Process(clk)
Begin
IF (elk = (0r AND clk'Event ) Then
IF reset = ‘11 Then
1
qout<= 0r;
ELSE
IF enable=T Then
qout <= din;
END IF;
END IF;
END IF;
END process;
END behavioral ;
Structural Description of Shifter
Entity shifter IS
port (sin, reset, enable, elk: IN bit;
parout: BUFFER Bit_Vector(7 downto 0));
END shifter ;

Architecture structural OF shifter IS


Component derflop IS
PORT (din, reset, enable, elk: IN BIT; qout: Buffer BIT :=[05);
END component;
Begin
b7: der flop port map (sin, reset, enable, elk, parout(7))'
bG: der flop port map (parout(7), reset, enable, elk, parout(G));
b5: der flop port map (parout(G), reset, enable, elk, parout(5));
b4: der_flop port map (parout(5), reset, enable, elk, parout(4));
b3: der flop port map (parout(4), reset, enable, elk, parout (3));
b2: der flop port map (parout(3), reset, enable, elk, parout(2));
b1: der flop port map (parout(2), reset, enable, elk, parout(1));
bO: der flop port map (parout(1), reset, enable, elk, parout(O));
END structural ;
Partitioning der_flop

der_flop

mux2_1 flop
Structural Description of der_flop
Entity der_flop IS
PORT (din, reset, enable, elk: IM BIT; qout: Buffer BIT :=‘D’);
END der_flop;
Architecture structural OF der_f1op IS
Component flop IS
Generic (td_reset, tdjn: TIME := 8 NS);
PORT (reset, din, elk: IN BIT; qout: Buffer BIT :=E0J);
END component ;
Component mux2_1 IS
Generic (dz_delay: TIME := 6 NS);
PORT (selT datal, dataO: IN BIT; z: OUT BIT);
END component ;
Signal dfMn: BIT;
Begin
mx: mux2_1 port map (enable, din, qout, dff_in);
ff: flop port map (reset, dffjn, elk, qout);
END structural ;
Complete Design of Serial Adder
Subprograms
■ VHDL allows the use of functions and procedures
■ Most of high-level behavioral constructs in VHDL can
be used in body of functions and procedures
■ Subprograms can be declared, defined, and invoked as
in software languages
■ Functions can be used
• to represent Boolean equations H/W discr.
• for type conversions
• for delay value calculations description of nonfunctional
behavior
■ Procedures can be used for
* type conversion
• description of counters
Procedure Example
Type Byte ARRAY (7 Downto 0} of BIT;
Procedure byte_to_integer(ib: IN Byte; oi: OUT Integer) IS
Variable result: Integer :=0;
Begin
For UNO To 7 Loop
IF ib(l) = fV Then
result := result + 2**l;
END IF;
END Loop;
oi := result;
END byte_toJnteger;
Function Example
Entity fu I ladder IS
Port (a, b, cin: IN BIT; sum, cout: OUT BIT);
END fulladder;
Architecture behavioral OF fulladder IS
Function fadd{a, b, c : IN BIT) RETURN Bit_ Vector IS
variable sc: Bit_Vector{1 downto 0);
Begin
sc(1) := a XOR b XOR c;
sc(0) := (a AND b) OR (a AND c) OR (b AND c);
Return sc;
END; ,
array aggregate operation *
?
(sum, cout) <= fadd(a, b, cin);
END behavioral ;
Controller

program= data unit and control unit


control unit has control j/p & control o/p at interface
inside it is an state machine
state transitions= f(control i/p)
ex: sequence detector
Controller Description
■ Moore Sequence Detector
* Detection sequence is 110

x IF 110 found on x
Then Z gets *V
Else z gets ‘O’ z
elk End

1 1 1 o

0
VHDL Description of Moore 110 Sequence
Detector
ENTITY moore_110_detector IS
PORT (x, elk : IN BIT; z : OUT BIT);
END mo ore_110_d elector;
ARCHITECTURE behavioral OF moore 110 detector IS
TYPE state IS (reset, got1, got11r gol1107;
SIGNAL current : state := reset;
BEGIN
PROCESS(clk)
BEGIN
IF (elk = T AND CLKr Event) THEN
CASE current IS
WHEN reset =>
IF x = T1' THEN current <ÿ got1;
ELSE current <= reset; END IF;
WHEN got1 =>
HFx = T1' THEN current <= got11;
ELSE current <= reset; END IF;
WHEN got11 =>1
IF x = '1 THEN current got1 1;
ELSE current <= got110; END IF;
WHEN g[ot110=?
HFx = Tr THEN current <± got1;
ELSE current <* reset; END IF;
END CASE;
END IF-
END PROCESS;
z <='1‘WHEN current = got110 ELSE ‘0T;
END behavioral;
VHDL Objects ...
■ VHDL OBJECT : Something that can hold a value of a
given Data Type.
■ VHDL has 3 classes of objects
* CONSTANTS
• VARIABLES
* SIGNALS and file types
■ Every object & expression must unambiguously
belong to one named Data Type
m Every object must be Declared.
VHDL Object

Syntax

Obj_Closs <id_list> : Type/SubType \signa!_kind\ [:= expression];

Default Initial Vaiue


BUS Register (not Optional for Constant
Declarations)
Only Tor Signals
object of signal class
represents h/w wires
have timing associated
scheduling can be done by AFTER clause

object of variable class


do not represent any h/w
appear in sequential part
no timing associated

object of constant class


represent the constant value
can appear in concurrent or sequential part
value given can not be changed
... VHDL Object ...
■ Value of Constants must be specified when declared
■ Initial values of Variables or Signals maybe specified
when declared
■ If not explicitly specified, initiat values of Variables or
Signals default to the value of the Left Element in the
type range specified in the declaration.
■ Examples:
• Constant Rom_Size : Integer := 2**16;
• Constant Address_Field ; Integer := 7;
• Constant Ovfl_Msg : String (1 To 20) := "Accumulator Over Flow";
• Variable Busy, Active : Boolean := False;
• Variable Address : Bit_Vector (0 To Addre ss_ FieId) :=
"00000000";
■ Signal Reset; Bit;='0';
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Signal Assignments ...
■ Syntax:
Target Signal <= [ Transport ] Waveform ;
Waveform := Waveform_element {, Waveform_etement }
Waveform etement := VatueExpression [ After TimeExpression ]
■ Examples:
* X <= <01 ;; -- Assignment executed After 5 delay
* S<=T After 10 ns;
* Q <= Transport "1’ After 10 ns;
* S<=T After 5 ns, *0' After 10 ns, T After 15 ns;
■ Signal assignment statement
* mostly concurrent {within architecture bodies)
* can be sequential (within process body)
... Signal Assignments
■ Concurrent signal assignments are order independent
■ Sequential signal assignments are order dependent
■ Concurrent signal assignments are executed
* Once at the beginning of simulation
• Any time a signal on the right hand side changes
111 A Signal Has a 1- Current Value (CV), and
2- Projected Waveform (P_Wfm)
* A Waveform; Consists of a Set of Signal Transactions
* Signal Transaction = Pair (Value, Time)
f
Signal Value at Indicated Time Relative to Current Simulation Time
Decremented a? Simulation Time tnereasks
DELAY MECHANISM
Signal Transaction
■ When the time element of a signal transaction expires
(t=0)
• Its associated value is made the current value (CV) of a
signal
• The transaction is deleted from the list of transactions forming
the Projected Waveform (P_Wfm) of the signal
Signal Transaction & Event ...
■ When a new value is assigned to a signal, it is said that
• a Transaction has been Scheduled for this signal
• or a Transaction has been placed on this Signal Driver
■ A Transaction which does not cause a signal transition
(Event) is still a Transaction
■ A Transaction May/May not cause a signal transition
(Event) on the target signal

Transaction
... Signal Transaction & Event ...
■ A <= ‘1’ After 10 ns, ‘O’ After 20 ns, ‘V After 30 ns;

t=0 t=5 ns t=10 ns t=20 ns t=30 ns

A (CV) ‘01 0' *V O' *V

A (‘V, 10ns) {'1*, 5ns) {' 0\ 10ns) {*1’f 10ns)


(PWfm) ('0% 20ns) {[0\ 15ns) {T, 20ns)
HS 30ns) {‘1\ 25ns)
Signal Transaction & Event
ARCHITECTURE
demo OF example IS
SIGNAL a, b, c : BIT
:= 'O';
BEGIN
a <= T AFTER 15
NS;
b <= NOT a AFTER
5 NS;
c <= a AFTER 10 NS;
END demo;
Scope of Signal Declarations
■ Signals declared within a Package are Global usable by
all Entities using this package
■ Signals declared within an Entity are usable by all
architectural bodies of this entity
■ Signals declared within an Architectural body are only
usable within this Architectural body
Delta Delay in Sequential Signal
Assignments ...
■ Effect of 5-delay should be carefully considered when
signal assignments are embedded within a process

Entity BUFF2 IS
Port (X: IN BIT;
Z: OUT BIT);
END BUFF2;

Architecture Wrong of BUFF 2 IS


Signal y: BIT; * Process activated on x-events only
Begin
■ y <r x<S)
Process(x)

z <ÿ y{0)
Begin * z gets OLD value of y and not new
y <- value of x
z <= y;
End Process ;
End Wrong;
... Delta Delay in Sequential Signal
Assignments _

Architecture OK of BUFF2 tS
- Process activated on both x and y
Signet y: BIT;
events
Begin
Process{x;y) - x changes and process activated
Begin
■y fx; -y gets x value after 6
y<=x;
z<=y; -z y; — z gets y(0) value after 6
End Process ;
- Process terminated
End OK;
- After 5, y changes and process
activated

z gets new y {=x) after §

Process terminated
Oscillation in Zero Real Time

Architecture forever of Delta x y


oscillating IS +0 0 1
Signal x: BIT :=‘Q';
Signal y: BIT :=‘V; +1 1 1
Begin +2 1 0
x <£= y;
y <= NOTx; +3 0 0
End forever; +4 0 1
+5 1 1
+6 1 0
+7 0 0
+8 0 1
Sequential Placement of Transactions

Transport Inertial
New Transaction Overwrite Overwrite
is Before existing existing
Already Existing transaction transaction

New Transaction Append new


is After Already transaction
Existing

v
v new = v ,
w old
'= V0,d Vnew /= vold
Tnÿ'Toidÿ Reject TI,ew-Toldc= Reject
Append new
Append new Overwrite existing
transaction transaction
transaction
Example: Transport, New Transaction
Before Already Existing
ARCHITECTURE sequential OF
overwriting old IS
Type tit is ('O', ‘1 ‘Z’);
'
SIGNAL x : tit := Z';
BEGIN
PROCESS
BEGIN Discards previous
x<= 1' AFTER 5 NS; transaction
x <= Transport 'O’ AFTER 3 NS ;
WAIT;
END PROCESS;
END sequential;

x
Example: Transport, New Transaction
After Already Existing
ARCHITECTURE sequential OF
saving_all IS
Type tit is (‘O’, ‘1’, ‘Z’);
SIGNAL x : tit := Z';
BEGIN
PROCESS
BEGIN Appends
x<=1' AFTER 5 NS; transaction
x <= Transport ‘O' AFTER 8 NS;
WAIT;
END PROCESS;
END sequential;

x
1 r

HKMNH
—I—I—I—I T -
I
1
!— r—-
i
0

0123456 789
Example: Inertial, New Transaction
Before Already Existing_
ARCHITECTURE sequential OF
overwriting_old IS
Type tit is <'0‘, ‘V, ‘Z');
SIGNAL x : St := Z';
BEGIN
PROCESS
BEGIN Discards previous
x <= T AFTER 5 NS; transaction
x <= V AFTER 3 NS;
WAIT;
END PROCESS,-
END sequential;

0 1 2 3 4 5 6 7 8 9
Example: Inertial, New Transaction
After Already Existing (Same Value)
ARCHITECTURE sequential OF
saving ail IS
Type tit is ('O', ‘V, ‘Z’);
SIGNAL x : tit := Z';
BEGIN
PROCESS
BEGIN Saves previous
x <= ‘O' AFTER 5 NS; Transaction with
x<='0' AFTER 8 NS;
WAIT; Same value
END PROCESS;
END sequential;

0123456789
Example: Inertial, New Transaction After
Already Existing (Different Value)
ARCHITECTURE sequential OF
discarding_old IS
Type tit is ('O’, ‘V, ‘Z’);
SIGNAL x : tit := Z';
BEGIN
PROCESS
BEGIN Discards old
x <= ‘V AFTER 5 NS; value
x <= ‘O' AFTER 8 NS;
WAIT;
END PROCESS;
END sequential;

0123456 789 O 01
Example: Inertial, New Transaction After
Already Existing (Diff. Value with Reject)
ARCHITECTURE sequential OF
appending IS
Type tit is (‘O’, lV, lF);
SIGNAL x : tit F;
BEGIN
‘Time difference
PROCESS
between new and
BEGIN
existing transaction
x<= ‘1r AFTER 5 NS;
is greater than reject
x <= Reject 2 ns inertial ‘0‘ AFTER 8 NS;
value
WAIT;
END PROCESS;
-Appends transaction
END sequential;

X o
0123456789
Example: Inertial, New Transaction After
Already Existing (Diff. Value with Reject)
ARCHITECTURE sequential OF
appending IS
Type tit is (‘O’, l1\ ’T);
SIGNAL x : tit := Z';
BEGIN
PROCESS
-Time difference
between new and
BEGIN
existing transaction
x<= lV AFTER 5 NS;
is less than reject
x <= Reject 4 ns Inertial l0‘AFTER 8 NS;
value
WAIT;
-Discards old value
END PROCESS;
END sequential;

X z 0
0123456789
Signal Attributes...
■ Attributes are named characteristics of an Object (or
Type) which has a value that can be referenced.
■ Signal Attributes
-
* S' Event Is TRUE if Signal S has changed.

* S'Stable(t) Is TRUE if Signal S has not changed for the
last "t" period. If t=0; it is written as S' Stable
-
* S'Last_Value Returns the previous value of S before the
last change.

* S'Quiet(t)
--
* S' Active ** ** Is TRUE if Signal S has had a transaction in the
current simulation cycle.
Is TRUE if no transaction has been placed on
Signal S for the last ”t" period. If t=0; it is written as S'Quiet
* S'Last_Event ** Returns the amount of time since the last
value change on S.
...Signal Attributes
architecture ex of example is
signal a, a 5: bit; signal a1, a 2, a 3, Boo/ean,
jbeg/n
a <= V after 5 ns, 'V after 10 ns, 1’ after 15 ns, '0' after 20 ns;
a1 <= a'event;
al <- ars table;
a3 <= arstable(2 ns);
a4 <= a quiet;
35 <- ariast_valu9;
end ex;
Basic Components & Graphical
Notation
■ Three basic components are used
■ Will use as the basic components of several designs
■ A graphical notation helps clarify wiring
A Cascadable Single-Bit Comparator
■ When a > b the a_gt_b becomes 1
■ When a < b the a_lt_b becomes 1
■ If a = b outputs become the same as corresponding inputs

a>b a=b a<b


Structural Single-Bit Comparator
■ Design uses basic components
■ The less-than and greater-than outputs use the same logic

It 4-
b
Structural Single-Bit Comparator:
Aspect Notation_
Structural Model of Single-Bit
Comparator ...
ENTITY bit_comparator IS
PORT (a, bs gt, eq, It : IN BIT; a_gt_bf a_eq_b, a_lt_b : OUT BIT);
END bit_comparator;
ARCHITECTURE gatejevel OF bit_comparator IS

COMPONENT n1 PORT (i1: IN BIT; o1: OUT BIT); END COMPONENT ;


COMPONENT n2 PORT (i1J2: IN BIT; o1:OUT BIT); END COMPONENT;
COMPONENT n3 PORT (i1, i2, i3: IN BIT; o1: OUT BIT); END COMPONENT;
- Component Configuration
FOR ALL : n1 USE ENTITY WORK.inv (single_delay);
FOR ALL : n2 USE ENTITY WORK.nand2 (single_delay);
FOR ALL : n3 USE ENTITY WORK.nand3 (single_delay);
—Interm edia te s ig rials
SIGNAL im1,im2, im3, im4# im5, im6, im7, im8, im9t im10 : BIT;
...Structural Model of Single-Bit
Comparator
BEGIN
-a gt_b output
gO : n1 PORT MAP (a, im1);
g1 : n1 PORT MAP (b, im2);
g2 : n2 PORT MAP (a, im2, im3);
g3 : n2 PORT MAP (a, gt, im4);
g4 : n2 PORT MAP (Im2, gt, im5);
g5 : n3 PORT MAP (im3, im4, imS, a gt b);
- s_eq_b output
g6 : n3 PORT MAP (iml, im2, eq, im6);
g7 : n3 PORT MAP (a, b, eq, im7);
g8 : n2 PORT MAP (im6, im7, a_eq_b);
-ajt_b output
g9 : n2 PORT MAP (im1, b, imS);
g10 : n2 PORT MAP It, im9>;
g11 : nZ PORT MAP {b, It, im10);
g12 : n3 PORT MAP {imS, im9, im10, a_lt_b);
END gatejevel;
Netlist Description of Single-Bit
Comparator
ARCHITECTURE netlist OF bit_comparator IS
SIGNAL im1,im2, im3, im4, im5, im6, im7, im8, imS, im10 : BIT;
BEGIN
— a gt b output
g£) : ENTITY Work.inv(single_delay) PORT MAP (a, im1);
g1 : ENTITY Work.inv(s ingle delay) PORT MAP {b, im2);
g2 : ENTITY Work.nand2(single_delay) PORT MAP (a, im2, im3);
g3 : ENTITY Work.nand2(single delay) PORT MAP (a, gt, im4);
g4 : ENTITY Work.nand2(single_delay) PORT MAP (im2, gt, im5);
g5 : ENTITY Work.nand3(single_delay) PORT MAP (im3, im4, imS, a_gt_b);
— a_eq_b output
g6 : ENTITY Work.nand3(single_delay) PORT MAP (im1, im2, eq, im6);
g7 : ENTITY Work.nand3(single_delay) PORT MAP (a, b, eqT im7);
g8 : ENTITY Work.nand2(single_delay) PORT MAP (im6, im7, a_eq_b);
3_tt_b output
-ÿ

g9 : ENTITY Work.nand2(single_delay) PORT MAP (im1, bT imS);


g10 : ENTITY Work.nand2(single_delay) PORT MAP (im1, It, im9);
g11 : ENTITY Work. nand2(single_delay) PORT MAP {b, It, im10);
g12 : ENTITY Work. nand3(single_delay) PORT MAP (im8, im9, im10, a_lt_b);
END netlist;
4-Bit Comparator Structural Iterative
Wiring
Four Bft Comparator
4
<Jata A
4 A>0
inputs — — B
Pom pare
A-B
□LTtpLJtS
Control
inputs A<B
<
4-Bit Comparator Aspect Notation
■ Aspect notation shows
VHDL wiring
■ VHDL description will use
same intermediate signal
names
Syntax of Generate Statement

■Generate statement is a concurrent statement


■Generate statement brackets concurrent statements
4-Bit Comparator: “For
Generate” Statement ...
ENTITY nibble_comparator IS
PORT (a, b : IN BIT_VECTOR (3 DOWNTO 0); - a and b data inputs
gt, eq, It: IN BIT; -- previous greater, equal & less than
a_gt_b, a_eq_b, a_lt_b : OUT BIT); « a > b, a = b, a < b
END nibble_comparator;

ARCHITECTURE iterative OF nibblle_com parator IS

COMPONENT compl
PORT (a, b, gt, eq, It : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
FOR ALL : compl USE ENTITY WORK.bit_comparator (gatejevel);
SIGNAL im : BIT_VECTOR ( 0 TO 8);
BEGIN

cO: compl PORT MAP (a(0), b(0), gt, eq, It, im(0), im(1), im(2));
... 4-Bit Comparator: “For
Generate” Statement
c1to2: FOR i IN 1 TO 2 GENERATE

c: compl PORT MAP ( a{i), b(i), im(i*3-3), im{i*3-2), im(i*3-1),


im{i*3+0), im(i*3+1), im(i*3+2) );

END GENERATE;
c3: compl PORT MAP (a(3), b{3), im(6), im(7), im(8), a_gt_b,
a_eq_b, a_lt_b);

END iterative;

■USE BIT_VECTOR for Ports a & b


■Separate first and last bit-slices from others
■Arrays FOR intermediate signals facilitate iterative wiring
■Can easily expand to an n-bit comparator
Structural Test Bench
■ A Testbench is an Entity
without Ports that has a
Structural Architecture
■ The Testbench Architecture,
in general, has 3 major
components:
• Instance of the Entity Under
Test (EUT)
♦ Test Pattern Generator
(
Generates Test Inputs for the
Input Ports of the EUT)
• Response Evaluator
{Compares the EUT Output
Signals to the Expected
Correct Output)
Testbench Example ...
Entity nibble_comparator_test_bench IS
End nibble_comparator_test_bench ;

ARCHITECTURE input output OF nibblecomparatortestbench IS

COMPONENT comp4 PORT (a, b : IN bit_vector (3 DOWNTO 0);


gt, eq, It : IN BIT;
agtb, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;

FOR a1 : comp4 USE ENTITY WORK.nibblecomparator(iterative);

SIGNAL a, b : BIT_VECTOR (3 DOWNTO 0);


SIGNAL eql, Iss, gtr, gnd : BIT;
SIGNAL vdd : BIT := T;

BEGIN
a1: comp4 PORT MAP (a, b5 gnd, vdd, gnd, gtr, eql, Iss);:
Testbench Example
B2\ a <= "0000", - a = b (steady state)
"1111" AFTER 0500 NS, - a > b (worst case)
"1110" AFTER 1500 NS, - a < b (worst case)
"1110" AFTER 2500 NS, - a > b (need bit 1 info)
"1010" AFTER 3500 NS, - a < b (need bit 2 info)
"0000" AFTER 4000 NS, - a < b (steady state, prepare FOR next)
"1111" AFTER 4500 NS, - a = b (worst case)
"0000" AFTER 5000 NS, - a < b (need bit 3 only, best case)
"0000" AFTER 5500 NS, - a = b (worst case)
"1111" AFTER 6000 NS; - a > b (need bit 3 only, best case)

a3 : b <= "0000", -- a = b (steady state)


"1110" AFTER 0500 NS, - a > b (worst case)
"1111" AFTER 1500 NS, - a < b (worst case)
"1100" AFTER 2500 NS, - a > b (need bit 1 info)
"1100" AFTER 3500 NS, - a < b (need bit 2 info)
"1101" AFTER 4000 NS, - a < b (steady state, prepare FOR next)
"1111" AFTER 4500 NS, - a = b (worst case)
"1110" AFTER 5000 NS, - a < b (need bit 3 only, best case)
"0000" AFTER 5500 NS, - a = b (worst case)
"1110" AFTER 6000 NS; - a > b (need bit 3 only, best case)
END inputoutput;
Different Binding Schemes

Entity srjatch IS USE 4 2-Input NAND gates


Port (S, R, C : IN Bit; q : Out Bit); to design an SR latch
END srjatch;

ARCHITECTURE Wrong OF srjatch IS


COMPONENT n2 t

PORT (i1, I2: IN BIT; o1: OUT BIT);


END COMPONENT;
r

FOR ALL : n2 USE ENTITY WORK.nand2 | ingle_delay);

SIGNAL im1, im2, im4 : BIT;

BEGIN
g1 : n2 PORT MAP (s, c, im1);
g2 : n2 PORT MAP (r, ct im2);
g3 : n2 PORT MAP (Im1s im4, q);
g4 : n2 PORT MAP (q, im2, im4); -- Error ... q declared as Output
END Wrong; 2-23
SR Latch Modeling .

Fix #1 (Same Architecture — Change mode of q to Inout)


Entity sr_latch IS
Port (S, R, C : IN Bit; q : tnOut Bit);
END sr latch;

Fix #2 (Same Architecture — Change mode of q to Buffer)


Entity sr latch IS
Port (S, R, C : IN Bit; q : Buffer Bit);
END srjatch;
SR Latch Modeling
Fix #3 (Use Local Signal Mode of q is maintained as Out)

ARCHITECTURE Problem OF srjatch IS


COMPONENT n2
PORT 01, i2: IN BIT; o1: OUT BIT);
END COMPONENT;
FOR ALL : n2 USE ENTITY WORK.nard2 (single_delay);
SIGNAL im1, im2, im3, im4 : BIT;
BEGIN
g1 :n2 PORT MAP (s, c, im1);
g2 : n2 PORT MAP (r, c, im2);
g3 : n2 PORT MAP (im1, im4, im3);
g4 : n2 PORT MAP 0m3, im2, im4);
q <= im3;
END Problem;

•Correct Syntax Problem Oscillating


•If all delays are equal then (0,0) on (q, qbar) will oscillate clk=0
•Remedy by using gates of different delay values
2-25
SR Latch Modeling
ARCHITECTURE fast_single_delay OF nand2 IS
BEGIN
o1 <=i1 NAND i2 AFTER 1 NS;
END fastsinglcdclay:

ARCHITECTURE gateÿLevel OF srjatch IS


COMPONENT n2
PORT (H, i2: IN BIT; of: OUT BIT);
END COMPONENT;
FOR g1, g3 : n2 USE ENTITY WORK.nand2 (fast_single_delay);
FOR g2, g4 : n2 USE ENTITY W0RK.nand2 (single_deiay);
SIGNAL im1, im2, im3, im4 : BIT;
BEGIN
g1 : n2 PORT MAP (s. c, im1);
g2 : n2 PORT MAP (r, c, im2);
g3 : n2 PORT MAP (im1, im4, im3);
g4 : n2 PORT MAP (im3, im2, im4);
q <= im3;
END gate Level:
Binding 3-Input NAND Entity (Different
De/ay) to 2-Input “NAND” Component
ARCHITECTURE gatejevel OF srjatch fS
COMPONENT n2
PORT (x, y: in BIT; z: out BIT);
END COMPONENT;
FOR g17 g3 : n2 USE ENTITY W0RK.nand2
(singlejdetay) PORT MAP (x, y, z);
FOR g2, g4 : n2 USE ENTITY WORK.nand3
{singie delay) PORT MAP (x, x, yf z);
SIGNAL im1, im2, im3, im4 : BIT;
BEGIN
g1 : n2 PORT MAP (s, c, Im1);
g2 : n2 PORT MAP (rf c7 im2);
g3 : n2 PORT MAP (im1, im4 im3);
7

g4 : n2 PORT MAP (Im3, im27 im4 );


q <= im3;
END gatejevel;
Port Map Association

Signals of Instance Actual Signals


galaJewel of im2
srjatch Port map association
of instantiation
Local ports statement
y
of g2 instance z
of n2

Formal
ports of nand3 in3 01
Port Map Association
■ Association is done in two steps:
■ Instance-To-Component
(Actuals Component Local Ports)
■ Componenet-To-Entity (Configuration Port Map)
(Component Local Ports Entity Formal Ports)
• Specifying PORT MAP in Configuration Statements is
Optional

• To Override Component Local Port Names, USE PORT MAP


in configuration declaration
• IF No Port Map is Specified in Configuration Statement, Local
Port Names of COMPONENT declaration are the Default
Default Binding
■ Default Binding: Component instance is Bound to an
Entity which:
* Has the same NAME as the Component
* Has the same number of Ports as the Component
* Ports must have the Same Type and be of Compatible modes
* The most Recently analyzed Architecture will Be used
* A declared Signal can be associated with A Formal Port of Any Mode as
long as it has the Same Type
■ Port Compatibility: Formal => Actual
Actual's Mode (Instance Ports)

IN OUT INOUT BUFFER


IN X X
Format s Mode OUT X X
Entity Format Ports
INOUT X
BUFFER X
Sequential Comparator ...
■ Compare consecutive sets of data on an 8-bit input
bus.
■ Data on the input bus are synchronized with a clock
signal (new value on falling edge of clock)

-A+
-
□Id

comparator
bytejatch

Data new
7
.g
-
k.
D-Latch
ENTITY djatch IS
PORT (d, c : IN BIT; q: OUT BIT);
END djatch;

ARCHITECTURE sr_based OF djatch IS


COMPONENT srjatch
PORT (s, r, C : IN BIT; q : OUT BIT);
END COMPONENT;
COMPONENT inv
PORT (i1 : IN BIT; o1 : OUT BIT);
END COMPONENT;
SIGNAL dbar: BIT;
BEGIN
c1 : srjatch PORT MAP {d, dbar, c, q);
c2 : inv PORT MAP (d, dbar);
END sr_based;
2-
Range Attributes

If A is a constrained array object then

* A'RANGE (N): returns the Nth index range of A (N=l, if not specified).
* A'REVERSE.RANGE(N): returns the Nth index range reversed.

For example* if

variable WBUS: MVL_VECT0R(7 downto 0);

then
WBUS'RANGE returns the range "7 downto 0" (quotations not included)

while

WBUS REVERSE_RANGE returns the range "0 to 7".


Byte Latch

ENTITY bytejatch IS
PORT ( di : IN BIT_VECTOR (7 DOWNTO 0); elk : IN BIT; qo : OUT
BIT_VECTOR( 7 DOWNTO 0));
END bytejatch;

ARCHITECTURE iterative OF bytejatch IS


COMPONENT djatch
PORT (d, c : IN BIT; q : OUT BIT);
END COMPONENT;
BEGIN
g : FOR i IN di'RANGE GENERATE
L7DT0 : djatch PORT MAP (di(i), elk, qo{i));
END GENERATE;
END iterative;
Sequential Comparator
ENTITY old_new_comparator IS
PORT (i : IN BIT_ VECTOR (7 DOWNTO 0);
elk : IN BIT; compare : OUT BIT);
END old_new_comparator; A
r
"old
ARCHITECTURE wiring Of oldnewcomparator IS comparalor
bylejalch
COMPONENT bytejatch PORT (di : IN
BITJVECTOR (7 DOWNTO 0); elk : IN BIT; Data , f:
TEW
7 ’
qo : OUT BlT_VECTOR (7 DOWNTO 0));
END COMPONENT;
COMPONENT byte_comparator
PORT {a, b : BIT_ VECTOR (7 DOWNTO 0);
gt, eq, It : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
SIGNAL coni : BIT_VECTOR {7 DOWNTO 0);
SIGNAL vdd : BIT := T;
SIGNAL gnd : BIT:= *0*;
■■ ■ Sequential Comparator
BEGIN
I : bytejatch PORT MAP (i, elk, coni);
c : byte_comparator
PORT MAP (coni, i, gnd, vdd, gnd, OPEN, compare, OPEN);
END wiring;

Con 1

i
Subprograms...
■ Subprograms consist of functions and procedures.
■ Subprograms are used to
• Simplify coding,
* Achieve modularity,
* Improve readability.
■ Functions return values and cannot alter values of
their parameters.
■ Procedures used as a statement and can alter values
of their parameters.
■ All statements inside a subprogram are sequential.
...Subprograms
■ Subprograms
• Concurrent
• Sequential
■ Concurrent subprograms exist outside of a process or
another subprogram.
■ Sequential subprograms exist in a process statement
or another subprogram.
■ A procedure exists as a separate statement in
architecture or process.
■ A function usually used in assignment statement or
expression.
Functions
■ Function specification:
• Name of the function
• Formal parameters of the function
* Class constant is default
* Name of the parameter
• Mode IN is default & only allowed mode
• Type of the parameter
• Return type of the function
• Local declarations
■ A function body
• Must contain at least one return statement
• May not contain a wait statement
A Left-Shift Function

Subtype Byte IS Bit_Vector (7 Downto 0);


Function SLL (V: Byte; N: Natural; Fill: Bit) Return Byte IS
Variable Result: Byte := V;
Begin
For I IN 1 To N Loop
Result := Result (6 Downto 0) & Fill;
End Loop;
Return Result;
End SLL;
Using the Function
Architecture Functional Of LeftShifter IS
Subtype Byte IS Bit_Vector (7 Downto 0);
Function SLL (V: Byte; N: Natural; Fill: Bit) Return Byte is
Variable Result: Byte := V;
Begin
For I IN 1 To N Loop
Result := Result (6 Downto 0) & Fill;
End Loop;
Return Result;
End SLL;

Begin
Sout <= SLL(Sin, 1, 01) After 12 ns;
End Functional;
A Single-Bit Comparator
Entity Bit_Comparator IS
Port ( a, b, -- data inputs
gt. -- previous greater than
eq, -- previous equal
It: IN BIT; -- previous less than
a_gt_b, - greater
a_eq_b, -- equal
a_lt_b: OUT BIT); - less than
End Bit_Comparator;
a_9t_b = a . gt + b' . gt + a . b'
a_eq_b = a . b . eq + a' . b' . eq
a It b = b . It + a' . It + b . a'
A Single-Bit Comparator using
Functions
Architecture Functional of Bit_Comparator IS
Function fgl (w, x, gl: BIT) Return BIT IS
Begin
Return (w AND gl) OR (NOT x AND gl) OR (w AND NOT x);
End fgl;
Function feq (w, x, eq: BIT) Return BIT IS
Begin
Return (w AND x AND eq) OR (NOT w AND NOT x AND eq);
End feq;
Begin
a_gt_b <= fgl (a, b, gt) after 12 ns;
a_eq_b <= feq (a, b, eq) after 12 ns;
a_lt_b <= fgl (b, a, It) after 12 ns;
End Functional;
Binary to Integer Conversion Function

Function Tojnteger (Bin : BIT VECTOR) Return Integer IS


Variable Result: Integer;
Begin
Result := 0;
Fori IN Bin' RANGE Loop
If Bin(l) = ‘V then
Result := Result + 2**l;
End if;
End Loop;
Return Result;
End Tojnteger;
Execution of a Function
■ Actual parameters are evaluated.
■ Actuals are associated with their formals.
■ Sequential statements are executed in order.
■ Function exits when a return statement is executed.
■ Return must supply a value of the return type.
■ Direct and indirect recursion is allowed.
■ Argument modification is not allowed.
■ Execution of a wait statement is not allowed.
Procedure Specification
■ Name of the procedure
■ Formal parameters of the procedure
• Class of the parameter
• optional
* defaults to constant
• Name of the parameter
• Mode of the parameter
• optional
* defaults to IN
• Type of the parameter
■ Local declarations
A Left-Shift Procedure

Subtype Byte is Bit_Vector (7 downto 0);


Procedure SLL (Signal Vin : In Byte; Signal Vout :out
Byte; N: Natural; Fill: Bit;
ShiftTime: Time) IS
Variable Temp: Byte := Vin;
Begin
For I IN 1 To N Loop
Temp := Temp (6 downto 0) & Fill;
End Loop;
Vout <= Temp after N * ShiftTime;
End SLL;
4-12
Using the Procedure
Architecture Procedural of LeftShifter is
Subtype Byte is BitVector (7 downto 0);;
Procedure SLL (Signal Vin : In Byte; Signal Vout :out Byte; I: Natural;
Fill: Bit; ShiftTime: Time) IS
Variable Temp: Byte := Vin;
Begin
For I IN 1 ToN Loop
Temp := Temp (6 downto 0) & Fill;
End Loop;
Vout <= Temp after N * ShiftTime;
End SLL;
Begin
Process (Sin)
Begin
SLLfSin, Sout, 1, ‘0*, 12 ns);
End process;;
4’
End Procedural;
Binary to Integer Conversion
Procedure
Procedure Bin2lnt (Bin : IN BIT_VECTOR; Int: OUT Integer) IS
Variable Result: Integer;
Begin
Result := 0;
For I IN Bin' RANGE Loop
If Bin(l) = ‘1’ Then
Result := Result + 2**l;
End If;
End Loop;
Int := Result;
End Bin2lnt;
Integer to Binary Conversion
Procedure
Procedure lnt2Bin (Int: IN Integer; Bin : OUT BIT_VECTOR} IS
Variable Tmp: Integer;
Begin
Tmp := Int;
For I IN 0 To (Bin' Length - 1) Loop
If (Tmp MOD 2 = 1) Then
Bin(l) :*“T;
Else Bin(l) := ‘O’;
End If;
Tmp := Tmp 12;
End Loop;
End lnt2Bin;
Using Procedures in a Test Bench ...
Architecture Procedural of Nibble_Comparator_Test IS
Component Comp4 Port (a, b: IN Bit_Vector(3 Downto 0);
gt, eq, It: IN Bit;
a_gt_b, a_eq_b, a_lt_b: OUT BIT);
End Component;
Signal a, b: Bit_Vector (3 downto 0);
Signal eql, gtr, Ise: BIT;
Signal Vdd: BIT := ‘1’;
Signal GND: BIT :=
Type Integers IS Array (0 to 5) of Integer;
Procedure Apply_Data (
Signal Target: OUT Bit_Vector (3 Downto 0);
Constant Values: IN Integers;
Constant Period: IN Time) IS
Variable Buf: Bit Vector (3 Downto 0);
Using Procedures in a Test Bench

Begin
For I IN 0 To 5 Loop
lnt2Bin (Values(l), Buf);
Target <ÿ Transport Buf After I * Period;
End Loop;
End Apply_Data;
Begin
a1: Comp4 Port Map {a, b, GND, Vdd, GND, gtr, eql, Iss);
Apply Data (a, 00&1S&14&12&10&01, 500 ns);
Apply_Data (b, 00&14&15&06&10&02, 500 ns);
End Procedural;
Executing a Procedure
■ Actual parameters are evaluated.
■ Actuals are associated with their formals.
■ Sequential statements are executed in order.
■ Procedure exits when
• End of the procedure is reached

■ Direct and indirect recursion is allowed.


■ Argument modification is allowed.
■ Execution of a wait statement is allowed.
Packages...
■ A package is a common storage area used to hold data
to be shared among a number of entities.
■ Packages can encapsulate subprograms to be shared.
■ A package consists of
• Declaration section
• Body section
■ The package declaration section contains subprogram
declarations, not bodies.
■ The package body contains the subprograms’ bodies.
■ The package declaration defines the interface for the
package.
Package Declaration
■ The package declaration section can contain:
• Subprogram declaration
• Type, subtype declaration
• Constant, deferred constant declaration
• Signal declaration creates a global signal
• File declaration
• Component declaration
• Attribute declaration, a user-defined attribute
• Attribute specification
• Use clause
Package Body
■ The package body main purpose is
• Define the values of deferred constants
• Specify the subprogram bodies for subprograms declared in
the package declaration
■ The package body can also contain:
• Subprogram declaration
• Subprogram body
• Type, subtype declaration
• Constant declaration, which fills in the value for deferred
constants
• File declaration
• Alias declaration
• Use clause
Package Example for Component
Declaration ...
Package simplegates is
COMPONENT n1 PORT (II : IN BIT; Ol : OUT BIT); END COMPONENT ;
COMPONENT n2 PORT (11,12: IN BIT;o1:OUT BIT); END COMPONENT;
COMPONENT n3 PORT (II, 12, i3: IN BIT; o1: OUT BIT); END COMPONENT:
end simple gates;

Use work.simple_gates.all;
ENTITY blt_comparator IS
PORT (a, b, gt, eg, It : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END bit_comparator;
ARCHITECTURE gatejevel OF b IS
FOR ALL : n1 USE ENTITY WORK.inv (single_delay);
FOR ALL : n2 USE ENTITY WORK.nand2 (Single_delay);
FOR ALL : n3 USE ENTITY WORK.nand3 (Singledelay);
■■Intermediate signals
SIGNAL im1,lm2, im3, im4, imS, ImB, imT, Im8, im3, im10 : BIT;
BEGIN
— description of architecture
END gatejevel;
... Package Example for Component
Declaration

USE WORK.simple_gates.ALL ;
- is equaivatent to:
USE
WORK.simple gates.n1 ,
WORK.simpie_gates.n2 ,
WORK.simpie_gates.n3 ;
- n1, n2 and n3 component declarations are visibie
Package Example

Package Shifters IS
Subtype Byte IS Bit Vector (7 Downto 0);
Function SLL (V: Byte; N: Natural; Fill: Bit := ‘0’) Return Byte;
Function SRL (V: Byte; N: Natural; Fill: Bit := ‘0’) Return Byte;
Function SLA (V: Byte; N: Natural; Fill: Bit := ‘0’) Return Byte;
Function SRA (V: Byte; N: Natural) Return Byte;
Function RLL (V: Byte; N: Natural) Return Byte;
Function RRL (V: Byte; N: Natural) Return Byte;
End Shifters;
Package Example
Package Body Shifters IS
Function SLL (V: Byte; N: Natural; Fill: Bit) Return Byte is
Variable Result: Byte := V;
Begin

For I IN 1 To N Loop
Result := Result {6 Downto 0) & Fill;
End Loop;
Return Result;
End SLL;

End Shifters;
Package Example

USE WORK.Shifters .ALL


Architecture Functional of LeftShifter IS
Begin
Sout <= SLL(Sin, 1, ‘0’) After 12 ns;
End Functional;
Another Package Example...
Package Basic_Utilities IS
Type Integers IS Array (0 to 5) of Integer;
Function fgl (w, x, gl: BIT) Return BIT;
Function feq (w, x, eq: BIT) Return BIT;
Procedure Bin2lnt (Bin : IN BIT_VECTOR; Int: OUT Integer);
Procedure lnt2Bin (Int: IN Integer; Bin : OUT BIT_VECTOR);
Procedure Apply_Data (
Signal Target: OUT Bit_Vector (3 Downto 0);
Constant Values: IN Integers;
Constant Period: IN Time);
Function To_lnteger (Bin : BIT_VECTOR) Return Integer;

End BasicJJtilities;
...Another Package Example...
Package Body Basic_lltilities IS
Function fgl (w, x, gl: BIT) Return BIT IS
Begin
Return (w AND gl) OR (NOT x AND gl) OR (w AND NOT x);
End fgl;
Function feq (w, x, eq: BIT) Return BIT IS
Begin
Return (w AND x AND eq) OR (NOT w AND NOT x AND eq);
End feq;

End BasiicJJtilities;
...Another Package Example

USE WORK.Basic_Utilities.ALL
Architecture Functional of Bit_Comparator IS
Begin
a_gt_b <=fgl (a, b, gt) after 12 ns;
a_eq_b <= feq (a, b, eq) after 12 ns;
a_lt_b <= fgl (b, a, It) after 12 ns;
End Functional;
Design Libraries...
■ VHDL supports the use of design libraries for
categorizing components or utilities.
■ Applications of libraries include
• Sharing of components between designers
• Grouping components of standard logic families
• Categorizing special-purpose utilities such as subprograms or
types
■ Two Types of Libraries
• Working Library (WORK) f A Predefined library into which a
Design Unit is Placed after Compilation.},
• Resource Libraries {Contain design units that can be
referenced within the design unit being compiled}.
... Design Libraries...
■ Only one library can be the Working library
■ Any number of Resource Libraries may be used by a
Design Entity
■ There is a number of predefined Resource Libraries
■ The Library clause is used to make a given library visible
■ The Use clause causes Package Declarations within a
Library to be visible
■ Library management tasks, e.g. Creation or Deletion, are
not part of the VHDL Language Standard -> Tool
Dependent
... Design Libraries...
■ Exiting libraries
• STD Library
* Contains the STANDARD and TEXTIO packages (See Appendix
F in the Textbook).
* Contains all the standard types & utilities
* Visible to all designs
• WORK library
* Root library for the user
■ IEEE library
• Contains VHDL-related standards
• Contains the std_logic_1164 (IEEE 1164.1) package
* Defines a nine values logic system
...Design Libraries
■ To make a library visible to a design
• LIBRARY libname;
■ The following statement is assumed by all designs
• LIBRARY WORK;
■ To use the std_logic_1164 package
• LIBRARY IEEE
• USE IEEE.std_logic_1164.ALL
■ By default, every design unit is assumed to contain the
following declarations:
•LIBRARY STD, work;
• USE STD.Standard.All ;
Standard Package...
■ Defines primitive types, subtypes, and functions.
■ The package STANDARD is usually integrated directly
in the simulation or synthesis program.
■ It contains all basic types: Boolean, bit, bit_vector,
character, integer, and the like.
■ Additional logical, comparison and arithmetic
operators are defined for these types within the
package.
■ The package STANDARD does not have to be explicitly
included by the use statement.
..Standard Package

Package Standard IS
Type Boolean IS (false, true);
Type Bit is ( O’, ‘1’);
Type Character IS ( nul, soh, stx,
Type Sensitivityjevel IS (Note, Warning, Error, Failure);
Type Integer IS Range -2147483648 to 2147483647;
Type Real IS Range -1.0E308 to 1.0E308;
Subtype Natural IS Integer Range 0 to Integer'High;
Subtype Positive IS Integer Range 1 to Integer'High;
Type String IS Array (positive Range <>) of Character;
...Standard Package
Type Bit_Vector IS Array (Natural Range <>) of Bit;
Type Time IS Range -2147483647 to 2147483647
Units
fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000
us; sec - 1000 ms; min - 60 sec; hr - 60 min;
End Units;
Subtype Delay length IS Time Range 0 fs to Time' High;

End Standard;
TEXTIO Package...
■ Defines types, procedures, and functions for standard
text I/O from ASCII files.
■ This package is also a part of the library STD.
■ It is not included in every VHDL description by default.
■ Therefore, if required, it has to be included by the
statement USE STD.TEXTIO.all;.
Syntax of Generic Statement
■ GENERIC clause has syntax similar to PORT clause
■ Interface CONSTANT declaration
Design Parameterization
■ GENERICs can pass design parameters
■ GENERICs can include default values
■ New versions of gate descriptions contain timing

ENTITY inv_t IS
GENERIC (tplh : TIME := 3 NS; tphl : TIME := 5 NS);
PORT 01 : in BIT; o1 : out BIT);
END inv_t;

ARCHITECTURE average delay OF inv tIS


BEGIN
o1 <= NOTH AFTER (tplh + tphl)/ 2;
END average_delay;
Design Parameterization

ENTITY nand2_t IS ENTITY nand3_t IS


GENERIC (tplh : TIME := 4 NS; GENERIC (tplh : TIME := 5 NS;
tphl : TIME := 6 NS); tphl : TIME := 7 NS);
PORT (H, i2 : IN BIT; o1 : OUT PORT (i1, \2, /3 : IN BIT; o1 ;
BIT); OUT BIT);
END nand2_t; END nand3_t;

ARCHITECTURE average_delay ARCHITECTURE av&rage_delay


OF nand2_t IS OF nand3_t IS
BEGIN BEGIN
o1 <= 11 NAND i2 AFTER (tplh + o1 <=NOT( i1 AND i2 AND i3 )
tphl)/ 2; AFTER (tplh + tphl) / 2;
END averagejdeiay; END average_delay;
Values Passed to Generic Parameters
■ Several alternatives for passing values to GENERICs
• Using defaults
• Assigning fixed values
• Passing values from higher level components
• Configuring designs
Using Default values
ARCHITECTURE default_delay OF bit_comparator IS
Component n1 PORT{i1~IN BIT; o1: OUT BIT);
END Component;
Component n2 PORT fi1, 12: IN BIT; ol: OUT Bll VO Gentries Specified in
J

END Component; Component Declarations


Component n3 PORT {M, 12> 13: IN BIT; ol: OUT
END Component;
FOR ALL : n1 USE ENTITY WORK.in*_t faverage_delay);
FOR ALL : n2 USE ENTITY VYGRK.nand2J {average_delay);
FOR ALL : n3 USE ENTITY WQRK,nand3_t {average_delay);
- Intermediate signals
SIGNAL im1,im2. im3, im4, im5: im6: im7, ImS, im9; im10 : BIT;
BEGIN
"a_9Lb output
* Component declarations do not contain GENERICs
gO : n1 PORT MAP (a, im1);
• Component instantiation are as before
gl : n1 PORT MAP (b, im2);
g2 : n2 PORT MAP (a, im2, im3 •If default values exist, they are used
g3 : n2 PORT MAP (a, gt, im4);
g4 : n2 PORT MAP (im2, gt, imS);
g5 : n3 PORT MAP (im3, 11114, imS, a_gt_b);
Assigning Fixed Values to Generic
Parameters ...
ARCHITECTURE fixedjdelay OF bit_comparator IS
Component n1
Generic {tplh, tphl : Time); Port {II: in Bit; o1: out Bit);
END Component;
Component n2
Generic (tplh, tphl : Time); Port{i1, i2: in Bit; o1: out Bit);
END Component;
Component n3
Generic (tplh, tphl : Time); Port (M, 12, 13: In Bit; o1: out Bit);
END Component;
FOR ALL : n1 USE ENTITY WORK.inv_t (averageÿdelay);
FOR ALL : n2 USE ENTITY WORK.nand2J (average_delay);
FOR ALL : n3 USE ENTITY WORK.nand3_t (average_delay);
— Intermediate signals
SIGNAL im1,im2, im3, im4, im5, im6, im7, imB, im9, im10 : BIT;
BEGIN
- a_gt_b output
gO ~nfGeneric Map (2 NS, 4 NS) Port Map fa, im1);
g1 : n1 Generic Map (2 NS, 4 NS) Port Map fb, lm2);
g2 : n2 Generic Map (3 NS, 5 NS) Port Map (a, im2, im3);
... Assigning Fixed Values to Generic
Parameters
g3 : n2 Generic Map (3 NS, 5 NS) Pert Map P (a, gt, im4);
g4 : n2 Generic Map (3 NS, 5 NS) Pert Map (im2, gt, im5);
g5 : n3 Generic Map (4 NS, E NS) Pert Map (im3, im4 Im5, a_gt_b);
— a_eq_b output
g6 : n3 Generic Map (4 NS, 6 NS) Pert Map (im1, im2, eg, im6);
g7 : n3 Generic Map (4 NS, 6 NS) PORT MAP (a, b, eq, im7);
gS : n2 Generic Map (3 NS, 5 NS) PORT MAP (im6, Im7, a_eq_b);
— a_lt_b output
g9 : n2 Generic Map (3 NS, 5 NS) Port Map (im1, b, imB);
g10 : n2 Generic Map (3 NS, S NS) PORT MAP (im1, It, im9);
g 11 : n2 Generic Map (3 NS, S NS) PORT MAP (b, It, ImlO);
g12 : n3 Generic Map (4 NS, 6 NS) PORT MAP (imS, im9, im10, a_lt_b);
END fixed delay;

Component declarations contain GENERICs


Component instantiation contain GENERIC Values
GENERIC Values overwrite default values
Passing Values From Higher Level Specs

•To pass values, upper level units must contain GENERtCs


•A timed bit comparator is developed
... Passing Values From Higher Level

ARCHITECTURE passed_defay OF bit_comparator_t IS


Component nl
Generic {tplh, tphl : Time); Port (II: In Bit; o1: out Bit);
END Component;
Component n2
Generic (tplh, tphl : Time); Port{i1, 12: in Bit; o1: out Bit);
END Component;
Component n3
Generic (tplh, tphl : Time); Port (M, 12, 13: in Bit; o1: out Bit);
END Component;
FOR ALL : nl USE ENTITY WORK.inv_t (average jjel ay);
FOR ALL : n2 USE ENTITY WORK.nand2J (average_delay);
FOR ALL : n3 USE ENTITY WORK.nand3J (average_delay);
— Intermediate signals
SIGNAL im1 Jm2, im3, im4, im5, im6, Im7, imG, im9, lm10 : BIT;
BEGIN
- a_gt_b output
gO : n1 Generic Map {tplh1 , tphll j Port Map (a, im1);
g1 : n1 Generic Map (tplhl, tphH) Port Map (b, im2);
g2 : n2 Generic Map (tplh2, tphl2) Port Map fa, (m2, im3);
Passing Values From Higher Level Specs

g3 ; n2 Generic Map (tplh2, tphl2) Port Map P (a, gt. im4);


g4 : n2 Generic Map (tplh2, tphl2) Port Map {im2, gt, im5);
g 5 : n3 Generic Map (tplh3, tphl3) Port Map {im3, im4, im5, a_gt_b);
— a_eq_b output
g6 : n3 Generic Map (tplh3, tphl3) Port Map (im1 , im2, eq, im6);
g7 : n3 Generic Map (tplh3, tphl3) PORT MAP (a, b, eq, Im7);
gS : n2 Generic Map (tplh2, tphl2) PORT MAP (im6r im7. a eq b):
— a_lt_b output
g9 : n2 Generic Map (tplh2, tphl2) Port Map {im1, b, imB);
g10 : n2 Generic Map (tplh2, tphl2) PORT MAP (Im1, It, Im9);
g11 : n2 Generic Map (tplh2, tphl2) PORT MAP (b, It, im10);
g12 : n3 Generic Map (tplh3, tphl3) PORT MAP (imB, Im9, ImlO, a_lt_b);
END passed_delay,

* Componentdeclarations include GENERICs


•Component instantiations include passed values
•GENERIC maps are required 4-70
Passing Values Through Component
Defaults ...
ARCHITECTURE iterative OF nibble_comparator IS
Component compl
Generic (tplhl : Time := 2 ns; tplh2 : Time:= 3 ns; tplh3 : Time:= 4 ns;
tphll : Time:= 4 ns; tphl2 : Time:= 5 ns; tphl3 : Time:= 6 ns);
Port (a, b, gt, eg, It : in Bit; a_gt_b, a_eq_b, a_lt_b : Out Bit);
END Component;
FOR ALL : compl USE ENTITY WORK.bit_comparator_t
(passed_delay);
SIGNAL im : BITVECTOR ( 0 TO 8);
BEGIN
cO: compl Port Map (a(0), b(0), gt, eq, It, im(0), im(1), im(2));
c1to2: FOR i IN 1 TO 2 GENERATE
... Passing Values Through Component
Defaults
c: compl PORT MAP (a(i), b(i), im(i*3-3), im(i*3-2), im(i*3-1), im(i*3+0),
im(i*3+1), im(i*3+2) );
END GENERATE;
c3: compl PORT MAP (a(3), b(3), im(6), im(7), im(8), a_gt_b, a_eq_b,
a_lt_b);
END iterative;

•Using bit_comparator_t in a larger design


•Specification of GENERIC parameters is Required
•Exclusion of GENERIC Map leaves all parameters
OPEN
•Association with OPEN causes default values to be
used
Configuration Declarations
USE WORK.basic_utilities.ALL; - Grants Entities Visibility
ARCHITECTURE customizable OF nibble_comparator_test_bench IS
Component comp4 PORT (a9 b ; IN bit_vector (3 DOWNTO 0); gt, eq, It : IN
BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END Component;

SIGNAL a, b : IBIT_VECTOR (3 DOWNTO 0);


SIGNAL eql, Iss, gtr : BIT;
SIGNAL vdd: BIT := '1';
•A general purpose testbench
(comp4 component is unbound )
SIGNAL gnd : BIT := 'O';
•Configure it to test any of the
previous nibble_comparators
BEGIN
a1: comp4 PORT MAP (a, b, gnd, vdd, gnd, gtr, eql, Iss);
apply_data (a, 00&15&15&14&U&14&14&10&00&15&00&00&15, 500 NS);
apply_data (b, 00&14&14&15&15&12&12&12&15&15&15&00&00, 500 NS);
END customizable-,
A 7A
Syntax of Configuration Declaration

configuration
dedorodan
Customizable Testbench
Configuration Declaration
Configuration functional OF
nibble_comparator_test_bench IS
Configuration of testbench
FOR customizable requires binding of a1:comp4
FOR a1 : comp4
USE ENTITY WORK.nibble_comparator
(structural);
Testbench configured for
END FOR: Structural ARCHITECTURE of
END FOR; nibble_comparator
END functional;

Configuration average_delay OF
nibble_comparator_test_bench IS
FOR customizable
FOR a1 : comp4 Testbench configured for
USE ENTITY WORK.nibblecomparator iterative ARCHITECTURE of
(iterative ); nibble_comparator
END FOR;
END FOR;
END functional; 4-75
Configuration Nesting ...
ARCHITECTURE flexible OF nibble_comparator IS
Component compl
Port (a, bf gta eqa It : in Bit; a_gt_bf For flexible> No particular
a_eq_ba a_lt_b : out Bit);; bitcomparator is specified
END Component; Using customizable testbench
SIGNAL im : BIT_ VECTOR ( 0 TO S ); creates flexibility for:
Mi
1) Specifying nibble_comparator for
testbench
BEGIN 2) Specifying bit_comparator for
cO: compl Port Map (a(0), b(0)? gtT eqT ltr nibble_comparator
im(0)a im(1), im(2));
c1to2: FOR i IN 1 TO 2 GENERATE
c: compl Port Map (a(i), b(i). im(i*3-3),
im(i*3-2)a im(i*3-1), im(i*3+0)s im{i*3+1)T im(i*3+2) );
END GENERATE;
c3: compl Port Map (a(3), b(3>, im(6), im(7)r im(S)T a_gt_ba a_eq_ba a_lt_b);
END flexible; 4-77
... Configuration Nesting
USE WORK. ALL; - Grant Entities Visibility
Configuration default_bit_level Of nibblecomparatortestbench IS
FOR customizable
FOR a1 : comp4
USE ENTITY WORK.nlbble_compar ato r(flejfitp/e);
FOR flexible
FOR cO, c3: compl
USE ENTITY WOR K.bi t_c ompa rator (defauI t_de Ia jr);
END FOR;
FOR c1to2 - Grants Generate Block Visibility
FOR c: compl
USE ENTITY WORK.bit_comparator (default_delay);
END FOR;
END FOR; Configuring customizable testbench for testing
END FOR; default_delay bit_comparator instantiated through
END FOR; flexible nibble_comparator
END FOR; Visibility is obtained before component configuration
END default_bit_level; is done
Configurations and Generics
USE WGRK.ALL; - Grant Entities Visibility
Configuration passed_bit_level Of nibble_comparator_test_beneh IS
FOR customizable
FOR a1 : comp4
USE ENTITY WORK jiibble_comparatorfflejrtf>te);
FOR flexible
FOR tO, c3: compl
USE ENTITY workbit_comparator_t (Passed_delay)
GeneiNc Map (tplhl => 2 NS, tplh2 => 3 NS, tpTh3
=> 4 NS, tphll => 4 NS, tphl2 => 5 NS, tphl3

END FOR;
FOR t1to2 - Grante Generate Block Visibility
FOR t: compl
USE ENTITY work.bit_comparator_t (Passed_delay)
Map {tplhl => 2 NS, tplh2 => 3 NS, tplh3 => 4 NS, tphll => 4 NS, tphl2 => 5 NS, tphl3

END FOR;
hitcomparatort uses GENERIC parameters, Configure for;
END FOR;
END FOR; Component binding, and
END FOR; GENERIC Map specification
END FOR;
_ _
END passed bit level;
N-biit Register Example ...

d latch

n_bit register

•NAND gates form sr_latch


•Add an inverter to form d latch
•/? d_latch structures form an n-bit register
N-bit Register Example

ENTITY srjatch IS ENTITY djatch IS


PORT (sf rf c : IN BIT; q : OUT BIT); PORT (dr c : IN BIT; q : OUT BIT);
END srjatch; END djatch;
ARCHITECTURE gatejevel OF ARCHITECTURE sr_based OF
srjatch IS djatch IS
Component n2 Component sr
Port 01, 12; IN Bit; o1: OUT Bit): Port (st r, c : in Bit; q : out Bit);
End Component; End Component;
SIGNAL im1f im2f im3, ImA : BIT; Component n1
BEGIN Port fit: in Bit ; of: out Bit);
g1 : n2 Port Map ( s, cf im1); End Component;
g2 : n2 Port Map (r c; im2); SIGNAL dbar : BIT;
p3 : n2 Port Map (im1t im4f im3); BEGIN
g4 : n2 Port Map (im3t im2r im4); c1 : sr Port Map (d, dbar, c, q);
q <- im3; c2 :n1 Port Map (d. dbar):
END gatejevel; END sr_based;
N-bit Register Example
ENTITY d_registef IS
PORT (d . in Bit_Vector; c ; in Bit; q : out Bf (Vector );
END deregister;

ARCHITECTURE latchjased OF d_register IS


Component dl PORT (d, c : in Bit; q : out Bit);
End Component;
BEGIN
dn . FOR i IN d'RANGE GENERATE
di : dl PORT MAP (d(i), cp q(i));
END GENERATE;
END fatchbased;

*gate_ievel srjatch uses unbound gate components


*sr_based djatch uses unbound srjatch and gate
*Iatch_based d_register uses unbound djatch components
USE WORK.ALL; Configuration
CONFIGURATION average_gate_delay OF d_register IS
FOR latch based -Architecture name
FOR dn - Generate Visibility
FOR di : dl -
USE ENTITY WORK.dJatch(srJbased);
FOR sr based -
FOR c1 : sr -
USE ENTITY WORK.sr_latch(gafe_/eve/);
FOR gatejevel -
FOR g2, g4 : n2 USE ENTITY WORK.nand2_t (average_delay)
GENERIC MAP (5 NS, 6 NS);
END FOR;
FOR g1, g3 : n2 USE ENTITY WORK.nand2_t (average_delay)
GENERIC MAP (2 NS, 4 NS);
END FOR;
END FOR; To avoid timing
END FOR; problem; g2rg4
delays are at 5NS,
FOR c2 : n1
6NS while g1tg3
USE ENTITY WORK.inv_t(average_delay) delays are at 2NS,
GENERIC MAP (3 NS, 5 NS); 4NS
END FOR;
END FOR;
END FOR;
END FOR; END FOR;
END average_gate_delay;
Selective Configuration of Generate-
Statement Instances
■ Example: Parity checker

ENTITY xor2_t IS ENTITY inv_t IS


GENERIC (tplh : TIME := 9 NS; tpht : GENERIC (tplh : TIME “ 5 NS; tpht :
TIME := 7 NS); TIME := 3 NS);
P0RT(i1t i2 : IN BIT; o1 : OUT BIT): PORT (H : IN BIT; o1 : OUT BIT);
END xor2_t; END inY_t;

ARCHITECTURE average_delay OF ARCHITECTURE average_detay OF


xor2_t IS inv_t IS
BEGIN BEGIN
o1 <= i1 XOR \2 AFTER (tplh + tpht) / o1 <= NOTH AFTER (tplh + tphl) /
2; 2;
END average delay: END average delay;

Develop an eight bit parity checker


Use an XOR gate and an inverter A OC
8-bit Parity Checker

ENTITY parity IS
Port (A : In Bit_Vector (7 Downto 0); Odd, Even : Out Bit);
END parity;
... 8-bit Parity Checker ...
ARCHITECTURE iterative OF parity IS
Component X2
Port (11, 12: In Bit; 01: Out Bit);
End Component;
Component N1
Port (11: In Bit; 01: Out Bit);
End Component;
SIGNAL im : BIT_VECTOR ( 0 TO 6 );
BEGIN
first x2 PORT MAP (a(0), a(1), im(0)};
middle. FOR i IN 1 TO 6 GENERATE
m: x2 PORT MAP (im(i-1), a(i+1), im(i));
END GENERATE;
last odd <= im(6);
inv. n1 PORT MAP (im(6), even);
END iterative;
8-bit Parity Checker ...
CONFIGURATION parlty_blndlng OF parity IS
FOR iterative
FOR first : x2
USE ENTITY WQRK.xor2_t faverage_delay)
•Due to fanout fast gate has a higher
GENERIC MAP (5 NS, 5 NS);
END FOR; delay
FOR middle(1 TO 5) •Element 6 of Generate statement
FOR m : x2 specifies 6 NS, 7 NS delays
USE ENTITY WORK.xor2_t (average_delay) •Other generated elements use 5
GENERIC MAP (5 NS, 5 NS); NS, 5 NS
END FOR;
Generate Index Value May be Used
END FOR;
FOR middle f 6) to Bind different instances of the
FORm : x2 Generate Statement to Different
USE ENTITY WORK.xor2_t (average_delay) Entities/Architectures
GENERIC MAP {6 NS, 7 NS);
END FOR;
END FOR;
FOR Inv : n1
USE ENTITY WORK.invj faverage_delay) GENERIC MAP f5 NS, 5 NS);
END FOR;
END FOR;
END parlty_bindlng; 4-89
Data Types
■ A Data Type defines a set of values & a set of
operations.
■ VHDL is a strongly-typed Language. Types cannot be
mixed in Expressions or in assigning values to
Objects in general
Scalar Data Types
■ SYNTAX
• TYPE Identifier IS Type-Definition
■ Numeric Data Type
• Type-Definition is a RangeConstraint as follows:
• Type-Definition := Range Initial-Value < To | DownTo> Final-
Value
■ Examples
• TYPE address IS RANGE 0 To 127;
• TYPE index IS RANGE 7 DownTo 0;
• TYPE voltage IS RANGE -0.5 To 5.5;
Predefined Numeric Data Types
■ Integer -- Range is Machine limited but At
Least -(231) To (231 - 1)
-2147483648 to 2147483647
■ Positive -INTEGERS >0
■ Natural - INTEGERS >= 0
■ Real - Range is Machine limited
-1.0E308 to 1.0E308
Number Formats
■ Integers have no Decimal Point.
■ Integers may be Signed or Unsigned (e.g. -5 356 )
■ A Real number must have either a Decimal Point, a -ive Exponent
Term (Scientific Notation), or both.
■ Real numbers may be Signed or Unsigned (e.g. -3.75 1E-9 1.5E-
12)
■ Based Numbers:
• Numbers Default to Base 10 (Decimal)
• VHDL Allows Expressing Numbers Using Other Bases
• Syntax
* B#nnnn# -- Number nnnn is in Base B
• Examples
--16#DF2# - Base 16 Integer {HEX}
8#71 34# - Base 8 Integer (OCTAL)
* 2#10011# -- Base 2 Integer (Binary)
• 16#65_3EB.37# - Base 16 REAL {HEX}
Enumeration Data Type
■ Parenthesized ordered list of literals.
• Each may be an identifier or a character literal.
• The list elements are separated by commas
■ A Position # is associated with each element in the List
■ Position #'s begin with 0 for the Leftmost Element
■ Variables & Signals of type ENUMERATION will have
the leftmost element as their Default (Initial) value
unless, otherwise explicitly assigned.
■ Examples
• TYPE Color IS (Red, Orange, Yellow, Green, Blue,
Indigo, Violet);
• TYPE Tri_Level IS ('O', '1', 'Z');
• TYPE Bus_Kind IS (Data, Address, Control);
• TYPE State IS (Init, Xmit, Receive, Wait, Terminal);
Predefined Enumerated Data Types
■ TYPE BIT IS {'O' ,1) ;
■ TYPE BOOLEAN IS (False, True) ;
■ TYPE CHARACTER IS (128 ASCII Chars );
■ TYPE Severity_Level IS (Note, Warning, Error, Failure) ;
■ TYPE Std_U_Logic IS (
'll' , - Uninitialized
X' , — Forcing Unknown
'O' , — Forcing 0
'1' , - Forcing 1
T , - High Impedence
W' , - Weak Unknown
L , -WeakO
H' , - Weak 1
, — Don't Care
);
Enumerated Data Types
■ TYPE qit IS ('O', '1', 'Z\ ’X');
• New type for multi-value logic system
• qit is type identifier
• 'O', T, ’Z', 'X' are enumeration elements
• This is enumeration type definition
• 'O' is default initial values
• Let's assume qit goes in basic_utilities
• Can develop logic gates using qit values system
Ini c 1 z X
In:
In2: 0 1 1 1 1
1 1 0 0 X
NOT NAND
2 1 ro 0 X
X 1 X X X
out
INV and NAND2 Gates Using qit
USE WORK,basic utilities. ALL;
USE WORK,basic utilities.ALL; ENTITY nand2 q IS
ENTITY inv_q IS GENERIC (tplh ; TIME := 7 NS; tphl :
GENERIC (tplh : TIME := 5 NS; TIME := 5 NS);
tphl : TIME ;= 3 NS); PORT (it \2 ; IN qit; o1 : OUT qit);
PORT (i1 : IN qit; o 1 : OUT qit); END nand2_jq;
END invq; —
— ARCHITECTURE double_delay OF
ARCHITECTURE double_delay nand2_q IS
OF inv q IS BEGIN
BEGIN o1 <= T AFTER tplh WHEN i1 = ’O' OR
ol <= '1' AFTER tplh WHEN i1 = i2 = 'O' ELSE ’O’ AFTER tphl WHEN (i1 =
V ELSE V’ AFTER tphl WHEN T AND i2 = T) OR (H = T AND i2 = rZ)
i1 = ’VORH = T ELSE X OR (i1 = 'Z' AND i2 = T) OR (i1 = rZf
AFTER tplh; AND i2 = T) ELSE X AFTER tplh;
END double delay; END double delay;
Physical Data Type
■ Specifies a Range Constraint, one Base Unit, and 0 or
more secondary units.
■ Base unit is indivisible, i.e. no fractional quantities of
the Base Units are allowed.
■ Secondary units must be integer multiple of the
indivisible Base Unit.
■ Examples
TYPE Resistance IS Range 1 To Integer’High
Units
Ohm; -- Base Unit
Kohm = 1000 Ohm; —Secondary Unit
Mohm = 1000 Kohm; —Secondary Unit
end Units ;
Predefined Physical Data Types
■ Time is the ONLY predefined Physical data type

TYPE Time IS Range -2147483647 To 2147483647


Units
fs; - Base Unit (Femto Second = 1E-15 Second)
ps= 1000 fs; — Pico_Second
ns = 1000 ps; — Nano_Second
us = 1000 ns; — Micro_Second
ms = 1000 us; — Milli_Second
sec = 1000 ms;— Second
min = 60 sec; — Minuite
hr = 60 min; — Hour
end Units ;
Example on Use of Real and Time
USE WORK.basic_utilities.ALL; - FROM
PACKAGE USE : qit
ENTITY inv_rc IS
GENERIC (cjoad : REAL := 0.066E-12); - Farads
PORT (H : IN qit; o1 : OUT qit);
CONSTANT rpu : REAL ;= 25000.0; - Ohms
CONSTANT rpd : REAL := 15000.0; - Ohms
END in vjrc;

ARCHITECTURE doubleÿdelay OF invÿrc IS


CONSTANT tpth : TIME := INTEGER ( rpu * cjoad
*1.0E15) * 3 FS;
CONSTANT tphl : TIME := INTEGER ( rpd * cjoad * Time is calculated from
* 1.0E15) * 3 FS; R and C values
BEGIN
o1 <= 'V AFTER tplh WHEN i1 = 'O' ELSE real to integer type conversion
'O' AFTER tphl WHEN H = 'V OR i1 = Z' ELSE X transition is assumed as exponential
AFTER tplh; function : takes 3 re for transition
END double defay; 8-13
Physical Type Definition Examples

TYPE capacitance IS TYPE resistance IS RANGE


RANGE 0 TO 1E16 0 TO 1E16
UNITS UNITS
ffr; — Femto Farads l_o; - Milli-Ohms (base unit)
(base unit) ohms = 1000 l_o;
pfr = 1000 ffr; k_o = 1000 ohms;
nfr = 1 000 pfr; m o - 1000 k_o;
ufr = 1000 nfr; g o - 1000 m o;
mfr - 1000 ufr; END UNITS;
far = 1000 mfr;
kfr = 1000 far;
END UNITS;
Using Physical Types
USE WORK.basic_utilities.ALL;
- FROM PACKAGE USE : qit, resistance, capacitance
ENTITY inv_rc IS
GENERIC (c_load : capacitance ;= 66 ffr);
PORT (i1 : IN qit; o1 : OUT qit);
CONSTANT rpu ; resistance := 25000 ohms; •Use physical R
CONSTANT rpd : resistance := 15000 ohms; and C types
END inv rc; •Equation converts
values to their
ARCHITECTURE double_delay OF inv_rc IS base units
CONSTANT tplh ; TIME ;= (rpu / 1 l_o) * (cjoad/ 1
ffr) * 3 FS/ 1000; •Jo * ffr requires
CONSTANT tphl : TIME := (rpd/ 1 l_o) * (cjoad/ 1 ffr) *
10 18 adjustment
3 FS/ 1000;
BEGIN
o1 <= '1' AFTER tplh WHENH = 'Op ELSE
W AFTER tphl WHEN i1 = T OR i1 = Zr ELSE
'X' AFTER tplh;
END double delay; 8-15
Composite Data Types: Arrays
■ Elements of an Array have the same data type
■ Arrays may be Single/Multi - Dimensional
■ Array bounds may be either Constrained or Unconstrained.
■ Constrained Arrays
* Array Bounds Are Specified
• Syntax:
* TYPE id Is Array (Range_Constraint) of Type;
■ Examples
* TYPE word Is Array (0 To 7) of Bit;
* TYPE pattern Is Array (31 DownTo 0) of Bit;
* 2-D Arrays col row: numeric data type
• TYPE col Is Range 0 To 255;
• TYPE row Is Range 0 To 1023;
• TYPE Mem_Array Is Array (row, col) of
■ TYPE Memory Is Array (row) of word; 8-16
Composite Data Types: Arrays
■ Elements of an Array have the same data type
■ Arrays may be Single/Multi - Dimensional
■ Array bounds may be either Constrained or Unconstrained.
■ Constrained Arrays
* Array Bounds Are Specified
* Syntax:
* TYPE id Is Array (Range_Constraint) of Type;
m Examples
* TYPE word Is Array (0 To 7) of Bit;
* TYPE pattern Is Array (31 DownTo 0) of Bit;
* 2-D Arrays col row: numeric data type
• TYPE col Is Range 0 To 255;
■ TYPE row Is Range 0 To 1023;
• TYPE Mem_Array Is Array (row, col) of
• TYPE Memory Is Array (row) of word; 8-16
Unconstrained Arrays
■ Array Bounds not specified through using the notation
RANGEo.
■ Type of each Dimension is specified, but the exact
Range and Direction are not Specified.
■ Useful in lnterface_Lists Allows Dynamic Sizing of
Entities , e.g. Registers.
■ Bounds of Unconstrained Arrays in such entities
assume the Actual Array Sizes when wired to the
Actual Signals.
■ Example
• TYPE Screen Is Array ( Integer Range<> , Integer Range<>)
of BIT;
Predefined Array Types
■ Two UNCONSTRAINED Array Types are predefined
■ BITVECTOR
• TYPE Bit_ Vector Is Array { Natural Rangeo ) of Bit;
■ String
• TYPE String Is Array ( Positive Range<> ) of Character;
■ Example
• SUBTYPE Pixel Is Bit_Vector (7 DownTo 0);
subtype of dynamic range array
Use of Unconstrained Arrays
TYPE integer_vector IS ARRAY (NA TURAL RANGE <>) of INTEGER;
PROCEDURE appiyjdata (
SIGNAL target : OUT BIT_VECTOR;
CONSTANT values ; IN integervector; CONSTANT period : IN TIME) IS
VARIABLE buf: BIT VECTOR (target'RANGE);
BEGIN
FOR i IN valuesRANGE LOOP
int2bin (values(i), buf);
target <= TRANSPORT buf AFTER i * period;
END LOOP;
END apply_data;

•Example shows use of unconstrained:


target : BIT_VECTOR
values : integer vector
•Use RANGE to look up passed range
•Range will be determined when procedure is called
Unconstrained Comparator
ENTITY n bit_compara tor IS
PORT (a, b : IN BIT_VECTOR; gt, eq, It : IN BIT;
a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END n_bit_comparator;
ARCHITECTURE structural OF n bit comparator IS *S/ze of input
COMPONENT compl
PORT (a. b, gt, eq, It : IN BIT; a_gt_b, a_eq_b, a It b : OUT BIT); vectors are
END COMPONENT; not specified
FOR ALL : compl USE ENTITY WORK.bit_comparator (functional);
CONSTANT n : INTEGER := a'LENGTH; •Comparator
SIGNAL im : BIT VECTOR ( 0 TO (n-1)*3-1); length is
BEGIN a’LENGTH
c all: FOR i IN 0 TO n-1 GENERATE
I: IF i = 0 GENERATE •Size will be
least: compl PORT MAP (a(i), b(i), gt, eq, It, im(0), im(1 ), im{2) ); determined
END GENERATE;
m: IF i = n-1 GENERATE when
most: compl PORT MAP instatntiated
L
(a(i), b(i), im(i*3-3), im(i*3-2), im(r3-1), a_gt_b, a_eq_b, a_lt_b);
END GENERATE;
r: IF i > 0 AND i < n-1 GENERATE
rest: compl PORT MAP
(a(i), b(i), im(i*3-3), im(i*3-2), im(r3-1), im{i*3+0), im(i*3+1), im(i*3+2) );
END GENERATE;
END GENERATE;
END structural; 8-20
Unconstrained Comparator Test Bench
ENTITY n_bit_comparator_test_bench IS
END n_bit_comparator_test_bench ;

USE WORK.basic_utilities.ALL;
-- FROM PACKAGE USE : apply_data which uses integer_ vector
ARCHITECTURE procedural OF n_bit_comparator_test_bench IS
COMPONENT comp_n
PORT (a, b : IN bit_vector; gt, eq, It : IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT);
END COMPONENT;
FOR a1 : comp_n USE ENTITY WORK.n_bit_comparator(structural);
SIGNAL a, b : BIT_VECTOR (5 DOWNTO ft);
SIGNAL eql, lssT gtr : BIT;
SIGNAL vdd : BIT :=*1*;
SIGNAL gnd : BIT :=*0‘;
BEGIN
a1: comp n PORT MAP (aT b, gnd. vdd, gnd, gtr, eql, Iss);:
apply_data (a, 00&15&57&17, 500 NS);
apply_data (b, 00&43&14&45&11&21&44&11, 500 NS);
END procedural;
SIGNAL a determines size of comparator
SIGNAL a determines target size of apply data
SIGNAL b determines target size of apply data
Concatenated integers form lnteger_vector 8-21
Referencing Arrays & Array Elements ...

■ VHDL allows referencing an Array in its Entirety or by a


SLICE, or Element.
■ Examples
• TYPE clockstate IS (Low, Rising, High, Falling);
• TYPE ConversionArray IS Array (Clock state) of Bit;
.
• Signal C_A : Conversion_Array := {'O' 1'. O', 1) ;
• C_A <= (' 1\ '1\'0\'0'); -- Positional Association List
* C_A <= (Low => ‘O', Rising => 1', High => *1\ Falling => ’O');
-- Named Association List
* C_A <= (Low => 'O', High => 'O', OTHERS=> '1');
-- Alternative 3
• C_A(Low) <= 'O';
• TYPE Register4 IS Array (3 Downto 0) of Bit;
• TYPE Reg4 IS Array (0 To 3) of Bit;
• Signal A: Register := ('O' , '1', '0‘, '1') ;--A(0)='1\ A(3)='0'
•Signal B: Reg4 := ('O' , '1', 'O', '1') ;~B(0)='0\ B(3)='1'
... Referencing Arrays & Array Elements
■ 2-D Arrays
• TYPE Reg32 Is Array (31 DownTo 0) of Bit;
• TYPE ROM Is Array (0 To 3) of Reg32;
* TYPE ROM2 Is Array (0 To 4 , 0 To 2) of Bit;
• Signal A: ROM := (X”2F3C_5456” , X'FF32_E7B8” ,
X"109A_BA15" , X“FFFF_FFFF” );
•Signal B: ROM2 := ( ('1', 'O', '0'),
C0V1V0'),
C0V1V1',
civovn
f 1* , *1', M*) ) ;
• B(1 , 2) <= 'O' ; — Referencing a 2-D Array Element
Examples on Referencing Arrays ...
■ TYPE qit IS (‘O’ , T , ‘Z’ , ‘X’);
• TYPE qit nibble IS ARRAY ( 3 DOWNTO 0 ) OF qit;
• TYPE qit_byte IS ARRAY ( 7 DOWNTO 0 ) OF qit;
• TYPE qitword IS ARRAY ( 15 DOWNTO 0 ) OF qit;
• TYPE qit_4by8 IS ARRAY ( 3 DOWNTO 0 , 0 TO 7 ) OF qit;
• TYPE qit_nibble_by_8 IS ARRAY ( 0 TO 7 ) OF qit_nibble;
• SIGNAL sq1 : qit ;
• SIGNAL sq4 : qit_Nibble ; Direction of
• SIGNAL sq8 : qit_byte := "ZZZZZZZZ" ; indexing
• SIGNAL sq16 : qit word ; must be as
• SIGNAL sq nibble S : qit_nibble_by_8 ; declared
• sq8 <= "Z101000Z" ;
• sq8 <= sq16 (11 DOWNTO 4); — middle 8 bit slice of sq16 to sq8
• sq16 (15 DOWNTO 12) <= sq8(5 DOWNTO 2) ; - sq8 middle
nibble into left 4 bit slice of sq16
• sq4 <= sq_nibble_8(2) third nibble of sq_nibble_8 into sq4
• sq1 <= sq_nibble_8 (2)(1) ;
... Examples on Referencing Arrays ...
■ The following signal declarations are equivalent:
• Signal sq8 : qit_byte := “ZZZZ1111”;
• Signal sq8 : qit_byte := ('Z\ ’Z', ’Z’, '71, *1’, T, T, ‘1’);
* Signal sq8 : qit_byte := (Z’&'Z’&’Z’&'Z’&T&T&T&T);
• Signal sq8 : qit_byte := (7 Downto 4 => ‘Z\ OTHERS => T);
■ Index range can be in any direction as long as it covers
valid array indexes
• Signal sq8 : qit_byte := "111XX1ZZ”;
• Signal sq8 : qit_byte := (1 Downto 0 => Z\ 3 To 4 => ‘X’,
Others => T);
... Examples on Referencing Arrays ...
■ TYPE qit IS {‘0’ ,‘V ,‘Z’ , ‘X’);
• TYPE qit_nibble IS ARRAY ( 3 DOWNTO 0 ) OF qit;
• TYPE qit_byte IS ARRAY ( 7 DOWNTO 0 ) OF qit;
• SIGNAL sq4 : qit_Nibble ;
• SIGNAL sq8 : qit_byte ;
• sq8 <= sq8 (0) & sq8 (7 DOWNTO 1) ; — right rotate sq8
• sq4 <= sq8 (2} & sq8 (3) & sq8 (4) & sq8 (5) ; -- reversing sq8 into sq4

aq4: sq8:
IeI5 * a I2
' '

2 1 0 7 i a

Concatenation operator “&”can be used for


shift and rotate
... Examples on Referencing Arrays ..
• TYPE qit_4by8 IS ARRAY ( 3 DOWNTO 0 , 0 TO 7 ) OF qit;
— 2-D array
• SIGNAL sq_4_8 : qit_4by8 :=
(

( 'O', 'O', T, '1 ’Z’, Z’, 'X', ’X’ ), - sq_4_8 {3, 0 TO 7)

( ’X’, 'X', 'O', 'O', T, T, 'Z\ 'Z' ), - sq_4_8 {2, 0 TO 7)

( 'Z', '71, 'X', 'X', ’O', ’O', T, ’1’ ), - sq_4_8 (1 , 0 TO 7)

( T, ’1’, ’Z’, '71, 'X', 'X', ’O', ’0’ ) - sq_4_8 (0, 0 TO 7)

);

•Use nested parenthesis for multidimensional arrays


•Deepest set of parenthesis corresponds to right most index
... Examples on Referencing Arrays
■ Initializing a two-dimensional array
• SIGNAL sq_4_8 : qit_4byS := (Others => "11000000”);
• SIGNAL sq_4_8 : qit_4by8 := (Others => (Others => ‘Z’));
• SIGNAL sq_4_8 : qit_4by8 := (Others => (0 To 1 => T,
Others => ‘0’));
■ Signal assignment using Others
* sq_4_8 <= (3=> (Others => ‘X’), 0 => (Others => 'X'), Others
=> (0 => ‘X’, 7 => 'X', Others => T»;
Using Enumeration Types for Indexing
■ Can use enumeration types for indexing
■ TYPE qit_2d IS ARRAY (qit, qit) OF qit;
• Use qit for indexing
* Upper left most element is indexed by ('070')
,Q. I1P >ZP .x.
element ('Z\ 'Z1)

■ If qc is a signal of type qit_char,


* TYPE qit_char IS ARRAY (CHARACTER) OF qit;
• Then, qc('A') indexes a qit value in the qc array
Using Enumeration Types for Indexing
■ Can use enumeration types for indexing
■ TYPE qit_2d IS ARRAY (qit, qit) OF qit;
• Use qit for indexing
* Upper left most element is indexed by (’0’,'0')
'O’ 'li i"
PXF

element ('Z\ 'Z1)

■ If qc is a signal of type qit_char,


• TYPE qit_char IS ARRAY (CHARACTER) OF qit;
* Then, qc('A') indexes a qit value in the qc array
8-29
NAND2 Using qit_2d
USE WORK.basic_utilities.ALL;
- FROM PACKAGE USE: qit, qit 2d
ENTITY nand2 q IS
GENERIC (tplh : TIME := 7 NS; tphl : TIME := 5
NS);
PORT ( i1, \2 : IN qit; o1 : OUT qit); CONSTANT qit nand2 table :
END nand2_q; qit 2d := ( V’ => (Others =>’V),
ARCHITECTURE average delay OF nand2_q IS X' => (‘0’ => T} Others -> X),
CONSTANT qit nand2 table ; qit_2d := ( Others => ('O’ => ‘1 X’ => X\
-'O' TZ'X Others => V));

(T, 'V, T, T), - 'O'


('1\ '0\ 'O', 'X'), - 'V
(T, 'O', 'O', 'X'), - 'Z'
(T, 'X', 'X', X)); -'X'
BEGIN
o1 <= qit nand2 table (H, 12) AFTER (tplh + tphl)
/2;
END average delay; 8-30
Records
■ Elements of a Record are Heterogeneous (not
Necessarily of the Same Data Type).
■ Examples
• TYPE opcode Is ( STA, LDA, ADD, JMP);
• TYPE mode Is Range 0 To 3;
• SubType Address Is Bit_Vector(7 DownTo 0);
• TYPE Instruction Is
• Record
OPC: opcode ;
M : mode ; -- Addressing mode
OP1, OP2 : Address ;
* End record ;
Referencing Record Elements
■ TYPE lnstr_Q Is Array (0 To 15) of Instruction ;
■ SIGNAL IQ : lnstr_Q ;
■ IQ(0) <= (LDA, 2, x”F3", x"13 "); -Positional
Association
■ Alternatively
• IQ(0).OPC <= LDA;
• IQ(0).M <= 2;
* IQ(0).OP1 <= X”F3”;
• IQ(0).OP2 <= X”13” ;
■ Alternatively
• IQ(0) <= (M => 2,OP2 => X”13", OPC => LDA, OP1 =>
X"F3”); -Named Association
Aliasing ...
■ Alias declaration selects part of an object
■ Use for renaming, for convenience
■ Alias declaration can be used for signals, variables,
and constants
■ Alias declaration specifies an identifier, its type, name
of object identifier is alias of
■ Example
• ALIAS cflag : BIT IS flag_register (3);
• ALIAS v_flag : BIT IS flag_register (2);
• ALIAS n_flag : BIT IS flag_register (1);
* ALIAS z_flag : BIT IS flag_register (0);
... Aliasing
■ ALIAS page : BIT_VECTOR (2 DOWNTO 0) IS instr.adr (10
DOWNTO 8);
■ ALIAS offset : BIT_VECTOR (7 DOWNTO 0) IS instr.adr (7
DOWNTO 0);
■ page <= ”001"; - 3 bits
■ offset <= X"F1"; - 8 bits
■ offset <= B"1111JJ001 - 8 bits
151413 '1211 10 09 08 07 06 05 04 03 02 01 00 I
opcode mode page offset
address

•Use aliasing to separately name page and offset


•AH references to page refer to 1 0:8 of address
■ All references to offset refer to 7:0 of address
8-34
Subtypes
■ A SUBTYPE defines a SUBSET of values defined by a
TYPE declaration.
■ Subtypes of Subtypes are also possible
■ SUBTYPE = Constrained "TYPE” or "SubType"

Example (i) Range Constrained Subtypes


SubType Lower Case Is Character Range a' To 'z';
SubType Positive Is Integer Range 1 To Integer'High;
SubType Natural Is Integer Range 0 To Integer'High;

Index Constrained Subtypes


Example (ii)
SubType Byte Is Bit Vector (7DownToO); 8-35
Type Compatibility & Conversion
VHDL is a strongly-typed language.
Compiler flags an Error whenever different types are
mixed.
Subtypes are Type compatible with their higher level
Subtypes and their Root Type.
Two Subtypes of the same type are Type-Compatible

8-36
Important Type Compatibility Rules
■ Type of an Expression assigned to an Object must be the Same as, or
compatible with, the Type of the Object.
■ Operands of Predefined Operators Must be of the Same or compatible
Type
■ The Type of an Actual Signal is The SAME as, or compatible with, the
Type of the Formal Port it Connects To.
■ Example

• SubType XJnt Is Integer Range 1 To 30;


• SubType YJnt Is Integer Range 1 To 30;
• Type X2 int Is Range 1 To 30;
• Type Y2 int Is Range 1 To 30;
• SubType Z int Is XJnt Range 1 To 20;

• Signal I : Integer;
* Signal x : X int;
• Signal y : Y int;
• Signal z : Z int;
• Signal x2 : X2Jnt;
• Signal y2:Y2Jnt; 8-37
... Important Type Compatibility Rules
■ x <= z ; -- Legal Since ZJnt is a Subtype of X
■ x <= y ; --Legal
■ x2 <= y2; --Illegal, Operands are not compatible
■ I <= x + z ; -- Legal, both x and z are Vertical
subtypes of Integer
■ I <= x + y ; -- Legal, Operands are subtypes of same
type
■ I <= x2 + y2 ; -- Illegal, Operands are not compatible
■ z <= x ; -- Legal, value of x should be within the
range of z
■ z <= y ; -- Legal, value of y should be within the
range of z
Closely Related Types ...
■ Any two Numeric types are closely related
■ Closely related types can be Casted to each other
• Assume I is integer and X is real
• I := Integer(X); ~ Rounds X
• X :=Real(l);
• I := lnteger(3.5); --Ambiguous (Implementation Dependent)
■ Array Types are closely related iff:
• Same dimensionality
• Index Types are closely related for each dimension
• Elements Types are the same or compatible
... Closely Related Types
■ Example
* Type Minuites Is Range 0 To 59;
* Type Seconds Is Range 0 To 59;
* SubType X int Is Integer Range 1 To 30;

* Variable x : XJnt;
* Variable M : Minuites;
• Variable S : Seconds;;
* Variable I : Integer;

* —
I := 6Q*M + S; Illegal M & S are incompatible types
• I := 60*lnteger(M) + Integer(S); -- Valid
* I := M; — Illegal - Minuites is not a “SubType” of Integer
* M := 60*S; -- Illegal - Minuites & Seconds are not Compatible
* M := Minuites(S/60); — legal -Casting Closely Related Types
* M := x; — Illegal - Minuites & X int are not Type Compatible
* M := Minuites(x); — legal -Casting Closely Related Types
Mixed Type Arithmetic
■ Explicit Type Conversion is done between Closely-Related Types,
e.g. REALS & INTEGERS
■ Example:
* Variable x, y : Real;
* Variable n,m : Integer;
* n := INTEGER (x) * m; -- x is first converted to Integer
* y := REAL (n) * x; —
n is first converted to Real
■ Example:
• TYPE qitbyte IS ARRAY ( 7 DOWNTO 0 ) OF qit;
• TYPE qitoctal IS ARRAY ( 7 DOWNTO 0 ) OF qit;
* Signal qb: qit byte;
* Signal qo: qit octal;
* qb <= qit_byte(qo); - - Explicit Type Conversion (Type Casting)
-- of closely-related types
* qb <= qit_byte(OTHERS => AX'); - - Illegal type conversion
Custom Type Conversion
■ Custom Type Conversions can be defined Using either:
• Constant Conversion Arrays, or
• Subprograms (Functions or Procedures)
Type Conversion Using Functions
Type MVL4 ('X', 'O', '1', Z);
Function Bit_To_ MVL4
Function MVL4_To_Bit(B: in MVL4)
(B: in Bit) Return MVL4 IS
Return Bit IS
Begin
Begin
Case B is
Case B is
when O' => return O';
when 'X' => return O';
when T => return '1';
when O' => return 'O';
End Case;
when ’1' => return '1';
End MVL4_To_Bit ;
when Z' => return 'O';
End Case;
End MVL4_To_Bit ;

Signal B4: MVL4;


Signal B: Bit;
B <= MVL4_To_Bit(B4);
B4 <= Bit_To_ MVL4 (B);
8-43
Attributes of Types and SubTypes

T'LEFT : Left Bound of Scalar Typo T.


V RIGHT: Right Bound of Scalar Type T.
T’HJGH: Upper Bound of Scalar Type T, i.e. highest
value
T’LOW: Lower Bound of Scalar Type T, i.e. lowest
value
TTOS(V): Position of value V in Type T
T’VAL(P): Value of Type T at Position P
T’SUCC(V): Value after value V in Type T, i.e., if V at
position X in base of type, SUCC(V) will be
the value at position X+l
T'PRED(V): Value before value V in Type T, i.e., if V at
position X in base of type. PRED(V) w ill be
the value at position X-l
T'LEFTOF(V Value left of value V in Type T
T'RIGHTOF(V): Value right of value V in Type T
T'BASE: Base Type of Type T. Only Legal When Used
As Prefix To Another Attribute; e.g..
T'BASE'RIGHT.
Attributes of Types and SubTypes
■ EXAMPLES
• TYPE UP IS Range 0 To 7;
• TYPE Down IS Range 7 DownTo 0;
• TYPE Color IS (Red, Orange, Yellow, Green, Blue, Indigo, Violet);
0 1 2 3 4 5 6
• SubType ColorUP Is Color Range Orange To Indigo;
• SubType ColorDN Is Color Range Indigo DownTo Orange;
Color Pos(Creen) = 3

Color Left * Red


ColorUP Left * Orange
ColorD V Left = Indigo

L'P’Uelt = 0
Down1 Left » 7

I P Low * 0
Down" Low “ 0
Color1 Low “ Red
ColorUP Low = Orange
CojorDNXow - Orange
LPSuce(6) = 7
LPPred(6) = 5
ColorUP Suee(Bluc)= Indigo
ColorUP Pnd(B]iic>= Creen

Dow nSucc(6) = 7
Down Pred{6) = 5
1

ColorDN1 Succ(Blue)= Indigo


ColorDN1 PredfBlue)* Green
Examples
■ TYPE qit IS ('O', T, 'Z\ ’X’);
■ SUBTYPE tit IS qit RANGE ‘O' TO 'Z';
• Tit’Base qit
* Tit’Left ‘O’
• QitLeft ‘O’
• Tit’Right Z
• Qit’Right ‘X1
• Tit’High Z
• Qit'Low £0’
• Qit'Pos(X’) 3
• Tit’PosCX’) Error, out of range
• QitVal(3) ‘X1
• Tit’Val{3) Error, out of range
• Tit’Leftof(T) ‘0’
• Tit’Leftof(‘0’) Error
• Tit’Rightof{‘Z') Error, out of range
Array Attributes
■ Find Range, Length, Boundary of an Array Object or
Array Type
■ Follow attribute by ( ) to specify index
Left Bound of The Nlh Index (d‘ the Array
Object or Subtype. Optional Parameter.
[default is 1.
A'RIGHT(N) Right Bound of The Nth Index ef Array Object
or Subtype. Optional Parameter. Default is 1.
A'HIGH(N) Upper Bound of Nth Index of Array Object or
Subtvpc. Optional Parameter. Default is 1.
A'LOW(N) Lower Bound of Nctl Index of Array Object or
Subtvpc. Optional Parameter. Default is 1.
A'RANGE(N) Range of N*h Index of Array Object or
Constrained Array Subtype
Ascending: Left Bound To Right Bound.
Descend: Left Bound Down to Right Bound
A'REVERSE _ RAJNOE(N) Identical To AfRANGE(N) Except Range Is
Reverse; /.t*..
Ascending. Right Sound Dow n to Left Bound
Descending. Right Bound To Left Bound _
A'LENGTH(N) Number of Values In The Nth Index Of Array
Object or Constrained Array Subtype.
Optional Parameter. Default is 1.
Array Attributes
■ TYPE qit_4by8 IS ARRAY (3 DOWNTO 0, 0 TO 7) OF qit;

Attribute Description Example Result

'LEFT Left bound iq_4J'I.EFT(l) 3


TIGHT Right bound sqjl □ RIGHT
1
CT
jq 4 8 ' RIGHT(2) 1
'HIGH Upper bound sq 4 B'HISH(2) 7
'LOU Lower bound 'LOWS(2) 0
'RANGE Range sq_4 8 ' RANGE(2 ) 0 TO 7
sq_4J ' RAHSE( 11 3 DOWNTO C
'REVERSE_RANGE Reverse Range jqjl tt ' REVERSE RANGE ( 2 ) 7 DOWNTO U
?q_4_3'REYERSE_RANGE(l) 0 TO 3
'LENGTH Length 'LENGTH 4
Signal Attributes
■ SIGNAL S1 : BIT;
At.tr mute T/E tHairnHe Kind Tirue
description

" DELAYED - si ' DELAYED{ 5 NS > SIGNAL As si


A copy of si , but delayod by 5 NS . I f no parajneter or 0 ,
delayed tty delta. Equiv*.lent to TRANSPORT delay of si .

' STABLE EV si1 ST ABLE(5 NS > SIGNAL BOOLEAN-


A signal that is TRUE if si has net changed in the last £ NS .
If used with, no parameter or 0 , the resulying signal is TRUE
if si has not changed in the current Simulation time.
' EVENTS EV si EVENT
1
Va 1 lie BOOLE Ah
If si changes in the cur-rent simuLat ion cycle, si ' EVENT will
he TRUE for- this cycle ( delta t rme ) .
1
LAST_EVEWT EV si ■
LAST_EVENT Value T ime
The dwcvrit of time since the lest value change on si If
si EVENT is TRUE , the value of si ' LAST_EVEMT is 0.

LA5T_VALUE EV si ' LAST_ VALUE Value As s 1
The value of si bef ore the most recent event occurs on it .
Signal Attributes

Attribute T/E Example Kind Type


Description

■QUIET TR si QUIET( 5 NS) SIGNAI BOOIEAf


1

A signal that is TRUE if no transaction has been placed


on si in the last 5 NS. If no parameter of 0, for current
simulation cycle is assumed.
■ACTIVE TR si ACTIVE Value BOOLEAN
If si has had a transaction in the current simulation cycle,
si'ACTIVE trill be TRUE for this Simula t ion cycle, for * time.
' IAST_ ACTIVE TR si 1AST_ ACTIVE
1
Value Time

Tthe amount of tine since the last transaction occurred on si .


If si 'ACTIVE is TRUE, si 'LAST_ACTIVE is 0.
TRANSACTION TR si TRANSACTION
1
SIGNAL BIT
A signal that toggles each time a transaction occurs on si